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Электронный компонент: ICS87946I

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ICS87946I Final Data Sheet
background image
87946AYI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 22, 2002
1
Integrated
Circuit
Systems, Inc.
ICS87946I
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87946I is a low skew, 1, 2 LVCMOS
Clock Generator and a member of the
HiPerClockSTM family of High Performance Clock
Solutions from ICS. The ICS87946I has two select-
able single ended clock inputs. The single ended
clock inputs accept LVCMOS or LVTTL input levels. The low
impedance LVCMOS outputs are designed to drive 50
series
or parallel terminated transmission lines. The effective fanout
can be increased from 10 to 20 by utilizing the ability of the
outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the 1,
2 or a combination of 1 and 2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87946I is characterized at 3.3V core/3.3V output. Guar-
anteed output and part-to-part skew characteristics make the
ICS87946I ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
F
EATURES
10 single ended LVCMOS outputs, 7
typical output
impedance
Selectable CLK0 and CLK1 LVCMOS clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
Maximum input/output frequency: 150MHz
Output skew: 350ps (maximum)
3.3V input, 3.3V outputs
-40C to 85C ambient operating temperature
Pin compatible to the MPC946
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
DIV_SELA
DIV_SELB
DIV_SELC
MR/nOE
QA0:QA2
QB0:QB2
QC0:QC3
CLK_SEL
CLK0
CLK1
32-Lead LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
HiPerClockSTM
,&6
0
1
1
2
0
1
0
1
0
1
32 31 30 29 28 27 26 25
9 10 11 12 13 14 15 16
1
2
3
4
5
6
7
8
24
23
22
21
20
19
18
17
GND
QB0
V
DDB
QB1
GND
QB2
V
DDB
V
DDC
CLK_SEL
V
DD
CLK0
CLK1
DIV_SELA
DIV_SELB
DIV_SELC
GND
QC3
GND
QC2
V
DDC
QC1
GND
QC0
V
DDC
V
DDA
QA2
GND
QA1
V
DDA
QA0
GND
MR/nOE
ICS87946I
background image
87946AYI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 22, 2002
2
Integrated
Circuit
Systems, Inc.
ICS87946I
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
1. P
IN
D
ESCRIPTIONS
T
ABLE
2. P
IN
C
HARACTERISTICS
T
ABLE
3. F
UNCTION
T
ABLE
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background image
87946AYI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 22, 2002
3
Integrated
Circuit
Systems, Inc.
ICS87946I
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V0.3V, T
A
= -40C
TO
85C
T
ABLE
4B. LVCMOS DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V0.3V, T
A
= -40C
TO
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H
O
e
g
a
t
l
o
V
h
g
i
H
t
u
p
t
u
O
I
H
O
A
m
0
2
-
=
5
.
2
V
V
L
O
e
g
a
t
l
o
V
w
o
L
t
u
p
t
u
O
I
L
O
A
m
0
2
=
4
.
0
V
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
DD
-0.5V to V
DD
+ 0.5 V
Outputs, V
DDx
-0.5V to V
DDx
+ 0.5V
Package Thermal Impedance,
JA
47.9C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
background image
87946AYI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 22, 2002
4
Integrated
Circuit
Systems, Inc.
ICS87946I
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
T
ABLE
5. AC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V0.3V, T
A
= -40C
TO
85C
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.
background image
87946AYI
www.icst.com/products/hiperclocks.html
REV. B OCTOBER 22, 2002
5
Integrated
Circuit
Systems, Inc.
ICS87946I
L
OW
S
KEW
,
1,
2
LVCMOS C
LOCK
G
ENERATOR
t
PD
V
DD
2
V
DD
2
P
ARAMETER
M
EASUREMENT
I
NFORMATION
O
UTPUT
R
ISE
/F
ALL
T
IME
Propagation Delay
Clock Outputs
0.8V
2.0V
2.0V
0.8V
t
R
t
F
V
SW I N G
tsk(o)
V
DD
2
V
DD
2
Qx
Qy
O
UTPUT
S
KEW
P
ART
-
TO
-P
ART
S
KEW
3.3V O
UTPUT
L
OAD
AC T
EST
C
IRCUIT
SCOPE
Qx
LVCMOS
V
DD
,
V
DDx
=
1.65V0.15V
GND = -1.65V0.15V
x
x
Qx
Qy
PART 1
PART 2
tsk(pp)
V
DD
2
V
DD
2
x
x
QAx, QBx,
QCx, QDx
CLK0,
CLK1
x