87949AYI
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2002
1
Integrated
Circuit
Systems, Inc.
ICS87949I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
G
ENERAL
D
ESCRIPTION
The ICS87949I is a low skew, 1, 2 Clock Gen-
erator and a member of the HiPerClockSTM family
of High Performance Clock Solutions from ICS.
The ICS87949I has selectable single ended clock
or LVPECL clock inputs. The single ended clock
input accepts LVCMOS or LVTTL input levels. The PCLK,
nPCLK pair can accept LVPECL, CML, or SSTL input levels.
The low impedance LVCMOS outputs are designed to drive
50
series or parallel terminated transmission lines. The ef-
fective fanout can be increased from 15 to 30 by utilizing the
ability of the outputs to drive two series terminated lines.
The divide select inputs, DIV_SELx, control the output fre-
quency of each bank. The outputs can be utilized in the 1,
2 or a combination of 1 and 2 modes. The master reset
input, MR/nOE, resets the internal frequency dividers and also
controls the active and high impedance states of all outputs.
The ICS87949I is characterized at 3.3V core/3.3V output. Guar-
anteed output and part-to-part skew characteristics make the
ICS87949I ideal for those clock distribution applications demand-
ing well defined performance and repeatability.
F
EATURES
15 single ended LVCMOS outputs,
7
typical output impedance
Selectable LVCMOS or LVPECL clock inputs
CLK0 and CLK1 can accept the following input levels:
LVCMOS and LVTTL
PCLK, nPCLK supports the following input types:
LVPECL, CML, SSTL
Maximum output frequency: 160MHz
Output skew: 350ps (maximum)
Part-to-part skew: 2.75ns (maximum)
3.3V supply voltage
-40C to 85C ambient operating temperature
Pin compatible to the MPC949
B
LOCK
D
IAGRAM
P
IN
A
SSIGNMENT
52-Lead LQFP
10mm x 10mm x 1.4mm package body
Y Package
Top View
HiPerClockSTM
,&6
nc
V
DDD
QD4
GND
QD3
V
DDD
QD2
GND
QD1
V
DDD
QD0
GND
nc
MR/nOE
CLK_SEL
V
DD
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14 15 16 17 18 19 20 21 22 23 24 25 26
39
38
37
36
35
34
33
32
31
30
29
28
27
52 51 50 49 48 47 46 45 44 43 42 41 40
nc
GND
QC0
V
DDC
QC1
GND
QC2
V
DDC
QC3
GND
GND
QD5
nc
nc
V
DDB
QB2
GND
QB1
V
DDB
QB0
GND
GND
QA1
V
DDA
QA0
GND
ICS87949I
DIV_SELA
DIV_SELB
DIV_SELC
DIV_SELD
MR/nOE
QA0:QA1
QB0:QB2
QC0:QC3
QD0:QD5
CLK_SEL
CLK0
CLK1
PCLK
nPCLK
PCLK_SEL
0
1
1
2
0
1
0
1
0
1
0
1
R
0
1
87949AYI
www.icst.com/products/hiperclocks.html
REV. B NOVEMBER 21, 2002
4
Integrated
Circuit
Systems, Inc.
ICS87949I
L
OW
S
KEW
,
1,
2
C
LOCK
G
ENERATOR
T
ABLE
4A. P
OWER
S
UPPLY
DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V0.3V, T
A
= -40C
TO
85C
T
ABLE
4B. DC C
HARACTERISTICS
,
V
DD
= V
DD
X
= 3.3V0.3V, T
A
= -40C
TO
85C
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.
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3
.
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+
A
BSOLUTE
M
AXIMUM
R
ATINGS
Supply Voltage, V
DD
4.6V
Inputs, V
DD
-0.5V to V
DD
+ 0.5 V
Outputs, V
DDx
-0.5V to V
DDx
+ 0.5V
Package Thermal Impedance,
JA
42.3C/W (0 lfpm)
Storage Temperature, T
STG
-65C to 150C
NOTE: Stresses beyond those listed under Absolute
Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional
operation of product at these conditions or any conditions be-
yond those listed in the
DC Characteristics or AC Character-
istics is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect product reliability.
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