Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9112-06/07
Block Diagram
Low Skew Output Buffer
9112-06 9112-07 Rev H 1/22/99
Pin Configuration
16 pin SOIC
Zero input - output delay
Frequency range 25 - 75 MHz (3.3V), 30-90MHz (5.0V)
Less than 200 ps Jitter between outputs
Skew controlled outputs
Skew less than 250 ps between outputs
Available in 8 or 16 pin versions, 150 mil SOIC packages
3.3V 10%, 5.0V10% operation
The ICS9112 is a high performance, low skew, low jitter clock
driver. It uses a phase lock loop (PLL) technology to align, in
both phase and frequency, the REF input with the CLKOUT
signal. It is designed to distribute high speed clocks in PC
systems operating at speeds from 25 to
75 MHz (30 to 90mHz for 5V operation).
ICS9112 is a zero delay buffer that provides synchronization
between the input and output. The synchronization is
established via CLKOUT feed back to the input of the PLL.
Since the skew between the input and output is less than +/-
350 pS, the part acts as a zero delay buffer.
The ICS9112 comes in with two different options; dash 06
and dash 07. The dash 07 is available in a 16 pin 150 mil SOIC
package. It has two banks of four outputs controlled by two
address lines. Depending on the selected address line, bank B
or both banks can be put in a tri-state mode. In this mode, the
PLL is still running and only the output buffers are put in a
high impedance mode. The test mode shuts off the PLL and
connects the input directly to the output buffers (see table
below for functionality).
The dash 06 is an eight pin 150 mil SOIC package. It has five
output clocks. In the absence of REF input, both ICS9112-06
and -07 will be in the power down mode. In this mode, the
PLL is turned off and the output buffers are pulled low. Power
down mode provides the lowest power consumption for a
standby condition.
8 pin SOIC
2
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1
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A
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B
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Functionality (-07)
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all device
data to verify that any information being relied upon by the customer is current and accurate.
PB
ICS9112-06/07
Pin Descriptions
Notes:
1.
Guaranteed by design and characterization. Not subject to 100% test.
2.
Weak pull-down
3.
Weak pull-down on all outputs
4.
Weak pull-ups on these inputs
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3
ICS9112-06/07
Notes:
1.
Guaranteed by design and characterization. Not subject to 100% test.
2.
All Skew specifications are mesured with a 50
transmission line, load teminated with 50
to 1.4V.
3.
Duty cycle measured at 1.4V.
4.
Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
Absolute Maximum Ratings
Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . 7.0 V
Logic Inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . GND 0.5 V to V
DD
+0.5 V
Ambient Operating Temperature . . . . . . . . . . . . 0C to +70C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . 65C to +150C
Electrical Characteristics at 3.3V
V
DD
= 3.0 3.7 V, T
A
= 0 70
C unless otherwise stated
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are
stress specifications only and functional operation of the device at these or any other conditions above those listed in the
operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
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PB
ICS9112-06/07
Switching Characteristics (3.3V Continued)
Notes:
1.
Guaranteed by design and characterization. Not subject to 100% test.
2.
REF input has a threshold voltage of VDD/2
3.
All parameters expected with loaded outputs
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5
ICS9112-06/07
Notes:
1.
Guaranteed by design and characterization. Not subject to 100% test.
2.
All Skew specifications are mesured with a 50
transmission line, load teminated with 50
to 1.4V.
3.
Duty cycle measured at 1.4V.
4.
Skew measured at 1.4V on rising edges. Loading must be equal on outputs.
Electrical Characteristics at 5.0V
V
DD
= 4.5 5.5 V, T
A
= 0 70
C unless otherwise stated
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5
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4
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4
.
3
0
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4
V
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4
2
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6
A
m
PB
ICS9112-06/07
Switching Characteristics (5.0V Continued)
Notes:
1.
Guaranteed by design and characterization. Not subject to 100% test.
2.
REF input has a threshold voltage of VDD/2
3.
All parameters expected with loaded outputs
R
E
T
E
M
A
R
A
P
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B
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@
z
H
M
0
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=
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p
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C
0
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2
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0
8
0
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1
s
p
a
m
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;
r
e
t
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T
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c
0
0
0
,
0
1
@
z
H
M
0
5
-
0
2
=
F
F
p
0
3
=
L
C
4
1
0
3
s
p
7
ICS9112-06/07
Application Suggestion:
ICS9112 is a mixed analog/digital product. The analog portion of the PLL is very sensitive to any random noise generated by
charging or discharging of internal or external capacitor on the power supply pins. This type of noise will cause excess jitter
to the outputs of ICS9112. Below is a recommended lay out to alleviate any addition noise. Figure below depicts only ICS9112-
07, but similar techniques could be used for dash 06. For additional information on FT. layout, please refer to our AN07. The
0.1 uF capacitors should be connected as close as possible to power pins (4 & 13). An Isolated power plane with a 2.2 uF
capacitor to ground will enhance the power line stability.
PB
ICS9112-06/07
Ordering Information
ICS9112M-06
ICS9112M-07
Pattern Number (2 or 3 digit number for parts with ROM code patterns)
Package Type
M=SOIC
Device Type (consists of 3 or 4 digit numbers)
Prefix
ICS, AV = Standard Device
Example:
ICS XXXX M - PPP
ICS reserves the right to make changes in the device data identified in this publication
without further notice. ICS advises its customers to obtain the latest version of all device
data to verify that any information being relied upon by the customer is current and accurate.
8 pin SOIC Package
16-Pin SOIC Package
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