Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-37
0143G--08/04/04
Block Diagram
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
Pin Configuration
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPUAGP: < 1ns
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, 0.6%
Serial I
2
C interface for Power Management,
Frequency Select, Spread Spectrum.
Efficient Power management scheme through PCI and
CPU STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-37 is the single chip clock solution for
Desktop/Notebook designs using the VIA MVP3 style
chipset. It provides all necessary clock signals for such a
system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-
37 employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection. The
SD_SEL latched input allows the SDRAM frequency to
follow the CPUCLK frequency(SD_SEL=1) or the AGP
clock frequency(SD_SEL=0)
2
ICS9148-37
0143G--08/04/04
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use
10Kohm resistor to program logic Hi to VDD or GND for logic low.
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ICS9148-37
0143G--08/04/04
Functionality
V
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Crystal (X1, X2) = 14.31818MHz
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CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
5
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4
ICS9148-37
0143G--08/04/04
1.
The ICS clock generator is a slave/receiver, I
2
C component. It can read back the data stored in the latches for
verification. Read-Back will support Intel PIIX4 "Block-Read" protocol.
2.
The data transfer rate supported by this clock generator is 100K bits/sec or less (standard mode)
3.
The input is operating at 3.3V logic levels.
4.
The data byte format is 8 bit bytes.
5.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller.
The bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any
complete byte has been transferred. The Command code and Byte count shown above must be sent, but the
data is ignored for those two bytes. The data is loaded until a Stop sequence is issued.
6.
At power-on, all registers are set to a default condition, as shown.
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming.
For more information, contact ICS for an I
2
C programming application note.
How to Write:
Controller (host) sends a start bit.
Controller (host) sends the write address D2
(H)
ICS clock will acknowledge
Controller (host) sends a dummy command code
ICS clock will acknowledge
Controller (host) sends a dummy byte count
ICS clock will acknowledge
Controller (host) starts sending first byte (Byte 0)
through byte 5
ICS clock will acknowledge each byte one at a time.
Controller (host) sends a Stop bit
How to Read:
Controller (host) will send start bit.
Controler (host) sends the read address D3
(H)
ICS clock will acknowledge
ICS clock will send the byte count
Controller (host) acknowledges
ICS clock sends first byte (Byte 0) through byte 5
Controller (host) will need to acknowledge each byte
Controller (host) will send a stop bit
Notes:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D3
(H)
ACK
Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Read:
Controller (Host)
ICS (Slave/Receiver)
Start Bit
Address
D2
(H)
ACK
Dummy Command Code
ACK
Dummy Byte Count
ACK
Byte 0
ACK
Byte 1
ACK
Byte 2
ACK
Byte 3
ACK
Byte 4
ACK
Byte 5
ACK
Stop Bit
How to Write:
5
ICS9148-37
0143G--08/04/04
Byte 1: CPU, Active/Inactive
Register (1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive
Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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Byte0: Functionality and Frequency Select Register
(default = 0)
Serial Configuration Command Bitmap
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