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Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-93
Advance Information
Block Diagram
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9148-93 Rev - 1/22/99
Pin Configuration
Generates the following system clocks:
- 4 CPU(2.5V/3.3V) upto 100MHz.
- 6 PCI(3.3V) @ 33.3MHz
- 2AGP(3.3V) @ 2 x PCI
- 12 SDRAMs(3.3V) @ either CPU or AGP
- 2 REF (3.3V) @ 14.318MHz
Skew characteristics:
- CPU CPU<250ps
- SDRAM SDRAM < 250ps
- CPU SDRAM < 250ps
- CPU(early) PCI : 1-4ns
Supports Spread Spectrum modulation +0.25, 0.6%
Serial I
2
C interface for Power Management, Frequency
Select, Spread Spectrum.
Efficient Power management scheme through PCI and CPU
STOP CLOCKS.
Uses external 14.318MHz crystal
48 pin 300mil SSOP.
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:5)
VDD3 = SDRAM (0:11), supply for PLL core,
24 MHz, 48MHz
VDD4 = AGP (0:1)
VDDL = CPUCLK (0:3)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-93 is the single chip clock solution for Desktop/
Notebook designs using the VIA MVP3 style chipset. It
provides all necessary clock signals for such a system.
Spread spectrum may be enabled through I
2
C programming.
Spread spectrum typically reduces system EMI by 8dB to
10dB. This simplifies EMI qualification without resorting to
board design iterations or costly shielding. The ICS9148-93
employs a proprietary closed loop design, which tightly
controls the percentage of spreading over process and
temperature variations.
Serial programming I
2
C interface allows changing functions,
stop clock programming and frequency selection. The SD_SEL
latched input allows the SDRAM frequency to follow the
CPUCLK frequency(SD_SEL=1) or the AGP clock
frequency(SD_SEL=0).
ADVANCE INFORMATION documents contain information on products
in the formative or design phase development. Characteristic data and
other specifications are design goals. ICS reserves the right to change or
discontinue these products without notice.
2
ICS9148- 93
Advance Information
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor to
program logic Hi to VDD or GND for logic low.
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ICS9148-93
Advance Information
Functionality
V
DD
1, 2, 3, 4 = 3.3V5%, V
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= 2.5V 5% or 3.3 5%, TA= 0 to 70C
Crystal (X1, X2) = 14.31818MHz
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3
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3
CPU 3.3#_2.5V Buffer selector for CPUCLK drivers.
Power Management Functionality
Mode Pin - Power Management Input Control
5
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4
ICS9148- 93
Advance Information
Byte0: Functionality and Frequency Select Register
(default = 0)
Serial Configuration Command Bitmap
General I
2
C serial interface information
The information in this section assumes familiarity with I
2
C programming. For more information, contact ICS for an I
2
C
programming application note.
How to Write:
Send the address D2
(H)
.
Send two additional dummy bytes, a command code
and byte count.
Send the desired number of data bytes.
See the diagram below:
Note that the acknowledge bit is sent by the clock chip, and pulls the data line low. There is no minimum of data bytes that must
be sent.
How to Read:
Send the address D3
(H)
.
Send the byte count in binary coded decimal
Read back the desired number of data bytes
See the diagram below:
The following specifications should be observed:
1.
Operating voltage for I
2
C pins is 3.3V
2.
Maximum data transfer rate (SCLK) is 100K bits/sec.
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I
2
C is a trademark of Philips Corporation
Note 1. Default at Power-up will be for latched logic inputs,
as defined by Bit 3.
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5
ICS9148-93
Advance Information
Byte 1: CPU, Active/Inactive Register
(1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register
(1 = enable, 0 = disable)
Byte 3: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
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6
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5
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4
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4
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3
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3
K
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2
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(
2
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(
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0
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8
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I
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P
t
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B
#
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7
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(
7
M
A
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D
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6
t
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9
2
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I
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A
(
6
M
A
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D
S
5
t
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1
3
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I
/
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(
5
M
A
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4
t
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B
2
3
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(
4
M
A
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S
3
t
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B
4
3
1
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(
3
M
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2
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5
3
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(
2
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0
M
A
R
D
S
Byte 4: SDRAM Active/Inactive Register
(1 = enable, 0 = disable)
Byte 5: Peripheral Active/Inactive Register
(1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled
from switching.
t
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#
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6
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5
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4
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6
t
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-
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R
(
5
t
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B
-
1
)
d
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R
(
4
t
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B
7
4
1
)
t
c
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/
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A
(
1
P
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A
3
t
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B
-
1
)
d
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(
2
t
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-
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)
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R
(
1
t
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6
4
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)
t
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F
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