Integrated
Circuit
Systems, Inc.
General Description
Features
ICS9148-26
Block Diagram
Pentium is a trademark of Intel Corporation
I
2
C is a trademark of Philips Corporation
Frequency Generator & Integrated Buffers for PENTIUM/Pro
TM
9148-26 Rev D 07/23/98
Pin Configuration
3.3V outputs: SDRAM, PCI, REF, 48/24MHz
2.5V outputs: CPU, IOAPIC
20 ohm CPU clock output impedance
20 ohm PCI clock output impedance
Skew from CPU (earlier) to PCI clock - 1 to 4 ns, center 2.2 ns.
No external load cap for C
L
=18pF crystals
250 ps CPU, PCI clock skew
250ps (cycle to cycle) CPU jitter @ 66.66MHz
Smooth frequency switch, with selections from 50 to
133 MHz CPU.
I
2
C interface for programming
2ms power up clock stable time
Clock duty cycle 45-55%.
48 pin 300 mil SSOP package
3.3V operation, 5V tolerant inputs (with series R)
<6ns propagation delay SDRAM form Buffer Input
48-Pin SSOP
Power Groups
VDD1 = REF (0:1), X1, X2
VDD2 = PCICLK_F, PCICLK(0:4)
VDD3 = SDRAM (0:13), supply for PLL core
VDD4 = 24MHz, 48MHz
VDDL1 = IOAPIC
VDDL2 = CPUCLK (0:1)
* Internal Pull-up Resistor of
240K to 3.3V on indicated inputs
The ICS9148-26 generates all clocks required for high speed
RISC or CISC microprocessor systems such as Intel PentiumPro
or Cyrix. Eight different reference frequency multiplying factors
are externally selectable with smooth frequency transitions.
Features include two CPU, six PCI and fourteen SDRAM clocks.
Two reference outputs are available equal to the crystal
frequency. Plus the IOAPIC output powered by VDDL1. One
48 MHz for USB, and one 24 MHz clock for Super IO. Spread
Spectrum built in at 0.5% or 1.5% modulation to reduce the
EMI. Serial programming I
2
C interface allows changing
functions, stop clock programing and Frequency selection.
Additionally, the device meets the Pentium power-up
stabilization, which requires that CPU and PCI clocks be stable
within 2ms after power-up. It is not recommended to use I/O
dual function pin for the slots (ISA, PIC, CPU, DIMM). The
add on card might have a pull up or pull down.
High drive PCICLK and SDRAM outputs typically provide
greater than 1 V/ns slew rate into 30pF loads. CPUCLK outputs
typically provide better than 1V/ns slew rate into 20pF loads
while maintaining 505% duty cycle. The REF and 24 and 48
MHz clock outputs typically provide better than 0.5V/ns slew
rates into 20pF.
ICS reserves the right to make changes in the device data identified in this
publication without further notice. ICS advises its customers to obtain the latest
version of all device data to verify that any information being relied upon by the
customer is current and accurate.
2
ICS9148-26
Pin Descriptions
Notes:
1:
Internal Pull-up Resistor of 240K to 3.3V on indicated inputs
2:
Bidirectional input/output pins, input logic levels are latched at internal power-on-reset. Use 10Kohm resistor
to program logic Hi to VDD or GND for logic low.
PIN NUMBER
PIN NAME
TYPE
DESCRIPTION
1
VDD1
PWR
Ref (0:2), XTAL power supply, nominal 3.3V
2
REF0
OUT
14.318 Mhz reference clock.This REF output is the
STRONGER buffer for ISA BUS loads
3,9,16,22,
33,39,45
GND
PWR
Ground
4
X1
IN
Crystal input, has internal load cap (36pF) and feedback
resistor from X2
5
X2
OUT
Crystal output, nominally 14.318MHz. Has internal load
cap (36pF)
6,14
VDD2
PWR
Supply for PCICLK_F and PCICLK (0:5), nominal 3.3V
7
PCICLK_F
OUT
Free running PCI clock
MODE
1 , 2
IN
Pin 17, pin 18 function select pin, 1=Desktop Mode, 0=Mobile
Mode. Latched Input.
8
PCICLK0
OUT
PCI clock output.
10, 11, 12, 13
PCICLK(1:4)
OUT
PCI clock outputs.
15
BUFFER IN
IN
Input to Fanout Buffers for SDRAM outputs.
18
PCI_STOP#
1
IN
Halts PCICLK(0:4) clocks at logic 0 level, when input low (In
mobile mode, MODE=0)
17, 18, 20, 21,
28, 29, 31, 32,
34, 35,37,38,40,41
SDRAM (0:13)
OUT
(Pins 17, 18 SDRAM output only if MODE=High)
SDRAM clock outputs, Fanout Buffer outputs from BUFFER IN pin
(controlled by chipset).
19,30,36
VDD3
PWR
Supply for SDRAM (0:13) and CPU PLL Core, nominal 3.3V.
23
SDATA
IN
Data input for
I
2
C serial input, 5V tolerant input
24
SCLK
IN
Clock input of
I
2
C input, 5V tolerant input
25
24MHz
OUT
24MHz output clock
FS1
1 , 2
IN
Frequency select pin. Latched Input.
26
48MHz
OUT
48MHz output clock
FS0
1 , 2
IN
Frequency select pin. Latched Input
27
VDD4
PWR
Power for 24 & 48MHz output buffers and fixed PLL core.
43, 44
CPUCLK(0:1)
OUT
CPU clock outputs, powered by VDDL2. Low if CPU_STOP#=Low
42
VDDL2
PWR
Supply for CPU (0:1), either 2.5V or 3.3V nominal
46
REF1
OUT
14.318 MHz reference clock.
FS2
1 , 2
IN
Frequency select pin. Latched Input
17
CPU_STOP#
1
IN
Halts CPUCLK (0:1) clocks at logic 0 level, when input low (in
Mobile Mode, MODE=0)
47
IOAPIC
OUT
IOAPIC clock output. 14.318 MHz Powered by VDDL1.
48
VDDL1
PWR
Supply for IOAPIC, either 2.5 or 3.3V nominal
3
ICS9148-26
Functionality
V
DD
1,2,3 = 3.3V5%, V
DDL
1,2 = 2.5V5% or 3.35%, TA=0 to 70C
Crystal (X1, X2) = 14.31818MHz
Power Management Functionality
Mode Pin - Power Management Input Control
MODE, Pin 7
(Latched Input)
Pin 17
Pin 18
0
CPU_STOP#
(INPUT)
PCI_STOP#
(INPUT)
1
SDRAM11
(OUTPUT)
SDRAM10
(OUTPUT)
F S 2
F S 1
F S 0
C P U
(M H z)
P C IC LK
(M H z)
R EF, IO A P IC
(M H z)
1
1
1
100.2
33.3 (C PU/3)
1 4 . 3 1 8
1
1
0
133.3
1
33.3 (C PU/4)
1
1 4 . 3 1 8
1
0
1
112.0
1
37.3 (C PU/3)
1
1 4 . 3 1 8
1
0
0
1 0 3
34.3 (C PU/3)
1 4 . 3 1 8
0
1
1
6 6 . 8
33.4 (C PU/2)
1 4 . 3 1 8
0
1
0
8 3 . 3
41.65 (C PU/2)
1 4 . 3 1 8
0
0
1
7 5
37.5 (C PU/2)
1 4 . 3 1 8
0
0
0
5 0
25 (C PU/2)
1 4 . 3 1 8
CPU_STOP#
PCI_STOP#
CPUCLK
Outputs
PCICLK
(0:4)
PCICLK_F,
REF,
24/48MHz
and SDRAM
Crystal
OSC
VCO
0
1
Stopped Low
Running
Running
Running
Running
1
1
Running
Running
Running
Running
Running
1
0
Running
Stopped Low
Running
Running
Running
0
0
Stopped Low
Stopped Low
Running
Running
Running
Note1. Performance not guaranteed
4
ICS9148-26
Byte0: Functionality and Frequency Select Register (default = 0)
Serial Configuration Command Bitmap
A.
For the clock generator to be addressed by an I
2
C controller, the following address must be sent as a start sequence, with
an acknoledge bit between each byte.
B.
The clock generator is a slave/receiver I
2
C component. It can read back the data stored in the latches for verification. (set
R/W# to 1 above) Read-Back will support Intel PIIX4 "Block-Read" protocol, with a "Byte count" following the
address with R/W#=1, then proceding to Byte 0, 1, 2, ...until STOP.
C.
The data transfer rate supported by this clock generator is 100K bits/sec (standard mode)
D.
The input is operating at 3.3V logic levels.
E.
The data byte format is 8 bit bytes.
F.
To simplify the clock generator I
2
C interface, the protocol is set to use only "Block-Writes" from the controller. The
bytes must be accessed in sequential order from lowest to highest byte with the ability to stop after any complete byte
has been transferred. The Command code and Byte count shown above must be sent, but the data is ignored for those
two bytes. The data is loaded until a Stop sequence is issued.
G..
At power-on, all registers are set to a default condition. Byte 0 defaults to a 0, Bytes 1 through 5 default to a 1 (Enabled
output state).
General I
2
C serial interface information
I
2
C is a trademark of Philips Corporation
Then Byte 0, 1, 2, etc in
sequence until STOP.
Clock Generator
Address (7 bits)
ACK
+ 8 bits dummy
command code
ACK
+ 8 bits dummy
Byte count
ACK
A(6:0) & R/W#
D2
(H)
Then Byte 0, 1, 2, etc. in
sequence until STOP.
Clock Generator
Address (7 bits)
ACK
Byte Count
Readback
ACK
A(6:0) & R/W#
D3
(H)
Bit
Description
PWD
Bit 7
0 - 1.5% Spread Spectrum Modulation
1 - 0.5% Spread Spectrum Modulation
0
Bit6 Bit5 Bit4
CPU clock
PCI
Note1
Bit 6:4
111
110
100.2
133.3
2
33.3 (CPU/3)
33.3
2
101
100
112.0
2
103
37.3
2
34.3 (CPU/3)
011
010
66.8
83.3
33.4 (CPU/2)
41.65(CPU/2)
001
000
75
50
37.5 (CPU/2)
25 (CPU/2)
Bit 3
0 - Frequency is selected by hardware select, Latched Inputs
1 - Frequency is selected by Bit 6:4 (above)
0
Bit 2
0 - Spread Spectrum center spread type.
1 - Spread Spectrum down spread type.
0
Bit 1
0 - Normal
1 - Spread Spectrum Enabled
0
Bit 0
0 - Running
1- Tristate all outputs
0
Note1. Default at Power-up will be for
latched logic inputs to define
frequency. Bits 4, 5, 6 are default
to 000, and if bit 3 is written to a 1
to use Bits 6:4, then these should
be defined to desired frequency at
same write cycle.
Note2. Performance not guaranteed
Note: PWD = Power-Up Default
5
ICS9148-26
Byte 1: CPU, Active/Inactive Register (1 = enable, 0 = disable)
Byte 2: PCI Active/Inactive Register (1 = enable, 0 = disable)
Byte 3: SDRAM Active/Inactive Register (1 = enable, 0 = disable)
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Notes:
1. Inactive means outputs are held LOW and are disabled from switching.
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
-
1
(Reserved)
Bit 4
-
1
(Reserved)
Bit 3
40
1
SDRAM12 (Act/Inact)
Bit 2
41
1
SDRAM13 (Act/Inact)
Bit 1
43
1
CPUCLK1 (Act/Inact)
Bit 0
44
1
CPUCLK0 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
7
1
PCICLK_F (Act/Inact)
Bit 5
-
1
(Reserved)
Bit 4
14
1
PCICLK4 (Act/Inact)
Bit 3
12
1
PCICLK3 (Act/Inact)
Bit 2
11
1
PCICLK2 (Act/Inact)
Bit 1
10
1
PCICLK1 (Act/Inact)
Bit 0
8
1
PCICLK0 (Act/Inact)
Bit
Pin #
PWD
Description
Bit 7
-
1
(Reserved)
Bit 6
-
1
(Reserved)
Bit 5
26
1
48MHz (Act/Inact)
Bit 4
25
1
24 MHz (Act/Inact)
Bit 3
-
1
(Reserved)
Bit 2
21,20,18,17
1
SDRAM (8:11) (Active/Inactive)
(SDRAM 10, 11 only in Desktop Mode, MODE=1)
Bit 1
32,31,29,28
1
SDRAM (4:7) (Active/Inactive)
Bit 0
38,37,35,34
1
SDRAM (0:3) (Active/Inactive)
PDF 
ZIP