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M1010-01 Datasheet Rev 0.4
Revised 29Sep2003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
Integrated
Circuit
Systems, Inc.
P r e l i m i n a r y I n f o r m a t i o n
G
ENERAL
D
ESCRIPTION
The M1010-01 is a VCSO (Voltage Controlled SAW
Oscillator) based clock jitter
attenuator PLL designed for clock
jitter attenuation and frequency
translation. The device is ideal for
generating the transmit reference
clock for OC-12 and OC-48 optical
network systems supporting 622 -
2,488 MHz rates. It can serve to jitter attenuate a
stratum reference clock or a recovered clock in loop
timing mode. The M1010-01 module includes a
proprietary SAW (surface acoustic wave) delay line as
part of the VCSO. This results in a high frequency,
high-Q, low phase noise oscillator that assures low
intrinsic output jitter.
F
EATURES
Ideal for OC-12/48 data clock
Integrated SAW delay line
Output frequencies from 150 to 175 MHz
(Specify VCSO output frequency at time of order)
Low phase jitter of 0.5 ps rms, typical (12kHz to 20MHz)
LVPECL clock output
Pin-selectable feedback and reference divider ratios,
no programming required
Scalable dividers provide further adjustment of loop
bandwidth as well as jitter tolerance
Reference clock inputs support differential LVDS,
LVPECL, as well as single-ended LVCMOS, LVTTL
Single 3.3V power supply
Small 9 x 9 mm SMT (surface mount) package
P
IN
A
SSIGNMENT
(9 x 9 mm SMT)
Figure 1: Pin Assignment
S
IMPLIFIED
B
LOCK
D
IAGRAM
Figure 2: Simplified Block Diagram
Example I/O Clock Frequency Combinations
Using
M1010-01-155.5200
Frequency
Input (Mfin)
Ratio
Input Reference
Clock
(MHz)
Output
Clock MHz
8
19.44
155.52
2
77.76
1
155.52
Table 1: Example I/O Clock Frequency Combinations
M 1 0 1 0
( T o p V i e w )
18
17
16
15
14
13
12
11
10
28
29
30
31
32
33
34
35
36
1
2
3
4
5
6
7
8
9
F
I
N
_
SEL
1
GN
D
NC
DI
F
_RE
F
0
n
D
I
F
_RE
F
0
RE
F
_
S
E
L
DI
F
_RE
F
1
n
D
I
F
_RE
F
1
VC
C
VCC
NC
nFOUT
FOUT
GND
NC
NC
VCC
GND
FIN_SEL0
SEL0
SEL1
SEL2
NC
VCC
DNC
DNC
DNC
nOP
_
I
N
O
P
_O
UT
VC
nV
C
nOP
_
OU
T
OP
_
I
N
GN
D
GN
D
GN
D
19
20
21
22
23
24
25
26
27
R Div
VCSO
Mfin Div
M Div
Divider LUT
Mfin Divider
LUT
FIN_SEL1:0
REF_SEL
DIF_REF0
nDIF_REF0
DIF_REF1
nDIF_REF1
0
1
M1010
FOUT
nFOUT
SEL2:0
3
2
Loop
Filter
M1010-01 VCSO Based Clock Jitter Attenuator
M1010-01 Datasheet Rev 0.4
2 of 8
Revised 29Sep2003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
D
ETAILED
B
LOCK
D
IAGRAM
Figure 3: Detailed Block Diagram
P
IN
D
ESCRIPTIONS
Number
Name
I/O
Configuration
Description
1, 2, 3, 10, 14, 26
GND
Ground
Power supply ground connections.
4
9
OP_IN
nOP_IN
Input
External loop filter connections.
See Figure 4, External Loop Filter, on pg. 4.
5
8
nOP_OUT
OP_OUT
Output
6
7
nVC
VC
Input
11, 18, 19, 33
VCC
Power
Power supply connection, connect to +
3.3
V.
12, 13, 17, 25, 32
NC
No internal connection.
15
16
FOUT
nFOUT
Output
No internal terminator
Clock output pairs. Differential LVPECL.
20
nDIF_REF1
Input
Internal pull-UP resistor
1
Note 1: For typical values of internal pull-down and pull-up resistors, see "Inputs with Pull-down" and "Inputs with Pull-up"
in Table 8, DC Characteristics, on pg. 6.
Reference clock input pair.
Differential LVPECL or LVDS.
21
DIF_REF1
Internal pull-down resistor
1
22
REF_SEL
Input
Internal pull-down resistor
1
Reference clock input selection. LVCMOS/LVTTL:
Logic
1
selects
DIF_REF1, nDIF_REF1.
Logic
0
selects
DIF_REF0, nDIF_REF0
.
23
nDIF_REF0
Input
Internal pull-UP resistor
1
Reference clock input pair.
Differential LVPECL or LVDS.
24
DIF_REF0
Internal pull-down resistor
1
27
28
FIN_SEL1
FIN_SEL0
Input
Internal pull-down resistor
1
I
nput clock frequency selection. LVCMOS/LVTTL.
See
Table 3,
Mfin (Frequency Input) Divider Look-Up Table
(LUT)
on
pg. 3.
29
30
31
SEL0
SEL1
SEL2
Input
Internal pull-UP resistor
1
M and R divider value selection. LVCMOS/ LVTTL.
See
Table 4,
SEL2:0 Look-up Table (LUT)
on
pg. 3.
34, 35, 36
DNC
Do Not Connect.
Table 2: Pin Descriptions
Phase
Locked
Loop
(PLL)
M1010
SAW Delay Line
Phase
Shifter
VCSO
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
R
IN
R
IN
OP_IN
nOP_IN
Phase
Detector
Loop Filter
Amplifier
External
Loop Filter
Components
FOUT
nFOUT
SEL2:0
FIN_SEL1:0
R Div
MUX
0
REF_SEL
DIF_REF1
nDIF_REF1
DIF_REF0
nDIF_REF0
1
2
Divider LUT
3
Mfin Divider
LUT
Mfin Divider
M Div
M1010-01 Datasheet Rev 0.4
3 of 8
Revised 29Sep2003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
PLL D
IVIDER
L
OOK
-U
P
T
ABLES
Mfin (Frequency Input) Divider Look-Up Table (LUT)
The
FIN_SEL1:0
pins select the feedback divider value
("Mfin").
SEL2:0 Look-up Table (LUT)
The
SEL2:0
pins select the feedback and reference
divider values M and R to enable adjustment of loop
bandwidth and jitter tolerance.
F
UNCTIONAL
D
ESCRIPTION
The M1010-01 is a PLL (Phase Locked Loop) based
clock generator that generates output clocks synchro-
nized to one of two selectable input reference clocks.
An internal high "Q" SAW filter provides low jitter signal
performance and controls the output frequency of the
VCSO (Voltage Controlled SAW Oscillator).
A configurable frequency divider (labeled "Mfin Divider")
provides the division options to accomodate various
reference clock frequencies.
In addition, configurable feedback and reference
dividers (the "M Divider" and "R Divider") provide divider
value options to enable adjustment of loop bandwidth
and jitter tolerance.
For example, the
M1010-01-155.5200
(see "Ordering
Information"
on pg. 8
)
has a
155.52
MHz VCSO
frequency:
The Mfin feedback divider allows an input frequency to
be the VCSO output frequency divided by
1
,
2
, or
8
.
Therefore, for the base input frequency of
155.52
MHz,
the actual input reference clock frequencies can be:
155.52
,
77.76
, and
19.44
MHz. (See Table 3 on pg. 3.)
The PLL
The PLL uses a phase detector and configurable
dividers to synchronize the output of the VCSO with
selected reference clock.
The "Mfin Divider" and "M Divider" divide the VCSO
frequency, feeding the result into the phase detector.
The selected input reference clock is divided by the "R
Divider". The result is fed into the other input of the
phase detector.
The phase detector compares its two inputs. It then
outputs pulses to the loop filter as needed to increase or
decrease the VCSO frequency and thereby match and
lock the divider output's frequency and phase to those
of the input reference clock.
Due to the narrow tuning range of the VCSO
(+200ppm), appropriate selection of all of the following
are required for the PLL be able to lock: VCSO center
frequency, input frequency, and divider selections.
Relationship Among Frequencies and Dividers
The VCSO center frequency must be specified at time
of order. The relationship between the VCSO (Fvcso)
frequency, the Mfin divider, the M divider, the R divider,
and the input reference frequency (Fin) is:
Clock Output
The M1010-01 provides one differential LVPECL output
pair
FOUT
. PECL and LVDS product options are
available; consult factory.
FIN_SEL1:0
Mfin Value
M1010-01-155.5200
Sample Ref. Freq. (MHz)
1
Note 1: Example with M1010-01-155.5200.
0
0
8
19.44
0
1
2
77.76
1
0
1
155.52
1
1
x
Test mode. Do not use.
Table 3: Mfin (Frequency Input) Divider Look-Up Table (LUT)
SEL2:0
M
R
Description
0 0 0
236
236
Various divider values to adjust bandwidth
and jitter tolerance
0 0 1
79
79
0 1 0
14
14
0 1 1
239
239
1 0 0
1
1
1 0 1
2
2
1 1 0
4
4
1 1 1
8
8
Table 4: SEL2:0 Look-up Table (LUT)
Fvcso
Fin Mfin
M
R
----
=
M1010-01 Datasheet Rev 0.4
4 of 8
Revised 29Sep2003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
Integrated
Circuit
Systems, Inc.
M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
External Loop Filter
To provide stable PLL operation, the M1010-01 requires
the use of an external loop filter. This is implemented by
connecting passive external components to the device
as shown in Figure 4 below.
The M1010-01 utilizes a differential analog signal path
to minimize noise coupling from the system. Because of
this, the loop filter implementation requires two identical
complementary RC filters as shown here.
Figure 4: External Loop Filter
PLL bandwidth is affected by the "M" value and the
"Mfin" value, as well as the VCSO frequency.
The various
SEL1:0
settings can be used to actively
change PLL loop bandwidth in a given application. See
"SEL2:0 Look-up Table (LUT)" on pg. 3.
See Table 5, Example Loop Filter Component
Values for M1010-01-155.5200, on pg. 4.
PLL Simulator Tool Available
A free PC software utility is available on the ICS website
(www.icst.com). The M2000 Timing Modules PLL
Simulator is a downloadable application that simulates
PLL jitter and wander transfer characteristics. This
enables the user to set appropriate external loop
component values in a given application.
C
POST
C
POST
VC
nVC
R
POST
nOP_OUT
OP_OUT
R
POST
R
LOOP
R
LOOP
C
LOOP
C
LOOP
OP_IN
nOP_IN
6
7
5
4
9
8
Example Loop Filter Component Values for M1010-01-155.5200
1
VCSO Parameters: K
VCO
= 200kHz/V, R
IN
= 2050k
, VCSO Bandwidth = 700kHz.
Device Configuration
Example External Loop Filter Component Value
Nominal Performance Using These Values
F
Ref
(MHz)
F
VCSO
(MHz)
Mfin
M, R
Value
2
R loop
C loop
R post
C post
PLL Loop
Bandwidth
Damping
Factor
Passband Peak
Amplitude
@ Center
(dB)
Freq
.
19.44
155.52
8
1
118.0
k
1.0
F
100
k
1000
pF
270
Hz
6.5
0.05
10
Hz
2
118.0
k
22.0
F
200
k
1000
pF
134
Hz
6.8
0.04
4
Hz
77.76
155.52
2
1
59.0
k
1.0
F
100
k
1000
pF
610
Hz
6.5
0.05
20
Hz
2
59.0
k
2.2
F
100
k
1000
pF
267
Hz
6.8
0.04
10
Hz
8
118.0
k
2.2
F
200
k
1000
pF
134
Hz
6.8
0.04
10
Hz
155.52
155.52
1
1
40.2
k
1.0
F
40.2
k
1000
pF
740
Hz
6.3
0.05
20
Hz
4
59.0
k
1.0
F
100
k
1000
pF
267
Hz
6.8
0.04
10
Hz
8
76.8
k
2.0
F
200
k
1000
pF
180
Hz
6.3
0.05
8
Hz
Table 5: Example Loop Filter Component Values for M1010-01-155.5200
Note 1: K
VCO
, VCSO Bandwidth, M Divider Value, and External Loop Filter Component Values determine Loop Bandwidth, Damping Factor,
and Passband Peaking. For PLL Simulator software, go to www.icst.com.
Note 2: For loop timing applications, the recommended value for the product of "Mfin" x "M" is 8 or higher.
M1010-01 Datasheet Rev 0.4
5 of 8
Revised 29Sep2003
I n t e g r a t e d C i r c u i t S y s t e m s , I n c .
C o m m u n i c a t i o n s M o d u l e s
w w w. i c s t . c o m
t e l ( 5 0 8 ) 8 5 2 - 5 4 0 0
M1010-01
VCSO B
ASED
C
LOCK
J
ITTER
A
TTENUATOR
P r e l i m i n a r y I n f o r m a t i o n
Integrated
Circuit
Systems, Inc.
A
BSOLUTE
M
AXIMUM
R
ATINGS
1
Symbol Parameter
Rating
Unit
V
I
Inputs
-
0.5
to V
CC
+
0.5
V
V
O
Outputs
-
0.5
to V
CC
+
0.5
V
V
CC
Power Supply Voltage
4.6
V
T
S
Storage Temperature
-
45
to +
100
o
C
Table 6: Absolute Maximum Ratings
Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the
device. These ratings are stress specifications only. Functional operation of product at these conditions
or any conditions beyond those listed in Recommended Conditions of Operation, DC Characteristics, or
AC Characteristics is not implied. Exposure to absolute maximum rating conditions for extended periods
may affect product reliability.
R
ECOMMENDED
C
ONDITIONS
OF
O
PERATION
Symbol Parameter
Min
Typ
Max
Unit
V
CC
Positive Supply Voltage
3.135
3.3
3.465
V
T
A
Ambient Operating Temperature
Commercial
0
+
70
o
C
Industrial
-40
+
85
o
C
Table 7: Recommended Conditions of Operation