IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

COMMERCIAL TEMPERATURE RANGE

NOVEMBER 2000

1999 Integrated Device Technology, Inc.

DSC-2552/9

IDT49C465

IDT49C465A

COMMERCIAL TEMPERATURE RANGE

64-BIT FLOW-THRU

ERROR DETECTION

AND CORRECTION UNIT

DESCRIPTION:

The IDT49C465/A is a 32-bit, two-data bus, Flow-thruEDC unit. The

chip provides single-error correction and two and three bit error detec-
tion of both hard and soft memory errors. It can be expanded to 64-bit
widths by cascading two units, without the need for additional external
logic. The Flow-thruEDC has been optimized for speed and simplicity
of control.

The EDC unit has been designed for use in either of two configura-

tions in an error correcting memory system. The bidirectional configu-
ration is most appropriate for systems using bidirectional memory
buses. A second system configuration utilizes external octal buffers,
and is well-suited for systems using memory with separate I/O buses.

The IDT49C465/A supports partial word writes, pipelining, and error

diagnostics. It also provides parity protection for data on the system
side.

SIMPLIFIED FUNCTIONAL BLOCK DIAGRAM

CBO

0-7

M em ory

C heckbit

Generator

r
o

r
a

t
o

Correct

Logic

i
o

i
c

Detect

Logic

M ux

System

Checkbit

Generator

Byte

M ux

i
p

l
i
n

t
c

M ux

C heckbit

Latch

M D

Latch

M LE

0-31

ER R

M E R R

C BI

0-7

PC B I

0-7

PLE

M D

0-31

SLE

C ON TROL

CON TR OL

Latch

C ONTR OL

C ON TR OL

FEATURES:

- 32-bit wide Flow-thruEDCTM unit, cascadable to 64 bits
- Single-chip 64-bit Generate Mode
- Separate system and memory buses
- On-chip pipeline latch with external control
- Supports bidirectional and common I/O memories
- Corrects all single-bit errors
- Detects all double-bit errors and some multiple bit errors
- Error Detection Time -- 12ns
- Error Correction Time -- 14ns
- On chip diagnostic registers
- Parity generation and checking on system data bus

Low power CMOS -- 100mA typical at 20MHz

144-pin PGA and PQFP packages

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

COMMERCIAL TEMPERATURE RANGE

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

Vcc

G ND

SO E

PL E

SL E

G ND

Vcc

49C465Y

PQ 144-2

108

109

144

M D

Vcc

M D

G ND

M D

G ND

M O E

M LE

M D

G ND

M D

Vcc

M D

I
D

PIN CONFIGURATION

PQFP

TOP VIEW

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

COMMERCIAL TEMPERATURE RANGE

PGA (CAVITY UP)

TOP VIEW

PIN CONFIGURATION

Vcc

PC BI

S D

SLE

S D

SO E

P LE

S D

G ND

S D

Vcc

S D

G ND

SY O

M D

Vcc

M D

M O E M D

G ND

M D

Vcc

M D

G ND

M D

M LE

M D

Vcc

CB 0

PC BI

G ND

SY O

M D

Vcc

SY O

Vcc

NC*

PC BI

COD E

ID 1

CO D E

ID 2

M OD E

M E RR ER R

PC BI

M OD E

S Y O

SY O

G ND

SY O

M D

G ND M D

M D

C B 0

CB 0

CBO E

CB 0

PS EL PE RR

C B 0

G ND

GND

M O D E

SC LK

SYN -

CLK

G ND

C B 1

C LE A R

C B 1

M D

Vcc

C B 1

M D

G 144-2

* = Tied to Vcc internally

COMMERCIAL TEMPERATURE RANGE

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

DETAILED FUNCTIONAL BLOCK DIAGRAM

PAR IT Y

CHE CK

PAR IT Y

GEN

1 O F 4

BYT ES

PLE

SO E

0-3

0-31

SL E

PS EL

0-3

PE RR

LAT CH

M
U

ERR

M ERR

SYO

0-7

SYN CLK

SC LKE N

CLEAR

COD E ID

0,1

M O DE

0-2

CONT RO L

LO G IC

/ER R

INTERN AL SYN CLK

ER RO R

DET ECT

U
X

INT ERNAL

FINA L

SYN DR O M E

SYN DR OM E

G ENERATO R

CH ECK

BIT

LATC H

M D

C HECKBIT

G ENE RAT O R

ERRO R

CO RR ECT

ERRO R D AT A LAT CH

DIAG NO STIC

LAT CH ES

M D

LAT CH

CLEAR

INTERN AL SYN CL K

BYTE M U X

0-3

CHE CKB IT

GENERAT OR

D ash ed L ine = Diagnostic path

PCB I

0-7

CBI

0-7

M LE

M D

0-31

M O E

CBO

0-7

CBO E

PCBI

0-7

C HECKBIT

G ENE RAT O R

U
X

M
U

PIPE

LAT CH

M
U

IDT49C465/A
32-BIT FLOW-THRU ERROR DETECTION AND CORRECTION UNIT

COMMERCIAL TEMPERATURE RANGE

M D

ED C

C BI

C BO

M EM OR Y

I/O

CPU

I/O

C HEC KBITS

EXT. BUFFER

M D

EDC

CBI

CBO

M E M OR Y

IN PU T BU S

C HEC KBIT

I/O

M E M OR Y

OUTPUT BUS

C PU BUS

EXT. BU FFER

Figure 1. Common I/O Configuration

Figure 3. Bypassed Separate I/O Configuration

SYSTEM CONFIGURATIONS

The IDT49C465 EDC unit can be used in various configurations in an

EDC system. The basic configurations are shown below.

Figure 1 illustrates a bidirectional configuration, which is most appropriate

for systems using bidirectional memory buses. It is the simplest
configuration to understand and use. During a correction cycle, the
corrected data word can be simultaneously output on both the system
bus and memory bus. During partial-word-write operations, the new
bytes are internally combined with the corrected old bytes for checkbit

generation and writing to memory.

Figure 2 illustrates a separate I/O configuration. This is appropriate

for systems using separate I/O memory buses. This configuration
allows separate input and output memory buses to be used. Corrected
data is output on the SD outputs for the system and for re-write to

memory. Partial word-write bytes are combined externally for writing
and checkbit generation.

Figure 3 illustrates a third configuration which uses external buffers

and is also well-suited for systems using memory with separate I/O

buses. Since data from memory does not need to pass through the part
on every cycle, the EDC system may operate in "bus-watch" mode. As
in the separate I/O configuration, corrected data is output on the SD
outputs.

Figure 4 illustrates the single-chip generate-only mode for the very

fast 64-bit checkbit generation in systems that use separate checkbit-
generate and detect-correct units. If this is not desired, 64-checkbit
generation and correction can be done with just two EDC units. 64-bit
correction is also straightforward, fast, and requires no extra hardware
for the expansion.

EXT.

M D

ED C

C BI

C BO

M EM O R Y

INP UTS

C HE C KBITS

M EM O R Y

O UTP UTS

CP U

ED C

C BO

64-BIT

G EN .

ON LY

M E M O RY

IN PUT BU S

CH ECK

BITS OU T

C PU BU S

BUFFER

M E M O RY

IN PUT BU S

BUFFER

BU FFER

C BI

LOW ER

DATA

U PPER

D ATA

ED C

EDC

C HEC K
BITS IN

M E M O RY

OUTPUT BUS

Figure 2. Separate I/O Configuration

Figure 4. Separate generate/Correction Units with 64-Bit Checkbit Generation

Электронный компонент: 49C465