COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

SEPTEMBER 2001

2001 Integrated Device Technology, Inc.

DSC 5844/1

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

· 3 pairs of programmable skew outputs
· Low skew: 200ps same pair, 250ps all outputs
· Selectable positive or negative edge synchronization:

Excellent for DSP applications

· Synchronous output enable
· Output frequency: 3.75MHz to 100MHz
· 2x, 4x, 1/2, and 1/4 outputs
· 5V with TTL outputs
· 3 skew grades:

IDT5993A-2: t

SKEW0

<250ps

IDT5993A-5: t

SKEW0

<500ps

IDT5993A-7: t

SKEW0

<750ps

· 3-level inputs for skew and PLL range control
· PLL bypass for DC testing
· External feedback, internal loop filter
· 46mA I

high drive outputs

· Low Jitter: <200ps peak-to-peak
· Outputs drive 50

terminated lines

· Available in QSOP package

FUNCTIONAL BLOCK DIAGRAM

G ND/sO E

Skew

S elect

1F1:0

Skew

S elect

2F1:0

REF

PLL

Skew

S elect

3F1:0

C CQ

/PE

IDT5993A

PROGRAMMABLE SKEW
PLL CLOCK DRIVER
TURBOCLOCKTM

DESCRIPTION:

The IDT5993A is a high fanout PLL based clock driver intended for

high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or
lag the REF input signal. The IDT5993A has six programmable skew
outputs and two zero skew outputs. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

PIN CONFIGURATION

NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Description

Max

Unit

Supply Voltage to Ground

0.5 to +7

DC Input Voltage

0.5 to +7

Maximum Power Dissipation (T

= 85°C)

0.66

STG

Storage Temperature

65 to +150

°C

NOTE:
1. Capacitance applies to all inputs except TEST, FS, and nF

1:0

. It is characterized but

not production tested.

CAPACITANCE

= +25°C, f = 1MHz, V

= 0V)

Parameter

Description

Typ.

Max.

Unit

Input Capacitance

QSOP

TOP VIEW

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit t

which is of the

order of a nanosecond (see PLL Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the nF

1:0

control pins. In order

to minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF

1:0

control pins.

PROGRAMMABLE SKEW

PIN DESCRIPTION

Pin Name

Type

Description

REF

Reference Clock Input

Feedback Input

TEST

(1)

When MID or HIGH, disables PLL (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See Control
Summary Table) remain in effect. Set LOW for normal operation.

GND/ sOE

(1)

Synchronous Output Enable. When HIGH, it stops clock outputs (except 3Q

and 3Q

) in a LOW state - 3Q

and 3Q

may be used as

the feedback signal to maintain phase lock. When TEST is held at MID level and GND/ sOE is HIGH, the nF

[1:0]

pins act as output disable

controls for individual banks when nF

[1:0]

= LL. Set GND/sOE LOW for normal operation.

CCQ

/PE

Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the
reference clock.

[1:0]

3-level inputs for selecting 1 of 9 skew taps or frequency functions

Selects appropriate oscillator circiot based on anticipated frequency range. (See PLL Programmable Skew Range.)

[1:0]

OUT

Three output banks of two outputs with programmable skew (1Q:3Q), and 4Q output has fixed zero skew outputs.

CCN

PWR

Power supply for output buffers

CCQ

PWR

Power supply for phase locked loop and other internal circuitry

GND

PWR

Ground

NOTE:
1. When TEST = MID and GND/sOE = HIGH, PLL remains active with nF[

1:0

] = LL functioning as an output disable control for individual output banks. Skew selections remain

in effect unless nF[

1:0

] = LL.

REF

GND

TEST

GND/sOE

CCN

GND

CCN

CCQ

/PE

CCQ

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

EXTERNAL FEEDBACK

By providing external feedback, the IDT5993A gives users flexibility

with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.

NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed. Selecting the appropriate FS value based on

input frequency range allows the PLL to operate in its `sweet spot' where jitter is lowest.

2. The level to be set on FS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at 1Q

1:0

, 2Q

1:0

, and the

higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be the same as the VCO when the output connected

to FB is undivided. The frequency of the REF and FB inputs will be 1/2 or 1/4 the VCO frequency when the part is configured for a frequency multiplication by using a divided

output as the FB input.

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example

if a 4t

skewed output is used for feedback, all other outputs will be skewed 4t

in addition to whatever skew value is programmed for those outputs. `Max adjustment' range

applies to output pairs 3 and 4 where ± 6t

skew adjustment is possible and at the lowest F

NOM

value.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.

FS = LOW

FS = MID

FS = HIGH

Comments

Timing Unit Calculation (t

)

1/(44 x F

NOM

)

1/(26 x F

NOM

)

1/(16 x F

NOM

)

VCO Frequency Range (F

NOM

)

(1,2)

15 to 35MHz

25 to 60MHz

40 to 100 MHz

Skew Adjustment Range

(3)

Max Adjustment:

±9.09ns

±9.23ns

±9.38ns

±49°

±83°

±135°

Phase Degrees

±14%

±23%

±37%

% of Cycle Time

Example 1, F

NOM

= 15MHz

= 1.52ns

Example 2, F

NOM

= 25MHz

= 0.91ns

= 1.54ns

Example 3, F

NOM

= 30MHz

= 0.76ns

= 1.28ns

Example 4, F

NOM

= 40MHz

= 0.96ns

= 1.56ns

Example 5, F

NOM

= 50MHz

= 0.77ns

= 1.25ns

Example 6, F

NOM

= 80MHz

= 0.78ns

PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0

Skew (Pair #1, #2)

Skew (Pair #3)

(1)

Divide by 2

M M

Zero Skew

M H

H M

H H

Divide by 4

NOTE:
1. LL disables outputs if TEST = MID and GND/sOE = HIGH.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

RECOMMENDED OPERATING RANGE

IDT5993A-5, -7

IDT5993A-2

(Industrial)

(Commercial)

Symbol

Description

Min.

Max.

Min.

Max.

Unit

Power Supply Voltage

4.5

5.5

4.75

5.25

Ambient Operating Temperature

-40

+85

+70

°C

POWER SUPPLY CHARACTERISTICS

Symbol

Parameter

Test Conditions

(1)

Typ.

(2)

Max.

Unit

CCQ

Quiescent Power Supply Current

= Max., TEST = MID, REF = LOW,

GND/sOE = LOW, All outputs unloaded

Power Supply Current per Input HIGH

= Max., V

= 3.4V

0.4

1.5

CCD

Dynamic Power Supply Current per Output

= Max., C

= 0pF

100

160

µA/MHz

TOT

Total Power Supply Current

= 5V, F

REF

= 20MHz, C

= 240pF

(1)

= 5V, F

REF

= 33MHz, C

= 240pF

(1)

= 5V, F

REF

= 66MHz, C

= 240pF

(1)

117

NOTE:
1. For eight outputs, each loaded with 30pF.

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Conditions

Min.

Max.

Unit

Input HIGH Voltage

Guaranteed Logic HIGH (REF, FB Inputs Only)

Input LOW Voltage

Guaranteed Logic LOW (REF, FB Inputs Only)

0.8

IHH

Input HIGH Voltage

(1)

3-Level Inputs Only

IMM

Input MID Voltage

(1)

3-Level Inputs Only

0.5

/2+0.5

ILL

Input LOW Voltage

(1)

3-Level Inputs Only

Input Leakage Current

= V

or GND

±5

µA

(REF, FB Inputs Only)

= Max.

= V

HIGH Level

±200

3-Level Input DC Current (TEST, FS, nF

1:0

)

= V

MID Level

±50

µA

= GND

LOW Level

±200

Input Pull-Up Current (V

CCQ

/PE)

= Max., V

= GND

±100

µA

Input Pull-Down Current (GND/sOE)

= Max., V

= V

±100

µA

Output HIGH Voltage

= Min., I

16mA

2.4

= Min., I

40mA

Output LOW Voltage

= Min., I

= 46mA

0.45

Output Short Circuit Current

(2)

= Max., V

= GND

250

NOTES:
1. These inputs are normally wired to V

, GND, or unconnected. Internal termination resistors bias unconnected inputs to V

/2. If these inputs are switched, the function and

timing of the outputs may be glitched, and the PLL may require an additional t

LOCK

time before all datasheet limits are achieved.

2. This is to be measured at 25

°C

with 10:1 duty cycle, one output at a time, and one second maximum.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

IDT5993A-2

IDT5993A-5

IDT5993A-7

Symbol Parameter

Min.

Typ.

Max.

Min.

Typ.

Max.

Min.

Typ.

Max.

Unit

NOM

VCO Frequency Range

See PLL Programmable Skew Range and Resolution Table

RPWH

REF Pulse Width HIGH

(1)

RPWL

REF Pulse Width LOW

(1)

Programmable Skew Time Unit

See Skew Selection Table for Output Pairs

SKEWPR

Zero Output Matched-Pair Skew (xQ

, xQ

)

(1,2,3)

0.05

0.2

0.1

0.25

0.1

0.25

SKEW0

Zero Output Skew (All Outputs)

(1,4,5)

0.1

0.25

0.5

0.3

0.75

SKEW1

Output Skew

0.25

0.5

0.6

0.7

0.6

(Rise-Rise, Fall-Fall, Same Class Outputs)

(1,3)

SKEW2

Output Skew

0.5

1.2

0.5

1.5

(Rise-Fall, Divided-Divided)

(1,6)

SKEW3

Output Skew

0.25

0.5

0.7

1.2

(Rise-Rise, Fall-Fall, Different Class Outputs)

(1,6)

SKEW4

Output Skew

0.5

0.9

0.5

1.2

1.7

(Rise-Fall, Nominal-Divided)

(1,2)

DEV

Device-to-Device Skew

(1,2,7)

0.75

1.25

1.65

REF Input to FB Propagation Delay

(1,9)

0.25

0.5

0.7

ODCV

Output Duty Cycle Variation from 50%

(1)

1.2

PWH

Output HIGH Time Deviation from 50%

(1,10)

2.5

PWL

Output LOW Time Deviation from 50%

(1,11)

1.5

3.5

ORISE

Output Rise Time

(1)

0.15

1.2

0.15

1.5

0.15

1.5

2.5

OFALL

Output Fall Time

(1)

0.15

1.2

0.15

1.5

0.15

1.5

2.5

LOCK

PLL Lock Time

(7)

0.5

Cycle-to-Cycle Output Jitter

RMS

Peak-to-Peak

200

NOTES:
1. All timing and jitter tolerances apply for F

NOM

> 25MHz.

2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t

delay has been selected when all are loaded with the specified

load.

3. t

SKEWPR

is the skew between a pair of outputs (xQ

and xQ

) when all eight outputs are selected for 0t

4. t

SKEW0

is the skew between outputs when they are selected for 0t

5. For IDT5993A-2 t

SKEW0

is measured with C

= 0pF; for C

= 30pF, t

SKEW0

= 0.35ns Max.

6. There are two classes of outputs: Nominal (multiple of t

delay), and Divided (3Qx only in Divide-by-2 or Divide-by-4 mode).

7. t

DEV

is the output-to-output skew between any two devices operating under the same conditions (V

, ambient temperature, air flow, etc.)

8. t

LOCK

is the time that is required before synchronization is achieved. This specification is valid only after V

is stable and within normal operating limits. This parameter is

measured from the application of a new signal or frequency at REF or FB until t

is within specified limits.

9. t

is measured with REF input rise and fall times (from 0.8V to 2V) of 1ns.

10. Measured at 2V.
11. Measured at 0.8V.

INPUT TIMING REQUIREMENTS

Symbol

Description

(1)

Min.

Max.

Unit

, t

Maximum input rise and fall times, 0.8V to 2V

ns/V

PWC

Input clock pulse, HIGH or LOW

Input duty cycle

Reference Clock Input

3.75

100

MHz

NOTE:
1. Where pulse width implied by D

is less than t

PWC

limit, t

PWC

limit applies.

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

IDT5993A
PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK

REF D IVIDE D B Y 2

REF D IVIDE D B Y 4

SKEW 1 , 3, 4

SKEW 2

SKEW 3

REF

F B

OTH ER Q

R EF

SKEWP R

SKEW0 , 1

SKEW P R

SKEW 0 , 1

OD CV

RPW H

R PW L

SKEW 3 , 4

NOTES:

CCQ

/PE: The AC Timing Diagram applies to V

CCQ

/PE=V

. For V

CCQ

/PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the

negative edge of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.

Skew:

The time between the earliest and the latest output transition among all outputs for which the same t

delay has been selected when all are loaded with 50pF (30pF for

-2 and -5) and terminated with 50

to 2.06V.

SKEWPR

The skew between a pair of outputs (xQ

and xQ

) when all eight outputs are selected for 0t

SKEW0

The skew between outputs when they are selected for 0t

DEV

The output-to-output skew between any two devices operating under the same conditions (V

ambient temperature, air flow, etc.)

ODCV

The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

SKEW2

and t

SKEW4

specifications.

PWH

is measured at 2V.

PWL

is measured at 0.8V.

ORISE

and t

OFALL

are measured between 0.8V and 2V.

LOCK

The time that is required before synchronization is achieved. This specification is valid only after V

is stable and within normal operating limits. This parameter is measured

from the application of a new signal or frequency at REF or FB until t

is within specified limits.

AC TIMING DIAGRAM

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