INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

JUNE 2002

2002 Integrated Device Technology, Inc.

DSC 5974/8

INDUSTRIAL TEMPERATURE RANGE

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

FEATURES:

· Ref input is 5V tolerant
· 8 pairs of programmable skew outputs
· Two separate A and B banks for individual control
· Low skew: 185ps same pair, 250ps same bank, 350ps both

banks

· Selectable positive or negative edge synchronization on each

bank: excellent for DSP applications

· Synchronous output enable on each bank
· Input frequency: 2MHz to 200MHz
· Output frequency: 6MHz to 200MHz
· 3-level inputs for skew and PLL range control
· 3-level inputs for feedback divide selection multiply / divide

ratios of (1-6, 8, 10, 12) / (2, 4)

· PLL bypass for DC testing
· External feedback, internal loop filter
· 12mA balanced drive outputs
· Low Jitter: <100ps cycle-to-cycle
· Power-down mode on each bank
· Lock indicator on each bank
· Available in BGA package

FUNCTIONAL BLOCK DIAGRAM

LOCK

PLL

BsOE

/ N

Skew

Select

Skew

Select

Skew

Select

Skew

Select

B1Q

B1F1:0

B2Q

B2F1:0

BDS1:0

B3Q

B3F1:0

B4Q

B4F1:0

BPD

LOCK

PLL

sOE

REF

/ N

Skew

Select

A1Q

A1F1:0

A2Q

A2F1:0

ADS1:0

A3Q

A3F1:0

A4Q

A4F1:0

APD

TEST

Skew

Select

Skew

Select

Skew

Select

IDT5V9955

PRELIMINARY

3.3V PROGRAMMABLE

SKEW DUAL PLL CLOCK
DRIVER TURBOCLOCKTM W

DESCRIPTION

The IDT5V9955 is a high fanout 3.3V PLL based clock driver intended

for high performance computing and data-communications applications. A
key feature of the programmable skew is the ability of outputs to lead or lag
the REF input signal. The IDT5V9955 has sixteen programmable skew
outputs in eight banks of 2. The two separate PLLs allow the user to
independently control A and B banks. Skew is controlled by 3-level input
signals that may be hard-wired to appropriate HIGH-MID-LOW levels.

The feedback input allows divide-by-functionality from 1 to 12 through

the use of the xDS[1:0] inputs. This provides the user with frequency
multiplication from 1 to 12 without using divided outputs for feedback.

When the xsOE pin is held low, all the xbank outputs are synchronously

enabled. However, if xsOE is held high, all the xbank outputs except x2Q0
and x2Q1 are synchronously disabled. The xLOCK is high when the
xbank PLL has achieved phase lock.

Furthermore, when xPE is held high, all the outputs are synchronized

with the positive edge of the REF clock input. When xPE is held low, all the
xbank outputs are synchronized with the negative edge of REF. The
IDT5V9955 has LVTTL outputs with 12mA balanced drive outputs.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

PIN CONFIGURATION

96 BALL FPBGA PACKAGE ATTRIBUTES

A3Q

AGND

AFB

A2Q

A4Q

AGND

A1Q

AGND

DDQ

ADS0

LOCK

A4F

A1F

ADS

AFS

DDQ

REF

AGND

A2F

B2F

TEST

BGND

A4Q

AGND

A1Q

DDQ

A3F

A2F

A1F

DDQ

BFS

B1F

B2F

DDQ

B3F

BDS

B1F

B4F

DDQ

BGND

BFB

BGND

LOCK

BDS

DDQ

B1Q

B4Q

BGND

B1Q

B4Q

B2Q

B3Q

FPBGA

TOP VIEW

1.5mm Max.

1.4mm Nom.

1.3mm Min.

0.8mm

TOP VIEW

13.5mm

5.5mm

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

NOTE:
1. Capacitance applies to all inputs except TEST, xFS, xnF

[1:0]

, and xDS

[1:0]

CAPACITANCE

= +25°C, f = 1MHz, V

= 0V)

Parameter

Description

Typ.

Max.

Unit

Input Capacitance

REF

Others

NOTE:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause

permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Description

Max

Unit

DDQ

, V

Supply Voltage to Ground

0.5 to +4.6

DC Input Voltage

0.5 to V

+0.5

REF Input Voltage

0.5 to +5.5

Maximum Power

= 85°C

1.1

Dissipation

= 55°C

1.9

STG

Storage Temperature Range

65 to +150

°C

NOTE:
1. When TEST = MID and xsOE = HIGH, PLL remains active

with xnF[

1:0

] = LL functioning as an output disable control for individual output banks. Skew selections remain

in effect unless xnF[

1:0

] = LL.

PIN DESCRIPTION

Pin Name

Type

Description

REF

Reference Clock Input

xFB

Individual Feedback Inputs for A and B banks

TEST

(1)

When MID or HIGH, disables PLL for A and B banks (except for conditions of Note 1). REF goes to all outputs. Skew Selections (See
Control Summary Table) remain in effect. Set LOW for normal operation.

xsOE

(1)

Individual Synchronous Output Enable for A and B banks. When HIGH, it stops clock outputs (except x2Q

and x2Q

) in a LOW state

(for xPE = H) - x2Q

and x2Q

may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE

is HIGH, the nF[

1:0

] pins act as output disable controls for individual banks when xnF[

1:0

] = LL. Set xsOE LOW for normal operation

(has internal pull-down).

xPE

Individual Selectable positive or negative edge control for A and B banks. When LOW/HIGH the outputs are synchronized with the negative/
positive edge of the reference clock (has internal pull-up).

xnF

[1:0]

3-level inputs for selecting 1 of 9 skew taps or frequency functions

xFS

Selects appropriate oscillator circuit based on anticipated frequency range. (See Programmable Skew Range.) Individual control on A
and B banks.

xnQ

[1:0]

OUT

Eight banks of two outputs with programmable skew

xDS

[1:0]

3-level inputs for feedback divider selection for A and B banks

xPD

Power down control. Shuts off either A or B bank of the chip when LOW (has internal pull-up).

xLOCK

OUT

PLL lock indication signal for A and B banks. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be
synchronized to the inputs.

DDQ

PWR

Power supply for output buffers

PWR

Power supply for phase locked loop, lock output, and other internal circuitry

GND

PWR

Ground

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

Output skew with respect to the REF input is adjustable to compensate

for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t

) which ranges

from 625ps to 1.3ns (see Programmable Skew Range and Resolution
Table). There are nine skew configurations available for each output
pair. These configurations are chosen by the xnF

1:0

control pins. In

order to minimize the number of control pins, 3-level inputs (HIGH-MID-
LOW) are used, they are intended for but not restricted to hard-wiring.
Undriven 3-level inputs default to the MID level. Where programmable
skew is not a requirement, the control pins can be left open for the zero
skew default setting. The Control Summary Table shows how to select
specific skew taps by using the xnF

1:0

control pins.

PROGRAMMABLE SKEW

EXTERNAL FEEDBACK

By providing two separate external feedbacks, the IDT5V9955 gives

users flexibility with regard to skew adjustment. The xFB signal is com-
pared with the input REF signal at the phase detector in order to drive
the VCO. Phase differences cause the VCO of the PLL to adjust up-
wards or downwards accordingly.

NOTES:
1. The device may be operated outside recommended frequency ranges without damage, but functional operation is not guaranteed.
2. The level to be set on xFS is determined by the nominal operating frequency of the VCO and Time Unit Generator. The VCO frequency always appears at x1Q

1:0

, x2Q

1:0

, and

the higher outputs when they are operated in their undivided modes. The frequency appearing at the REF and xFB inputs will be F

NOM

when the output connected to xFB is

undivided and xDS[

1:0

] = MM. The frequency of the REF and xFB inputs will be F

NOM

/2 or F

NOM

/4 when the part is configured for frequency multiplication by using a divided

output as the xFB input and setting xDS[

1:0

] = MM. Using the xDS[

1:0

] inputs allows a different method for frequency multiplication (see Divide Selection Table).

3. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed xQ output is used for feedback, then adjustment range will be greater. For example

if a 4t

skewed output is used for feedback, all other outputs will be skewed 4t

in addition to whatever skew value is programmed for those outputs. `Max adjustment' range

applies to output pairs 3 and 4 where ± 6t

skew adjustment is possible and at the lowest F

NOM

value.

An internal loop filter moderates the response of the VCO to the

phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.

xFS = LOW

xFS = MID

xFS = HIGH

Comments

Timing Unit Calculation (t

)

1/(32 x F

NOM

)

1/(16 x F

NOM

)

1/(8 x F

NOM

)

VCO Frequency Range (F

NOM

)

(1,2)

24 to 50MHz

48 to 100MHz

96 to 200MHz

Skew Adjustment Range

(3)

Max Adjustment:

±7.8125ns

±67.5°

±135°

±270°

Phase Degrees

±18.75%

±37.5%

±75%

% of Cycle Time

Example 1, F

NOM

= 25MHz

= 1.25ns

Example 2, F

NOM

= 37.5MHz

= 0.833ns

Example 3, F

NOM

= 50MHz

= 0.625ns

= 1.25ns

Example 4, F

NOM

= 75MHz

= 0.833ns

Example 5, F

NOM

= 100MHz

= 0.625ns

= 1.25ns

Example 6, F

NOM

= 150MHz

= 0.833ns

Example 7, F

NOM

= 200MHz

= 0.625ns

PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

DIVIDE SELECTION TABLE

xDS [

1:0

]

xFB Divide-by-n

Permitted Output Divide-by-n connected to xFB

(1)

1 or 2

1, 2, or 4

1 or 2

M M

1, 2, or 4

M H

1 or 2

H M

H H

NOTE:
1. Permissible output division ratios connected to xFB. The frequency of the REF input will be F

NOM

/N when the part is configured for frequency multiplication by using an undivided

output for xFB and setting xDS[

1:0

] to N (N = 1-6, 8, 10, 12).

CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS

nF1:0

Skew (Pair #1, #2)

Skew (Pair #3)

Skew (Pair #4)

(1)

Divide by 2

M M

Zero Skew

M H

H M

H H

Divide by 4

Inverted

(2)

NOTES:
1. LL disables outputs if TEST = MID and xsOE = HIGH.
2. When pair #4 is set to HH (inverted), xsOE disables pair #4 HIGH when xPE = HIGH, xsOE disables pair #4 LOW when xPE = LOW.

RECOMMENDED OPERATING RANGE

Symbol

Description

Min.

Typ.

Max.

Unit

DDQ

Power Supply Voltage

3.3

3.6

Ambient Operating Temperature

-40

+25

+85

°C

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

POWER SUPPLY CHARACTERISTICS

Symbol

Parameter

Test Conditions

(1)

Typ.

(2)

Max.

Unit

DDQ

Quiescent Power Supply Current

= Max., TEST = MID, REF = LOW,

xPE = LOW, xsOE = LOW, xPD = HIGH
xFS = MID, All outputs unloaded

DDPD

Power Down Current

= Max., PD = LOW, xsOE = LOW

µA

xPE = HIGH, TEST = HIGH, xFS = HIGH
xnF

[1:0]

= HH, xDS

[1:0]

= HH

Power Supply Current per Input HIGH

= 3V, V

= Max., xPD = LOW, TEST = HIGH

µA

(REF and xFB inputs only)

xFS = L

190

290

DDD

Dynamic Power Supply Current per Output

xFS = M

150

230

µA/MHz

xFS = H

130

200

xFS = L, F

VCO

= 50MHz, C

= 0pF

112

TOT

Total Power Supply Current

xFS = M, F

VCO

= 100MHz, C

= 0pF

160

xFS = H, F

VCO

= 200MHz, C

= 0pF

250

DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Conditions

(1)

Min.

Max.

Unit

Input HIGH Voltage

Guaranteed Logic HIGH (REF, xFB Inputs Only)

Input LOW Voltage

Guaranteed Logic LOW (REF, xFB Inputs Only)

0.8

IHH

Input HIGH Voltage

(2)

3-Level Inputs Only

0.6

IMM

Input MID Voltage

(2)

3-Level Inputs Only

0.3

/2+0.3

ILL

Input LOW Voltage

(2)

3-Level Inputs Only

0.6

Input Leakage Current

= V

or GND

µA

(REF, xFB Inputs Only)

= Max.

= V

HIGH Level

+400

3-Level Input DC Current

= V

MID Level

100

+100

µA

(TEST, xFS, xnF

[1:0]

, xDS

[1:0]

)

= GND

LOW Level

400

Input Pull-Up Current (xPE, xPD)

= Max., V

= GND

µA

Input Pull-Down Current (xsOE)

= Max., V

= V

+100

µA

Output HIGH Voltage

= Min., I

2mA (xLOCK Output)

2.4

DDQ

= Min., I

12mA (xnQ

[1:0]

Outputs)

2.4

Output LOW Voltage

= Min., I

= 2mA (xLOCK Output)

0.4

DDQ

= Min., I

= 12mA (xnQ

[1:0]

Outputs)

0.4

NOTES:
1. All conditions apply to A and B banks.
2. These inputs are normally wired to V

, GND, or unconnected. Internal termination resistors bias unconnected inputs to V

/2. If these inputs are switched, the function and timing

of the outputs may be glitched, and the PLL may require an additional t

LOCK

time before all datasheet limits are achieved.

NOTES:
1. Measurements are for divide-by-1 outputs, xnF

[1:0]

= MM, and xDS

[1:0]

= MM. All conditions apply to A and B banks.

2. For nominal voltage and temperature.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

SWITCHING CHARACTERISTICS OVER OPERATING RANGE

Symbol

Parameter

Min.

Typ.

Max.

Unit

NOM

VCO Frequency Range

See Programmable Skew Range and Resolution Table

RPWH

REF Pulse Width HIGH

(1)

RPWL

REF Pulse Width LOW

(1)

Programmable Skew Time Unit

See Control Summary Table

SKEWPR

Zero Output Matched-Pair Skew (xnQ

, xnQ

)

(2,3)

185

SKEWB

Bank Skew

(4)

0.1

0.35

SKEW0

Zero Output Skew (All Outputs from the same A or B bank)

(5)

0.1

0.25

SKEW1

Output Skew (Rise-Rise, Fall-Fall, Same Class Outputs)

(6)

0.1

0.25

SKEW2

Output Skew (Rise-Fall, Nominal-Inverted, Divided-Divided)

(6)

0.2

0.5

SKEW3

Output Skew (Rise-Rise, Fall-Fall, Different Class Outputs)

(6)

0.15

0.5

SKEW4

Output Skew (Rise-Fall, Nominal-Divided, Divided-Inverted)

(2)

0.3

0.9

DEV

Device-to-Device Skew

(2,7)

0.75

(

)1-3

Static Phase Offset (xFS = L, M, H) (FB Divide-by-n = 1, 2, 3)

(8)

0.25

(

Static Phase Offset (xFS = H)

(8)

0.25

(

Static Phase Offset (xFS = M)

(8)

0.5

(

)L1-6

Static Phase Offset (xFS = L) (xFB Divide-by-n = 1, 2, 3, 4, 5, 6)

(8)

0.7

(

)L8-12

Static Phase Offset (xFS = L) (xFB Divide-by-n = 8, 10, 12)

(8)

ODCV

Output Duty Cycle Variation from 50%

PWH

Output HIGH Time Deviation from 50%

(9)

1.5

PWL

Output LOW Time Deviation from 50%

(10)

ORISE

Output Rise Time

0.15

0.7

1.5

OFALL

Output Fall Time

0.15

0.7

1.5

LOCK

PLL Lock Time

(11,12)

0.5

CCJH

Cycle-to-Cycle Output Jitter (peak-to-peak)

100

(divide by 1 output frequency, xFS = H, FB divide-by-n=1,2)

CCJHA

Cycle-to-Cycle Output Jitter (peak-to-peak)

150

(divide by 1 output frequency, xFS = H, FB divide-by-n=any)

CCJM

Cycle-to-Cycle Output Jitter (peak-to-peak)

150

(divide by 1 output frequency, xFS = M)

CCJL

Cycle-to-Cycle Output Jitter (peak-to-peak)

200

(divide by 1 output frequency, xFS = L, F

REF

> 3MHz)

CCJLA

Cycle-to-Cycle Output Jitter (peak-to-peak)

300

(divide by 1 output frequency, xFS = L, F

REF

< 3MHz)

NOTES:
1. Refer to Input Timing Requirements table for more detail.
2. Skew is the time between the earliest and the latest output transition among all outputs for which the same t

delay has been selected when all are loaded with the specified

load.

3. t

SKEWPR

is the skew between a pair of outputs (xnQ0 and xnQ1) when all sixteen outputs are selected for 0t

4. t

SKEWB

is the skew between outputs (xnQ0 and xnQ1) from A and B banks when they are selected for 0t

5. t

SK(0)

is the skew between outputs when they are selected for 0t

6. There are 3 classes of outputs: Nominal (multiple of t

delay), Inverted (x4Q0 and x4Q1 only with x4F0 = x4F1 = HIGH), and Divided (x3Q1:0 and x4Q1:0 only in Divide-

by-2 or Divide-by-4 mode). Test condition: xnF0:1=MM is set on unused outputs.

7. t

DEV

is the output-to-output skew between any two devices operating under the same conditions (V

DDQ

, V

, ambient temperature, air flow, etc.)

8. t

is measured with REF input rise and fall times (from 0.8V to 2V) of 0.5ns. Measured from 1.5V on REF to 1.5V on xFB.

8. Measured at 2V.
10. Measured at 0.8V.
11. t

LOCK

is the time that is required before synchronization is achieved. This specification is valid only after V

DDQ

is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or xFB until t

is within specified limits.

12. Lock detector may be unreliable for input frequencies less than approximately 4MHz, or for input signals which contain significant jitter.

INDUSTRIAL TEMPERATURE RANGE

IDT5V9955
3.3V PROGRAMMABLE SKEW DUAL PLL CLOCK DRIVER TURBOCLOCK W

REF

OTHER Q

INVERTED Q

REF DIVIDED BY 2

REF DIVIDED BY 4

REF

SKEW2

SKEW3, 4

SKEW1, 3, 4

SKEW2, 4

SKEW3, 4

SKEW2

CCJH, HA,

M, L, LA

ODCV

RPWH

RPWL

SKEWPR,B

SKEW0, 1

(

)

SKEWPR,B

SKEW0, 1

AC TIMING DIAGRAM

NOTES:
PE:

The AC Timing Diagram applies to PE=V

. For PE=GND, the negative edge of FB aligns with the negative edge of REF, divided outputs change on the negative edge

of REF, and the positive edges of the divide-by-2 and the divide-by-4 signals align.

Skew:

The time between the earliest and the latest output transition among all outputs for which the same t

delay has been selected when all are loaded with 20pF and terminated

with 75

to V

DDQ

/2.

SKEWPR

The skew between a pair of outputs (xnQ

and xnQ

) when all eight outputs are selected for 0t

SKEWB

The skew between outputs (xnQ

and xnQ

) from A and B banks when they are selected for 0t

SKEW0

The skew between outputs when they are selected for 0t

DEV

The output-to-output skew between any two devices operating under the same conditions (V

DDQ

, ambient temperature, air flow, etc.)

ODCV

The deviation of the output from a 50% duty cycle. Output pulse width variations are included in t

SKEW2

and t

SKEW4

specifications.

PWH

is measured at 2V.

PWL

is measured at 0.8V.

ORISE

and t

OFALL

are measured between 0.8V and 2V.

LOCK

The time that is required before synchronization is achieved. This specification is valid only after V

DDQ

is stable and within normal operating limits. This parameter

is measured from the application of a new signal or frequency at REF or FB until t

is within specified limits.

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