1
INDUSTRIAL TEMPERATURE RANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
DECEMBER 2001
2001 Integrated Device Technology, Inc.
DSC 5855/4
c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
3.3V operation
4 pairs of programmable skew outputs
Low skew: 150ps same pair, 350ps all outputs
Selectable positive or negative edge synchronization:
Excellent for DSP applications
Synchronous output enable
Input frequency: 25MHz to 225MHz
Output frequency: 25MHz to 225MHz
2x, 4x, 1/2, and 1/4 outputs (of VCO frequency)
3-level inputs for skew control
PLL bypass for DC testing
External feedback, internal loop filter
12mA balanced drive outputs
Low Jitter: <150ps peak-to-peak
Available in 144-pin BGA package
FUNCTIONAL BLOCK DIAGRAM
IDT5V996
3.3V PROGRAMMABLE
SKEW PLL CLOCK DRIVER
TURBOCLOCK
TM
II PLUS
PLL
Skew
Select
1F2:0
Skew
Select
4F2:0
Skew
Select
3F2:0
Skew
Select
2F2:0
LOC K
FB
REF
TEST
1Q0
1Q 1
2Q0
2Q1
3Q 0
3Q1
4Q0
4Q 1
3
3
3
SE
Enable
Logic
3
3
3
3
3
3
3
3
3
G
DESCRIPTION:
The IDT5V996 is a high fanout PLL based clock driver intended for high
performance computing and data-communication applications. The IDT5V996
has eight programmable skew outputs organized in four banks of two. Skew
is controlled by 3-level input signals that may be hard wired to appropriate
HIGH-MID-LOW levels. The IDT5V996 provides up to 18 programmable
levels of output skew, prescaling, and other features.
Other features of IDT5V996 are synchronous output enable (G), TEST,
and lock detect indicator (LOCK). When G is held low, all the outputs are
synchronously enabled, however, if G is held high, all outputs except 3Q0
and 3Q1 are in the state designated by SE (HIGH or LOW).
When TEST is held low, the chip operates in normal condition. When held
high, the PLL is shut off and the chip functions as a buffer. The lock detect
indicator asserts high when the phase lock loop has acquired lock. During
acquisition, the indicator is in the low state. Once the PLL has reached the
steady-state condition within a specified frequency range, LOCK is
asserted high.
The PLL is closed externally to provide more flexibility by allowing the
user to control the delay between the input clock and the outputs. The
IDT5V996 has LVTTL outputs with 12mA balanced drive outputs.
The IDT5V996 is characterized for operation from 40C to +85C.
2
INDUSTRIAL TEMPERATURE RANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
A
B
C
D
E
F
G
H
J
K
L
M
1
2
3
4
5
6
7
8
9
10
11
12
1
2
G
R EF
FB
SE
V
DD Q
V
D DQ
V
DD Q
V
DD Q
V
D D Q
V
DD Q
V
D DQ
V
D DQ
3
4
5
6
7
8
9
10
11
12
V
D D Q
V
D D Q
V
D DQ
V
D D Q
V
D D Q
V
D D Q
V
D D Q
V
D DQ
V
DD Q
V
D D Q
V
D DQ
TEST
2Q 1
2Q0
1Q1
1Q 0
LOCK
2F2
2F0
1F1
4F1
3F0
3F2
2F1
1F2
1F0
4F0
4F2
3F1
3Q 1
3Q0
4Q1
4Q0
V
DD Q
V
DD Q
V
DD Q
V
DD Q
V
DD
V
DD
V
D D
V
DD
V
D D
V
DD
V
DD
V
DD
G ND
GN D
V
D D
V
D D
G ND
G ND
G ND
G ND
G ND
G ND
G ND
G ND
GN D
G ND
GND
GND
G ND
GND
GN D
GN D
G ND
GN D
GND
V
D D
V
D D
G ND
G ND
G ND
GN D
G ND
GN D
V
DD
V
D D
GND
GN D
GND
GND
GN D
GN D
V
D D
V
D D
GND
GN D
GND
GN D
GN D
GND
V
DD
V
D D
G ND
G ND
G ND
G ND
G ND
G ND
V
DD
V
D D
GN D
GN D
GN D
GND
GN D
GND
V
D D Q
V
D D Q
V
D D Q
V
D D Q
V
D D
V
D D
V
D D
V
D D
V
D D
V
D D
V
D D
V
D D
V
D DQ
V
D DQ
V
D DQ
V
D DQ
V
D DQ
V
D DQ
V
D DQ
V
D DQ
V
D DQ
V
D D Q
V
D DQ
V
D DQ
BGA
TOP VIEW
3
INDUSTRIAL TEMPERATURE RANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
NOTES:
1. Stresses beyond those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. These are stress ratings only, and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute-
maximum-rated conditions for extended periods may affect device reliability.
2. The input and output negative-voltage ratings may be exceeded if the input and
output clamp-current ratings are observed.
Output skew with respect to the REF input is adjustable to compensate
for PCB trace delays, backplane propagation delays or to accommodate
requirements for special timing relationships between clocked compo-
nents. Skew is selectable as a multiple of a time unit (t
U
) which ranges
from 278ps to 625ps (see Programmable Skew Range and Resolution
Table). There are 16 skew configurations available for each output pair.
These configurations are chosen by the nF
2:0
control pins. In order to
minimize the number of control pins, 3-level inputs (HIGH-MID-LOW)
are used, they are intended for but not restricted to hard-wiring. Undriven
3-level inputs default to the MID level. Where programmable skew is
not a requirement, the control pins can be left open for the zero skew
default setting. The Control Summary Table shows how to select specific
skew taps by using the nF
2:0
control pins.
PROGRAMMABLE SKEW
ABSOLUTE MAXIMUM RATINGS
(1)
Symbol
Description
Max
Unit
V
DDQ
, V
DD
Supply Voltage Range
0.5 to +4.6
V
V
I
(2)
Input Voltage Range
0.5 to 4.6
V
V
O
(2)
Voltage range applied to any
0.5 to
V
output in the high or low state
V
DDQ
+ 0.5
I
IK
(V
I
< 0)
Input Clamp Current
50
mA
I
O
(V
O
= 0 to V
DDQ
) Continuous Output Current
50
mA
V
DDQ
or GND
Continuous Current
100
mA
T
STG
Storage Temperature Range
65 to +150
C
NOTES:
1. Unused inputs must be held high or low to prevent them from floating.
2. Capacitance applies to all inputs except nF
2:0
. This value is characterized but not
production tested.
CAPACITANCE
(1,2)
(T
A
= +25C, f = 1MHz, V
IN
= 0V)
Parameter
Description
Min
Typ.
Max.
Unit
C
IN
Input Capacitance
--
8
--
pF
V
I
= V
DDQ
or GND
PIN DESCRIPTION
Pin Name
Type
Description
REF
IN
Reference Clock Input
SE
IN
Selectable positive or negative edge control. When LOW / HIGH, the outputs are synchronized with the negative/positive edge of the
reference clock. When outputs are synchronously stopped with the G pin, SE determines the level at which outputs stop. When SE is
LOW/HIGH, outputs synchronously stop HIGH/LOW.
FB
IN
Feedback Input
G
IN
Output gate for "true" nQ
[1:0]
outputs. When G is LOW, the "true" nQ
[1:0]
outputs are enabled. When G is HIGH, the "true" nQ
[1:0]
outputs
are in the state designated by SE (HIGH or LOW) (except 3Q
0
and 3Q
1
) - 3Q
0
and 3Q
1
may be used as the feedback signal to maintain
phase lock.
TEST
IN
TEST = LOW means normal operation. TEST = HIGH means that the PLL is powered down and REF is routed to all the outputs. The
skews selected with the nF
[2:0]
pins are still in effect. (The TEST pin is a TTL input.)
nF[
2:0
]
IN
3-level inputs for selecting 1 of 18 skew taps or frequency functions
nQ[
1:0
]
OUT
Clock Output Pairs
V
DDQ
PWR
Power supply for output buffers
V
DD
PWR
Power supply for phase locked loop and other internal circuitry
GND
PWR
Ground
LOCK
OUT
Lock Detect. Asserted (HIGH) when the PLL is locked. The REF input must be oscillating.
4
INDUSTRIAL TEMPERATURE RANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
EXTERNAL FEEDBACK
By providing external feedback, the IDT5V996 gives users flexibility
with regard to skew adjustment. The FB signal is compared with the
input REF signal at the phase detector in order to drive the VCO. Phase
differences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
CONTROL SUMMARY TABLE FOR FEEDBACK SIGNALS
(1)
nF
2
nF
1
nF
0
Output Skew
L
L
L
Disable
(2)
L
H
L
-7t
U
L
H
M
-6t
U
L
H
H
-5t
U
M
L
L
-4t
U
M
L
M
-3t
U
M
L
H
-2t
U
M
M
L
-1t
U
M
M
M
Zero Skew
M
M
H
+1t
U
M
H
L
+2t
U
M
H
M
+3t
U
M
H
H
+4t
U
H
L
L
+5t
U
H
L
M
+6t
U
H
L
H
+7t
U
H
M
L
Inverted
H
M
M
Divide by 2
H
M
H
Divide by 4
Comments
Timing Unit Calculation (t
U
)
1/(16 x F
NOM
)
VCO Frequency Range (F
NOM
)
(1)
100 to 225 MHz
Skew Adjustment Range
(2)
Max Adjustment:
4.375ns
ns
157.5
Phase Degrees
43.75%
% of Cycle Time
Example 1, F
NOM
= 100MHz
t
U
= 0.625ns
--
Example 2, F
NOM
= 167MHz
t
U
= 0.374ns
--
Example 3, F
NOM
= 225MHz
t
U
= 0.278ns
--
PLL PROGRAMMABLE SKEW RANGE AND RESOLUTION TABLE
NOTES:
1. The VCO frequency always appears at nQ
1:0
outputs when they are operated in their undivided modes. The frequency appearing at the REF and FB inputs will be F
NOM
when
the output connected to FB is undivided. The frequency of the REF and FB inputs will be F
NOM
/2 or F
NOM
/4 when the part is configured for frequency multiplication by using
a divided output as the FB input. Using the nF[
2:0
] inputs allows a different method for frequency multiplication (see Control Summary Table for Feedback Signals).
2. Skew adjustment range assumes that a zero skew output is used for feedback. If a skewed Q output is used for feedback, then adjustment range will be greater. For example
if a 4t
U
skewed output is used for feedback, all other outputs will be skewed 4t
U
in addition to whatever skew value is programmed for those outputs. `Max adjustment' range
applies to all output pairs where 7t
U
skew adjustment is possible and at the lowest F
NOM
value.
NOTES:
1. All unused/unnoted combinations are reserved.
2. When G is LOW, all output pairs are individually disabled to the level designated by SE. When SE is LOW/HIGH, output pairs disable HIGH/LOW.
5
INDUSTRIAL TEMPERATURE RANGE
IDT5V996
3.3V PROGRAMMABLE SKEW PLL CLOCK DRIVER TURBOCLOCK II PLUS
RECOMMENDED OPERATING RANGE
Symbol
Description
Min.
Typ.
Max.
Unit
V
DD
/ V
DDQ
Power Supply Voltage
3
3.3
3.6
V
T
A
Ambient Operating Temperature
-40
+25
+85
C
POWER SUPPLY CHARACTERISTICS
Symbol
Parameter
Test Conditions
(1)
Typ.
(2)
Max.
Unit
I
DDQ
Quiescent Power Supply Current
V
DDQ
= Max., REF = FB = SE = G = LOW,
--
30
mA
TEST = HIGH, All nF
2:0
= HHM
(3)
,
All outputs floating
I
DDD
Dynamic Power Supply Current per Output
V
DDQ
= Max., C
L
= 0pF
410
650
A/MHz
V
DDQ
= 3.3V, F
VCO
= 100MHz, C
L
= 20pF
124
--
I
TOT
Total Power Supply Current
V
DDQ
= 3.3V, F
VCO
= 167MHz, C
L
= 20pF
197
--
mA
V
DDQ
= 3.3V, F
VCO
= 225MHz, C
L
= 20pF
253
--
NOTES:
1. Measurements are for divide-by-1 outputs.
2. For nominal voltage and temperature.
3. This configuration is only specific for I
DDQ
measurements.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol
Parameter
Conditions
Min.
Max.
Unit
V
IH
Input HIGH Voltage
Guaranteed Logic HIGH (REF, FB Inputs Only)
2
--
V
V
IL
Input LOW Voltage
Guaranteed Logic LOW (REF, FB Inputs Only)
--
0.8
V
V
IHH
Input HIGH Voltage Level
(1)
3-Level Inputs Only
V
DD
-
0.6
--
V
V
IMM
Input MID Voltage Level
(1)
3-Level Inputs Only
V
DD
/2
-
0.3
V
DD
/2+0.3
V
V
ILL
Input LOW Voltage Level
(1)
3-Level Inputs Only
--
0.6
V
I
IN
Input Leakage Current
V
IN
= V
CC
or GND
-5
+5
A
(REF, FB Inputs Only)
V
CC
= Max.
V
IN
= V
DD
HIGH Level
--
+200
I
3
3-Level Input DC Current (nF
2:0
)
V
IN
= V
DD
/2
MID Level
-50
+50
A
V
IN
= GND
LOW Level
-200
--
V
OH
Output HIGH Voltage Level
V
DD
= Min., I
OH
=
-
12mA
2.4
--
V
V
OL
Output LOW Voltage Level
V
DD
= Min., I
OL
= 12mA
--
0.4
V
NOTE:
1. These inputs are normally wired to V
DDQ
, GND, or unconnected. Internal termination resistors bias unconnected inputs to V
DDQ
/2. If these inputs are switched, the function and
timing of the outputs may be glitched, and the PLL may require an additional t
LOCK
time before all datasheet limits are achieved.
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