FEBRUARY 2000

DSC-3242/10

Functional Block Diagram

Features:

True Dual-Ported memory cells which allow simultaneous
access of the same memory location

High-speed clock to data access
 Commercial: 9/12/15ns (max.)

Low-power operation
 IDT709089S

Active: 950mW (typ.)
Standby: 5mW (typ.)

 IDT709089L

Active: 950mW (typ.)
Standby: 1mW (typ.)

Flow-Through or Pipelined output mode on either port via
the

FT/PIPE pin

Counter enable and reset features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
 4ns setup to clock and 1ns hold on all control, data,

and address inputs

Data input, address, and control registers
Fast 9ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
15ns cycle time, 66MHz operation in the Pipelined

output mode

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (40°C to +85°C) is available
for selected speeds

Available in 100-pin Thin Quad Flatpack (TQFP) package

HIGH-SPEED 64K x 8
SYNCHRONOUS
DUAL-PORT STATIC RAM

PRELIMINARY

IDT709089S/L

0/1

/PIPE

I/O

Control

MEMORY

ARRAY

Counter/

Address

Reg.

I/O

Control

3242 drw 01

15R

CLK

ADS

CNTEN

CNTRST

CLK

ADS

15L

CNTEN

CNTRST

Counter/

Address

Reg.

I/O

- I/O

I/O

- I/O

0/1

/PIPE

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT709089 is a high-speed 64K x 8 bit synchronous Dual-Port

RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.

Pin Configuration

(1,2,3)

NOTES:
1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.

With an input data register, the IDT709089 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by

and CE

permits

the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT's CMOS high-performance technology,
these devices typically operate on only 950mW of power.

Index

75
74

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT709089PF

PN100-1

(4)

100-PIN TQFP

TOP VIEW

(5)

GND

/PIPE

CNTRST

GND

15R

12R

13R

11R

10R

14R

3242 drw 02

/PIPE

CNTRST

15L

14L

13L

12L

11L

10L

I
/
O

C
N
T
E
N

A
D
S

C
N
T
E
N

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

and

OE = V

; CE

and R/

W = V

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.

ADS is independent of all other signals including CE

and CE

5. The address counter advances if

CNTEN = V

on the rising edge of CLK, regardless of all other signals including

and CE

Truth Table IIAddress Counter Control

(1,2)

Truth Table I

Read/Write and Enable Control

(1,2,3)

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST = X.

OE is an asynchronous input signal.

CLK

I/O

0-7

Mode

High-Z

Deselected

High-Z

Deselected

Write

OUT

Read

High-Z

Outputs Disabled

3242 tbl 02

Address

Previous

Address

CLK

ADS

CNTEN

CNTRST

I/O

(3)

Mode

I/O

(0)

Counter Reset to Address 0

(4)

I/O

(n)

External Address Utilized

I/O

(n)

External Address Blocked--Counter Disabled

(5)

I/O

(n+1)

Counter Enable--Internal Address Generation

3242 tbl 03

Pin Names

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

- A

15L

- A

15R

Address

I/O

- I/O

I/O

- I/O

Data Input/Output

CLK

Clock

ADS

Address Strobe

CNTEN

Counter Enable

CNTRST

Counter Reset

/PIPE

Flow-Through/Pipeline

Power

GND

Ground

3242 tbl 01

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended DC Operating

Conditions

Recommended Operating

Temperature and Supply Voltage

(1,2)

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 10%.

Absolute Maximum Ratings

(1)

NOTES:
1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output

switch from 0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

(1)

= +25°C, f = 1.0MH

)

NOTES:
1. This is the parameter T

2. Industrial temperature: for specific speeds, packages and powers contact

your sales office.

NOTES:
1. V

TERM

must not exceed V

+ 10%.

2. V

> -1.5V for pulse width less than 10ns.

Grade

Ambient

Temperature

GND

Vcc

Commercial

C to +70

5.0V

10%

Industrial

-40

C to +85

5.0V

10%

3242 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Ground

Input High Voltage

2.2

____

6.0

(1)

Input Low Voltage

-0.5

(2)

____

0.8

3242 tbl 05

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage
with Respect
to GND

-0.5 to +7.0

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-55 to +125

OUT

DC Output
Current

3242 tbl 06

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

3242 tbl 07

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I

CC DC

(f=0)

= 150mA (Typ).

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

< 0.2V

"X" represents "L" for left port or "R" for right port.

6. 'X' in part numbers indicate power (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(6,7)

= 5V ± 10%)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 5.0V ± 10%)

NOTE:
1.

At Vcc < 2.0V input leakages are undefined.

Symbol

Parameter

Test Conditions

709089S/L

Unit

Min.

Max.

Input Leakage Current

(1)

= 5.5V, V

= 0V to V

___

µ A

Output Leakage Current

= V

or CE

= V

, V

OUT

= 0V to V

___

µ A

Output Low Voltage

= +4mA

___

0.4

Output High Voltage

= -4mA

2.4

___

3242 tbl 08

709089X9

Com'l Only

709089X12

Com'l Only

709089X15

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dynamic Operating
Current
(Both Ports Active)

and

= V

Outputs Open

f = f

MAX

(1)

COM'L

S
L

210
210

390
350

200
200

345
305

190
190

325
285

IND

S
L

____

SB1

Standby Current
(Both Ports - TTL
Level Inputs)

= V

f = f

MAX

(1)

COM'L

S
L

50
50

135

115

50
50

100

50
50

110

IND

S
L

____

SB2

Standby Current
(One Port - TTL
Level Inputs)

"A"

= V

and

"B"

= V

(3)

Active Port Outputs

Open,

f=f

MAX

(1)

COM'L

S
L

140
140

270
240

130
130

230
200

120
120

220

190

IND

S
L

____

SB3

Full Standby Current
(Both Ports -
CMOS Level Inputs)

Both Ports

and

> V

- 0.2V

> V

- 0.2V or

< 0.2V, f = 0

(2)

COM'L

S
L

1.0
0.2

IND

S
L

____

SB4

Full Standby Current
(One Port -
CMOS Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

> V

- 0.2V or

< 0.2V, Active Port

Outputs Open, f = f

MAX

(1)

COM'L

S
L

130
130

245
225

120
120

205
185

110
110

195
175

IND

S
L

____

3242 tbl 09

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For t

CKLZ

, t

CKHZ

, t

OLZ

, and t

OHZ

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

Figures 1,2 and 3

3242 tbl 10

3242 drw 05

893

30pF

347

DATA

OUT

893

5pF*

347

DATA

OUT

3242 drw 04

20 40

100

60 80

120 140 160 180 200

tCD

(Typical, ns)

Capacitance (pF)

3242 drw 06

-1

-10 pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device

characterization, but is not production tested.

2. The Pipelined output parameters (t

CYC2

, t

CD2

) apply to either or both left and right ports when

FT/PIPE = V

. Flow-through parameters (t

CYC1

, t

CD1

) apply when

FT/PIPE = V

for that port.

3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (

OE) and FT/PIPE. FT/PIPE should be treated as a DC

signal, i.e. steady state during operation.

4. 'X' in part number indicates power rating (S or L).
5. Industrial temperature: for specific speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)

(3,4,5)

= 5V ± 10%, T

= 0°C to +70°C)

709089X9

Com'l Only

709089X12

Com'l Only

709089X15

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC1

Clock Cycle Time (Flow-Through)

(2)

____

CYC2

Clock Cycle Time (Pipelined)

(2)

____

CH1

Clock High Time (Flow-Through)

(2)

____

CL1

Clock Low Time (Flow-Through)

(2)

____

CH2

Clock High Time (Pipelined)

(2)

____

CL2

Clock Low Time (Pipelined)

(2)

____

Clock Rise Time

____

Clock Fall Time

____

Address Setup Time

____

Address Hold Time

____

Chip Enable Setup Time

____

Chip Enable Hold Time

____

Setup Time

____

Hold Time

____

Input Data Setup Time

____

Input Data Hold Time

____

SAD

ADS

Setup Time

____

HAD

ADS

Hold Time

____

SCN

CNTEN

Setup Time

____

HCN

CNTEN

Hold Time

____

SRST

CNTRST

Setup Time

____

HRST

CNTRST

Hold Time

____

Output Enable to Data Valid

____

OLZ

Output Enable to Output Low-Z

(1)

____

OHZ

Output Enable to Output High-Z

(1)

CD1

Clock to Data Valid (Flow-Through)

(2)

____

CD2

Clock to Data Valid (Pipelined)

(2)

____

Data Output Hold After Clock High

____

CKHZ

Clock High to Output High-Z

(1)

CKLZ

Clock High to Output Low-Z

(1)

____

Port-to-Port Delay

CWDD

Write Port Clock High to Read Data Delay

____

CCS

Clock-to-Clock Setup Time

____

3242 tbl 11

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for

Flow-Through Output (FT/PIPE

"X"

= V

)

(3,6)

Timing Waveform of Read Cycle for Pipelined Output

(FT/PIPE

"X"

= V

)

(3,6)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

ADS = V

CNTEN and CNTRST = V

4. The output is disabled (High-Impedance state) by

= V

or CE

= V

following the next rising edge of clock. Refer to Truth Table 1.

5. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use

only.

6. "

" denotes Left or Right port. The diagram is with respect to that port.

An + 1

An + 2

An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

CKHZ

3242 drw 07

(1)

(2)

(4)

(5)

An + 1

An + 2

An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(4)

DATA

OUT

CD2

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

3242 drw 08

(1)

(2)

(5)

(1 Latency)

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of a Bank Select Pipelined Read

(1,2)

0(B1)

ADDRESS

(B1)

CLK

3242 drw 09

DATA

OUT(B1)

CH2

CL2

CYC2

(3)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

(3)

CKHZ

(3)

CKLZ

(3)

CD2

Timing Waveform of a Bank Select Flow-Through Read

(6,7)

0(B1)

ADDRESS

(B1)

CLK

3242 drw 09a

CD1

CKLZ

CKHZ

(1)

DATA

OUT(B1)

CH1

CL1

CYC1

(1)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD1

CKHZ

CD1

CKLZ

(1)

CKHZ

(1)

CKLZ

(1)

CD1

CKLZ

(1)

CKHZ

(1)

NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one 709089 for this waveform, and are setup for depth expansion in this example.

ADDRESS

(B1)

= ADDRESS

(B2)

in this situation.

OE and ADS = V

; CE

1(B1)

, CE

1(B2)

, R/

W, CNTEN, and CNTRST = V

3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4.

and

ADS = V

; CE

CNTEN, and CNTRST = V

OE = V

for the Right Port, which is being read from.

OE = V

for the Left Port, which is being written to.

6. If t

CCS

< maximum specified, then data from right port READ is not valid until the maximum specified for t

CWDD

If t

CCS

> maximum specified, then data from right port READ is not valid until t

CCS

+ t

CD1

. t

CWDD

does not apply in this case.

7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A".

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform with Port-to-Port Flow-Through Read

(1,2,3,5)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2.

and

ADS = V

; CE

CNTEN, and CNTRST = V

OE = V

for the Right Port, which is being read from.

OE = V

for the Left Port, which is being written to.

4. If t

CCS

< maximum specified, then data from right port READ is not valid until the maximum specified for t

CWDD

If t

CCS

> maximum specified, then data from right port READ is not valid until t

CCS

+ t

CD1

. t

CWDD

does not apply in this case.

5. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A".

DATA

IN"A"

CLK

"B"

ADDRESS

"A"

CLK

"A"

ADDRESS

"B"

MATCH

VALID

CWDD

CD1

DATA

OUT"B"

3242 drw 10

VALID

CD1

CCS

(4)

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = V

)

(3)

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)

(3)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3.

and

ADS = V

; CE

CNTEN, and CNTRST = V

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

3242 drw 11

Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ

NOP

READ

(4)

(2)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

DATA

Dn + 3

Dn + 2

CLK

3242 drw 12

DATA

OUT

Qn + 4

CH2

CL2

CYC2

CKLZ

(1)

CD2

OHZ

(1)

CD2

READ

WRITE

READ

(4)

(2)

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform Flow-Through Read-to-Write-to-Read (OE = V

)

(3)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)

(3)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3.

and

ADS = V

; CE

CNTEN, and CNTRST = V

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

3242 drw 13

DATA

OUT

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ

NOP

READ

CKLZ

(4)

(2)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

(4)

DATA

Dn + 2

CLK

3242 drw 14

DATA

OUT

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ

WRITE

READ

CKLZ

(2)

Dn + 3

OHZ

(1)

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read with Address Counter Advance

(1)

Timing Waveform of Flow-Through Read with Address Counter Advance

(1)

NOTES:
1.

and

OE = V

; CE

, R/

W, and CNTRST = V

2. If there is no address change via

ADS = V

(loading a new address) or

CNTEN = V

(advancing the address), i.e.

ADS = V

and

CNTEN = V

, then the data output

remains constant for subsequent clocks.

ADDRESS

CLK

DATA

OUT

Qx - 1

(2)

Qn + 2

(2)

Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

3242 drw 15

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1

ADDRESS

CLK

DATA

OUT

(2)

Qn + 1

Qn + 2

Qn + 3

(2)

Qn + 4

ADS

CNTEN

CYC1

CH1

CL1

3242 drw 16

SAD

HAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

CD1

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-Through or Pipelined Outputs)

(1)

Timing Waveform of Counter Reset (Pipelined Outputs)

(2)

NOTES:
1.

and R/

W = V

; CE

and

CNTRST = V

2. CE

= V

; CE

= V

3. The "Internal Address" is equal to the "External Address" when

ADS = V

and equals the counter output when

ADS = V

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset. ADDR

will be accessed. Extra cycles are shown here

simply for clarification.

CNTEN = V

advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1'Address is written

to during this cycle.

ADDRESS

CLK

DATA

Dn + 1

Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

3242 drw 17

INTERNAL

(3)

ADDRESS

(7)

An + 1

An + 2

An + 3

An + 4

Dn + 3

Dn + 4

SAD

HAD

WRITE

COUNTER HOLD

WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

ADDRESS

CH2

CL2

CYC2

CLK

DATA

CNTRST

3242 drw 18

INTERNAL

(3)

ADDRESS

ADS

CNTEN

SRST

HRST

COUNTER

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

An + 1

An + 2

READ

ADDRESS n+1

DATA

OUT

An + 1

(4)

(5)

(6)

SAD

HAD

SCN

HCN

(6)

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

3242 drw 19

IDT709089

Control Inputs

CNTRST

CLK

ADS

CNTEN

Functional Description

The IDT709089 provides a true synchronous Dual-Port Static

RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.

A HIGH on

or a LOW on CE

for one clock cycle will power

down the internal circuitry to reduce static power consumption.
Multiple chip enables allow easier banking of multiple IDT709089's for
depth expansion configurations. When the Pipelined output mode is
enabled, two cycles are required with

LOW and CE

HIGH to re-

activate the outputs.

Depth and Width Expansion

The IDT709089 features dual chip enables (refer to Truth Table I)

in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.

The 709089 can also be used in applications requiring expanded

width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 16-bit or
wider applications.

Figure 4. Depth and Width Expansion with IDT709089

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTE:
1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

Power

Speed

Package

Process/

Temperature

Range

Blank

(1)

Commercial (0

C to +70

Industrial (-40

C to +85

100-pin TQFP (PN100-1)

XXXXX

Device

Type

IDT

Speed in nanoseconds

3242 drw 20A

Standard Power

Low Power

709089 512K (64K x 8-Bit) Synchronous Dual-Port RAM

Commercial Only

Ordering Information for Flow-through Devices

Old Flow-through Part

New Combined Part

70908S/L20

709089S/L9

70908S/L25

709089S/L12

70908S/L30

709089S/L15

3242 tbl 12

Preliminary Datasheet:

"PRELIMINARY' datasheets contain descriptions for products that are in early release.

6.42

IDT709089S/L Preliminary
High-Speed 64K x 8 Synchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Datasheet Document History

1/12/99:

Initiated datasheet document history

Converted to new format
Cosmetic and typographical corrections
Added additional notes to pin configurations
Page 15 Added Depth and Width Expansion note

6/7/99:

Changed drawing format
Page 4 Deleted note 6 for Table II

11/10/99:

Replaced IDT logo

12/22/99:

Page 1 Removed "Separate upper-byte..." line

1/12/00:

Combined Pipelined 709089 family and Flow-through 70908 family offerings into one data sheet

Changed ±200mV in waveform notes to 0mV
Added corrresponding part chart with ordering information

2/18/00:

Pages 8 and 9 Changed ±220mV waveform notes to 0mV

Page 9 Changed "Operation" in heading to "Pipelined Output", fixed drawing 08
Removed PGA pin

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for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-6116

831-754-4613

Santa Clara, CA 95054

fax: 408-492-8674

DualPortHelp@idt.com

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