APRIL 2000

DSC-3493/8

Functional Block Diagram

Features:

True Dual-Ported memory cells which allow simultaneous
access of the same memory location

High-speed clock to data access
 Commercial: 9/12/15ns (max.)

Low-power operation

 IDT709269S

Active: 950mW (typ.)
Standby: 5mW (typ.)

 IDT709269L

Active: 950mW (typ.)
Standby: 1mW (typ.)

Flow-through or Pipelined output mode on either port via
the

FT/PIPE pin

Counter enable and reset features

Dual chip enables allow for depth expansion without
additional logic

HIGH-SPEED 16K x 16
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM

PRELIMINARY

IDT709269S/L

Full synchronous operation on both ports
 4ns setup to clock and 1ns hold on all control, data, and

address inputs

Data input, address, and control registers
Fast 9ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
15ns cycle time, 66MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (40°C to +85°C) is
available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP) package

0a 1a

0b 1b

0/1

/PIPE

I/O

Control

MEMORY

ARRAY

Counter/

Address

Reg.

I/O

Control

3493 drw 01

13R

CLK

ADS

CNTEN

CNTRST

I/O

-I/O

15L

I/O

-I/O

I/O

-I/O

15R

I/O

-I/O

CLK

ADS

13L

CNTEN

CNTRST

Counter/

Address

Reg.

/PIPE

0/1

1a 0a

1b 0b

0/1

6.42

IDT709269S/L Preliminary
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Index

75
74
73

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT709269PF

PN100-1

(4)

100-PIN TQFP

TOP VIEW

(5)

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

GND

3493 drw 02

I/O

15L

CNTRST

Vcc

13L

12L

11L

10L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

GND

I
/
O

/PIPE

CNTRST

GND

12R

13R

11R

10R

I
/
O

I
L

I
/
O

/PIPE

Description:

The IDT709269 is a high-speed 16K x 16 bit synchronous pipelined

Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers
on control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.

Pin Configuration

(1,2,3)

NOTES:
1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.

With an input data register, the IDT709269 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by

and CE

permits

the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT's CMOS high-performance technology,
these devices typically operate on only 950mW of power.

6.42

IDT709269S/L Preliminary
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST = X.

OE is an asynchronous input signal.

Truth Table IRead/Write and Enable Control

(1,2,3)

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

- A

13L

- A

13R

Address

I/O

- I/O

15L

I/O

- I/O

15R

Data Input/Output

CLK

Clock

Upper Byte Select

Lower Byte Select

ADS

Address Strobe

CNTEN

Counter Enable

CNTRST

Counter Reset

FT/PIPE

Flow-Through/Pipeline

Power

GND

Ground

3493 tbl 01

CLK

Upper

Byte

I/O

8-15

Lower B

yte

I/O

0-7

Mode

High-Z

Deselected--Power Down

High-Z

Deselected--Power Down

High-Z

Both Bytes Deselected

High-Z

Write to Upper Byte Only

High-Z

Write to Lower Byte Only

Write to Both Bytes

OUT

High-Z

Read Upper Byte Only

High-Z

OUT

Read Lower Byte Only

OUT

Read Both Bytes

High-Z

Outputs Disabled

3493 tbl 02

6.42

IDT709269S/L Preliminary
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

(1,2)

Recommended DC Operating

Conditions

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 10%.

Absolute Maximum Ratings

(1)

OTES:

1. These parameters are determined by device characterization, but are not produc-

tion tested.

2. 3dV references the interpolated capacitance when the input and output switch from

0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

= +25°C, f = 1.0MH

)

NOTES:
1. V

TERM

must not exceed V

+ 10%.

2. V

> -1.5V for pulse width less than 10ns.

NOTES:
1. This is the parameter T

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

Grade

Ambient

Temperature

GND

Vcc

Commercial

C to +70

5.0V

10%

Industrial

-40

C to +85

5.0V

10%

3493 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Ground

Input High Voltage

2.2

____

6.0

(1)

Input Low Voltage

-0.5

(2)

____

0.8

3493 tbl 05

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage
with Respect
to GND

-0.5 to +7.0

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-55 to +125

OUT

DC Output
Current

3493 tbl 06

Symbol

Parameter

(1)

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

3493 tbl 07

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

, and

= V

; CE

and R/

= V

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.

ADS

is independent of all other signals including

, CE

and

5. The address counter advances if

CNTEN

= V

on the rising edge of CLK, regardless of all other signals including

, CE

and

TRUTH TABLE IIAddress Counter Control

(1,2)

Address

Previous

Address

CLK

ADS

CNTEN

CNTRST

I/O

(3)

Mode

I/O

(0)

Counter Reset to Address 0

(4)

I/O

(n)

External Address Utilized

I/O

(n)

External Address Blocked--Counter Disabled

(5)

I/O

(n+1)

Counter Enable--Internal Address Generation

3493 tbl 03

6.42

IDT709269S/L Preliminary
High-Speed 16K x 16 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V

= 5V, T

= 25°C for Typ, and are not production tested. I

CC DC

(f=0)

= 150mA (Typ).

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

< 0.2V

"X" represents "L" for left port or "R" for right port.

6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(6,7)

= 5V ± 10%)

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range

= 5.0V ± 10%)

OTE:

At V

< 2.0V input leakages are undefined.

Symbol

Parameter

Test Conditions

709269S/L

Unit

Min.

Max.

Input Leakage Current

(1)

= 5.5V, V

= 0V to V

___

µ A

Output Leakage Current

= V

or CE

= V

, V

OUT

= 0V to V

___

µ A

Output Low Voltage

= +4mA

___

0.4

Output High Voltage

= -4mA

2.4

___

3493 tbl 08

709269X9

Com'l Only

709269X12

Com'l Only

709269X15

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dynamic Operating
Current
(Both Ports Active)

and

= V

Outputs Open

f = f

MAX

(1)

COM'L

S
L

210
210

390
350

200
200

345
305

190
190

325
285

IND

S
L

____

SB1

Standby Current
(Both Ports - TTL
Level Inputs)

= V

f = f

MAX

(1)

COM'L

S
L

50
50

135

115

50
50

110

50
50

110

IND

S
L

____

SB2

Standby Current
(One Port - TTL
Level Inputs)

"A"

= V

and

"B"

= V

(3)

Active Port Outputs

Open,

f=f

MAX

(3)

COM'L

S
L

140
140

270
240

130
130

230
200

120
120

220
190

IND

S
L

____

SB3

Full Standby Current
(Both Ports -
CMOS Level Inputs)

Both Ports

and

> V

- 0.2V

> V

- 0.2V or

< 0.2V, f = 0

(2)

COM'L

S
L

1.0
0.2

IND

S
L

____

SB4

Full Standby Current
(One Port -
CMOS Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

> V

- 0.2V or

< 0.2V, Active Port

Outputs Open, f = f

MAX

(1)

COM'L

S
L

130
130

245
225

120
120

205
185

110
110

195
175

IND

S
L

____

3493 tbl 09

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