JULY 2002

DSC-5633/1

.unctional Block Diagram

.eatures

True Dual-Ported memory cells which allow simultaneous
access of the same memory location

High-speed clock to data access
Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)

Low-power operation
 IDT709359/49L

Active: 925mW (typ.)
Standby: 2.5mW (typ.)

Flow-Through or Pipelined output mode on either Port via
the

FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
 3.5ns setup to clock and 0ns hold on all control, data, and

address inputs

Data input, address, and control registers
Fast 6.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
10ns cycle time, 100MHz operation in Pipelined output mode

Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility

TTL- compatible, single 5V (±10%) power supply

Industrial temperature range (40°C to +85°C) is
available for 83 MHz

Available in a 100-pin Thin Quad Flatpack (TQFP) package
and a 100-pin fine pitch Ball Grid Array (fpBGA)

HIGH-SPEED 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM

IDT709359/49L

0a 1a

0b 1b

0/1

I/O

Control

0/1

/PIPE

MEMORY

ARRAY

Counter/

Address

Reg.

5633 drw 01

12R

(1)

CLK

ADS

CNTEN

CNTRST

I/O

-I/O

17L

I/O

-I/O

I/O

-I/O

17R

I/O

-I/O

CLK

ADS

12L

(1)

CNTEN

CNTRST

Counter/

Address

Reg.

0/1

1b 0b

1a 0a

0/1

b a

I/O

Control

/PIPE

PRELIMINARY

NOTE:
1. A

is a NC for IDT709349.

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Index

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

100-Pin TQFP

Top View

(6)

10L

11L

12L

(1)

NC
NC
NC

CNTRST

/PIPE

I/O

16L

I/O

17L

GND

I/O

15L

I/O

14L

I/O

13L

I/O

12L

I/O

11L

I/O

10L

5633 drw 02

10R

11R

12R

(1)

NC
NC
NC

CNTRST

GND

/PIPE

I/O

14R

I/O

13R

I/O

12R

I/O

11R

I/O

17R

GND
I/O

16R

I/O

15R

I
/
O

709359/49PF

PN100-1

(5)

06/28/02

Pin Configurations

(1,2,3,4)

NOTES:
1. A

is a NC for IDT709349.

2. All V

pins must be connected to power supply.

3. All GND pins must be connected to ground.
4. Package body is approximately 14mm x 14mm x 1.4mm
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

Description

The IDT709359/49 is a high-speed 8/4K x 18 bit synchronous Dual-

Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times.

With an input data register, the IDT709359/49 has been optimized for

applications having unidirectional or bidirectional data flow in bursts.
An automatic power down feature, controlled by

and CE

permits

the on-chip circuitry of each port to enter a very low standby power
mode. Fabricated using IDT's CMOS high-performance technology,
these devices typically operate on only 925mW of power.

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

C10

I/O

11R

I/O

10R

I/O

D10

I/O

15R

I/O

12R

I/O

13R

A10

I/O

17R

I/O

14R

PL/

GND

I/O

16R

GND

CNTRST

10R

CLK

11R

GND

ADS

CNTEN

GND

CLK

CNTEN

11L

10L

GND

B10

I/O

ADS

GND

I/O

E10

GND

I/O

F10

I/O

GND

I/O

13L

I/O

GND

G10

I/O

CNTRST

I/O

15L

I/O

H10

I/O

PL/

I/O

12L

I/O

10L

GND

J10

I/O

16L

I/O

14L

I/O

11L

K10

I/O

17L

5633 drw 03

06/28/02

(1)

12R

12L

NOTES:
1. A

is a NC for IDT709349.

2. All V

pins must be connected to power supply.

Pin Configurations

(con't.)

(1,2,3,4)

709359/49BF

BF100

(5)

100-Pin fpBGA

Top View

(6)

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST = X.

OE is an asynchronous input signa

LB and UB are single buffered regardless of state of FT/PIPE.

CEo and CE

are single buffered when

FT/PIPE = V

CEo and CE

are double buffered when

FT/PIPE = V

, i.e. the signals take two cycles to deselect.

Truth Table IRead/Write and Enable Control

(1,2,3)

CLK

(5)

(4)

Upper Byte

I/O

9-17

Lower B

yte

I/O

0-8

Mode

High-Z

Deselected--Power Down

High-Z

Deselected--Power Down

High-Z

Both Bytes Deselected

DATA

High-Z

Write to Upper Byte Only

High-Z

DATA

Write to Lower Byte Only

DATA

Write to Both Bytes

DATA

OUT

High-Z

Read Upper Byte Only

High-Z

DATA

OUT

Read Lower Byte Only

DATA

OUT

DATA

OUT

Read Both Bytes

High-Z

Outputs Disabled

5633 tbl 02

Pin Names

Left Port

Right Port

Names

Chip Enables

(3)

R/W

Read/Write Enable

Output Enable

- A

12L

(1)

- A

12R

(1)

Address

I/O

- I/O

17L

I/O

- I/O

17R

Data Input/Output

CLK

Clock

Upper Byte Select

(2)

Lower Byte Select

(2)

ADS

Address Strobe

CNTEN

Counter Enable

CNTRST

Counter Reset

FT/PIPE

Flow-Through/Pipeline

Power (5V)

GND

Ground (0V)

5633 tbl 01

NOTES:
1. A

is a NC for IDT709349.

LB and UB are single buffered regardless of state of FT/PIPE.

CEo and CE

are single buffered when

FT/PIPE = V

CEo and CE

are double buffered when

FT/PIPE = V

i.e. the signals take two cycles to deselect.

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Recommended Operating

Temperature and Supply Voltage

(1)

Recommended DC Operating

Conditions

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 10% for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 10%.

Absolute Maximum Ratings

(1)

NOTES:
1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch from

0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

(1)

= +25°C, f = 1.0MH

)

NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

2. This is the parameter T

. This is the "instant on" case temperature.

NOTES:
1. V

TERM

must not exceed V

+ 10%.

2. V

> -1.5V for pulse width less than 10ns.

Grade

Ambient

Temperature

(1)

GND

Vcc

Commercial

C to +70

5.0V

10%

Industrial

-40

C to +85

5.0V

10%

5633 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

4.5

5.0

5.5

GND

Ground

Input High Voltage

2.2

____

6.0

(1)

Input Low Voltage

-0.5

(2)

____

0.8

5633 tbl 05

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

5633 tbl 07

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage
with Respect
to GND

-0.5 to +7.0

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-65 to +150

OUT

DC Output
Current

5633 tbl 06

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

LB, UB, and OE = V

; CE

and R/

W = V

3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.

ADS and CNTRST are independent of all other signals including CE

, CE

UB and LB.

5. The address counter advances if

CNTEN = V

on the rising edge of CLK, regardless of all other signals including

, CE

UB and LB.

Truth Table IIAddress Counter Control

(1,2)

External

Address

Previous

Internal

Address

Internal

Address

Used

CLK

ADS

CNTEN

CNTRST

I/O

(3)

MODE

(4)

I/O

(n)

External Address Used

An + 1

(5)

I/O

(n+1)

Counter Enabled--Internal Address generation

An + 1

I/O

(n+1)

E xternal Addre ss Blocked--Counter disab led (An + 1 reused)

(4)

I/O

(0)

Counter Reset to Address 0

5633 tbl 03

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input levels of

GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 5V, TA = 25°C for Typ, and are not production tested. I

CC DC

(f=0)

= 150mA (Typ).

5. CE

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

< 0.2V

"X" represents "L" for left port or "R" for right port.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(3)

= 5V ± 10%)

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range

= 5.0V ± 10%)

NOTE:
1.

At Vcc < 2.0V input leakages are undefined.

Symbol

Parameter

Test Conditions

709359/49L

Unit

Min.

Max.

Input Leakage Current

(1)

= 5.5V, V

= 0V to V

___

µ A

Output Leakage Current

= V

or CE

= V

, V

OUT

= 0V to V

___

µ A

Output Low Voltage

= +4mA

___

0.4

Output High Voltage

= -4mA

2.4

___

5633 tbl 08

709359/49L6

Com 'l Only

709359/49L7
Com 'l & Ind

709359/49L9

Com 'l Only

Sym bol

Param eter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dy nam ic Op e rating
Curre nt
(Bo th P o rts A ctiv e )

and

= V

Outp uts Disab le d

f = f

MAX

(1)

COM 'L

230

430

210

400

185

360

IND

____

210

440

____

SB1

S tand b y Curre nt
(Bo th P o rts - TTL
Le ve l Inp uts )

= V

f = f

MAX

(1)

COM 'L

115

105

IND

____

120

____

SB2

S tand b y Curre nt
(One Po rt - TTL
Le ve l Inp uts )

"A"

= V

and

"B"

= V

(3)

A ctive P o rt Outp uts

Disab le d , f= f

MAX

(1)

COM 'L

150

235

135

220

120

205

IND

____

_____

135

235

____

SB3

Full Stand b y Curre nt
(Bo th P o rts -
CMOS Le ve l Inp uts)

Bo th Po rts CE

and

> V

- 0.2V

> V

- 0.2V o r

< 0.2V, f = 0

(2)

COM 'L

0.5

3.0

0.5

3.0

0.5

3.0

IND

____

_____

0.5

3.0

____

SB4

Full Stand b y Curre nt
(One Po rt -
CMOS Le ve l Inp uts)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

> V

- 0.2V o r

< 0.2V, A ctive P o rt

Outp u ts Disab le d , f = f

MAX

(1)

COM 'L

160

210

130

190

110

170

IND

____

_____

130

205

____

5633 tbl 09

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

AC Test Conditions

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For t

CKLZ

, t

CKHZ

, t

OLZ

, and t

OHZ

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

2ns Max.

1.5V

Figures 1, 2 and 3

5633 tbl 10

5633 drw 05

893

30pF

347

DATA

OUT

893

5pF*

347

DATA

OUT

5633 drw 04

20 40

100

60 80

120 140 160 180 200

tCD

(Typical, ns)

Capacitance (pF)

5633 drw 06

-1

- 10pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed by device characteriza-

tion, but is not production tested.

2. The Pipelined output parameters (t

CYC2

, t

CD2

) to either the Left or Right ports when

FT/PIPE = V

. Flow-Through parameters (t

CYC1

, t

CD1

) apply when

FT/PIPE = V

for

that port

3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (

OE), FT/PIPE

and

FT/PIPE

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)

(3)

= 5V ± 10%, TA = 0°C to +70°C)

709359/49L6

Com'l Only

709359/49L7
Com'l & Ind

709359/49L9

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC1

Clock Cycle Time (Flow-Through)

(2)

____

CYC2

Clock Cycle Time (Pipelined)

(2)

____

CH1

Clock High Time (Flow-Through)

(2)

6.5

____

7.5

____

CL1

Clock Low Time (Flow-Through)

(2)

6.5

____

7.5

____

CH2

Clock High Time (Pipelined)

(2)

____

CL2

Clock Low Time (Pipelined)

(2)

____

Clock Rise Time

____

Clock Fall Time

____

Address Setup Time

3.5

____

Address Hold Time

____

Chip Enable Setup Time

3.5

____

Chip Enable Hold Time

____

Byte Enable Setup Time

3.5

____

Byte Enable Hold Time

____

W Setup Time

3.5

____

W Hold Time

____

Input Data Setup Time

3.5

____

Input Data Hold Time

____

SAD

ADS Setup Time

3.5

____

HAD

ADS Hold Time

____

SCN

CNTEN Setup Time

3.5

____

HCN

CNTEN Hold Time

____

SRST

CNTRST Setup Time

3.5

____

HRST

CNTRST Hold Time

____

Output Enable to Data Valid

____

6.5

____

7.5

____

OLZ

Output Enable to Output Low-Z

(1)

____

OHZ

Output Enable to Output High-Z

(1)

CD1

Clock to Data Valid (Flow-Through)

(2)

____

CD2

Clock to Data Valid (Pipelined)

(2)

____

6.5

____

7.5

____

Data Output Hold After Clock High

____

CKHZ

Clock High to Output High-Z

(1)

CKLZ

Clock High to Output Low-Z

(1)

____

Port-to-Port Delay

CWDD

Write Port Clock High to Read Data Delay

____

CCS

Clock-to-Clock Setup Time

____

5633 tbl 11

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Timing Waveform of Read Cycle for

.low-Through Output (FT/PIPE

"X"

= V

)

(3,7)

Timing Waveform of Read Cycle for Pipelined Operation

(FT/PIPE

"X"

= V

)

(3,7)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

ADS = V

CNTEN and CNTRST = V

4. The output is disabled (High-Impedance state) by

= V

, CE

= V

, following the next rising edge of the clock. Refer to Truth Table 1.

5. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

6. If

UB or LB was HIGH, then the Upper Byte and/or Lower Byte of DATA

OUT

for Qn + 2 would be disabled (High-Impedance state).

7. "X" here denotes Left or Right port. The diagram is with respect to that port.

An + 1

An + 2

An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

CKHZ

5633 drw 07

(1)

(2)

(5)

An + 1

An + 2

An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(4)

DATA

OUT

CD2

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

5633 drw 08

(1)

(2)

(5)

(1 Latency)

(6)

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Timing Waveform of Write with Port-to-Port .low-Through Read

(4,5,7)

NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT709359/49 for this waveform, and are setup for depth expansion in this

example. ADDRESS

(B1)

= ADDRESS

(B2)

in this situation.

UB, LB, OE, and ADS = V

; CE

1(B1)

, CE

1(B2)

, R/

W, CNTEN, and CNTRST = V

3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4.

UB, LB, and ADS = V

; CE

CNTEN, and CNTRST = V

OE = V

for the Right Port, which is being read from.

OE = V

for the Left Port, which is being written to.

6. If t

CCS

< maximum specified, then data from right port READ is not valid until the maximum specified for t

CWDD

If t

CCS

> maximum specified, then data from right port READ is not valid until t

CCS

+ t

CD1

. t

CWDD

does not apply in this case.

7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".

Timing Waveform of a Bank Select Pipelined Read

(1,2)

0(B1)

ADDRESS

(B1)

CLK

5633 drw 09

DATA

OUT(B1)

CH2

CL2

CYC2

(3)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

(3)

CKHZ

(3)

CKLZ

(3)

CD2

DATA

IN "A"

CLK

"B"

ADDRESS

"A"

CLK

"A"

ADDRESS

"B"

MATCH

VALID

CWDD

CD1

DATA

OUT "B"

5633 drw 10

VALID

CD1

CCS

(6)

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = V

)

(3)

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)

(3)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3.

UB, LB, and ADS = V

; CE

CNTEN, and CNTRST = V

. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

5633 drw 11

Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ

NOP

READ

(4)

(2)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

DATA

Dn + 3

Dn + 2

CLK

5633 drw 12

DATA

OUT

Qn + 4

CH2

CL2

CYC2

CKLZ

(1)

CD2

OHZ

(1)

CD2

READ

WRITE

READ

(4)

(2)

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Timing Waveform of .low-Through Read-to-Write-to-Read (OE = V

)

(3)

Timing Waveform of .low-Through Read-to-Write-to-Read (OE Controlled)

(3)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance is determined by the previous cycle control signals.
3.

UB, LB, and ADS = V

; CE

CNTEN, and CNTRST = V

. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

5633 drw 13

DATA

OUT

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ

NOP

READ

CKLZ

(4)

(2)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

(4)

DATA

Dn + 2

CLK

5633 drw 14

DATA

OUT

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ

WRITE

READ

CKLZ

(2)

Dn + 3

OHZ

(1)

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Timing Waveform of Pipelined Read with Address Counter Advance

(1)

Timing Waveform of .low-Through Read with Address Counter Advance

(1)

NOTES:
1.

OE, UB, and LB = V

; CE

, R/

W, and CNTRST = V

2. If there is no address change via

ADS = V

(loading a new address) or

CNTEN = V

(advancing the address), i.e.

ADS = V

and

CNTEN = V

, then the data output

remains constant for subsequent clocks.

ADDRESS

CLK

DATA

OUT

Qx - 1

(2)

Qn + 2

(2)

Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

5633 drw 15

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1

ADDRESS

CLK

DATA

OUT

(2)

Qn + 1

Qn + 2

Qn + 3

(2)

Qn + 4

ADS

CNTEN

CYC1

CH1

CL1

5633 drw 16

SAD

HAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

CD1

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Timing Waveform of Write with Address Counter Advance

(.low-Through or Pipelined Outputs)

(1)

Timing Waveform of Counter Reset (Pipelined Outputs)

(2)

NOTES:
1.

UB, LB, and R/W = V

; CE

and

CNTRST = V

2. CE

UB, LB = V

; CE

= V

3. The "Internal Address" is equal to the "External Address" when

ADS = V

and equals the counter output when

ADS = V

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle.
7.

CNTEN = V

advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1' Address is written

to during this cycle.

ADDRESS

CLK

DATA

Dn + 1

Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

5633 drw 17

INTERNAL

(3)

ADDRESS

(7)

An + 1

An + 2

An + 3

An + 4

Dn + 3

Dn + 4

SAD

HAD

WRITE

COUNTER HOLD

WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

ADDRESS

CH2

CL2

CYC2

CLK

DATA

CNTRST

5633 drw 18

INTERNAL

(3)

ADDRESS

ADS

CNTEN

SRST

HRST

COUNTER

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

An + 1

An + 2

READ

ADDRESS n+1

DATA

OUT

An + 1

(5)

(6)

(4)

(6)

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

5633 drw 19

IDT709359/49

12(1)

IDT709359/49

Control Inputs

CNTRST

CLK

ADS
CNTEN

A .unctional Description

The IDT709359/49 provides a true synchronous Dual-Port Static

RAM interface. Registered inputs provide minimal set-up and hold
times on address, data, and all critical control inputs. All internal
registers are clocked on the rising edge of the clock signal, however,
the self-timed internal write pulse is independent of the LOW to HIGH
transition of the clock signal.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory appli-
cations.

= V

or CE

= V

for one clock cycle will power down the

internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT709359/49's for depth
expansion configurations. When the Pipelined output mode is enabled, two
cycles are required with

= V

and CE

= V

to re-activate the outputs.

Depth and Width Expansion

The IDT709359/49 features dual chip enables (refer to Truth Table

I) in order to facilitate rapid and simple depth expansion with no require-
ments for external logic. Figure 4 illustrates how to control the various chip
enables in order to expand two devices in depth.

The IDT709359/49 can also be used in applications requiring ex-

panded width, as indicated in Figure 4. Since the banks are allocated at
the discretion of the user, the external controller can be set up to drive the
input signals for the various devices as required to allow for 36-bit
or wider applications.

Figure 4. Depth and Width Expansion with IDT709359/49

NOTE:
1. A

is for IDT709359, A

is for IDT709349.

6.42

IDT709359/49L
High-Speed 8/4K x 18 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Preliminary

Ordering Information

NOTE:
1. Contact your local sales office for industrial temp range for other speeds, packages and powers.

Power

Speed

Package

Process/

Temperature

Range

Blank

(1)

Commercial (0

C to +70

Industrial (-40

C to +85

100-pin TQFP (PN100-1)

100-pin fpBGA (BF100)

XXXXX

Device

Type

IDT

Speed in nanoseconds

5633 drw 20

Low Power

709359
709349

144K (8K x 18-Bit) Synchronous Dual-Port RAM

72K (4K x 18-Bit) Synchronous Dual-Port RAM

Commercial & Industrial

Commercial Only

Datasheet Document History

07/08/02:

Initial Public Release

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-611 6

831-754-4613

Santa Clara, CA 95054

fax: 408-492-8674

DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

Preliminary Datasheet:

Definition

"PRELIMINARY" datasheets contain descriptions for products that are in early release.

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