APRIL 2003

DSC-5670/1

Functional Block Diagram

On-chip port arbitration logic

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus
matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1 in
BGA-208 and BGA-256 packages

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 144-pin Thin Quad
Flatpack and 208-ball fine pitch Ball Grid Array

Industrial temperature range (40°C to +85°C) is available
for selected speeds

Features

True Dual-Port memory cells which allow simultaneous
access of the same memory location

High-speed access
Commercial: 10/12/15ns (max.)
Industrial: 12ns (max.)

Dual chip enables allow for depth expansion without
external logic

IDT70T633/1 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device

M/S = V

for BUSY output flag on Master,

M/S = V

for BUSY input on Slave

Busy and Interrupt Flags

Full hardware support of semaphore signaling between
ports on-chip

HIGH-SPEED 2.5V
512/256K x 18

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

PRELIMINARY

IDT70T633/1S

1. Address A

x is a NC for IDT70T631.

2. BUSY is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

BUSY

and INT are non-tri-state totem-pole outputs (push-pull).

4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, BUSYx, INTx, M/S

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

512/256K x 18

MEMORY

ARRAY

Address

Decoder

18R

(1)

Address
Decoder

Dout0-8_L
Dout9-17_L

Dout0-8_R

Dout9-17_R

B
E
0
L

B
E
1
L

B
E
1
R

B
E
0
R

I/O

- I/O

17L

I/O

- I/O

17R

Din_L

ADDR_L

Din_R

ADDR_R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

5670 drw 01

18L

(1)

CONTROL

LOGIC

(4)

JTAG

TCK

TRST

TMS

TDI

TDO

INT

L(3)

SEM

BUSY

L(2,3)

BUSY

R(2,3)

SEM

INT

R(3)

NOTES:

IDT70T633/1S Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70T633/1 is a high-speed 512/256K x 18 Asynchronous

Dual-Port Static RAM. The IDT70T633/1 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-
TER/SLAVE Dual-Port RAM for 36-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 36-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE

or CE

) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The 70T633/1 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (V

) remains at 2.5V.

IDT70T633/1S Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3)

NOTES:
1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. A

18X

is a NC for IDT70T631.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.

70T633/1BC

BC-256

(5,6)

256-Pin BGA

Top View

E16

I/O

D16

I/O

C16

I/O

B16

A16

A15

B15

C15

D15

E15

I/O

E14

D14

D13

C12

C14

OPT

B14

A14

A12

B12

C11

BUSY

D12

DDQR

D11

DDQR

C10

SEM

B11

A11

INT

DDQR

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

18L

(4)

16L

TDO

I/O

TDI

I/O

10R

I/O

10L

DDQL

I/O

11L

I/O

11R

DDQL

I/O

12L

DDQR

I/O

12R

DDQR

I/O

13L

I/O

14R

I/O

13R

DDQL

I/O

14L

DDQL

I/O

15L

I/O

15R

DDQR

I/O

16R

I/O

16L

DDQR

I/O

17R

I/O

17L

TMS

16R

TRST

18R

(4)

TCK

17R

13R

15R

P12

P10

SEM

T11

INT

P11

BUSY

R12

T12

P13

R13

T13

12R

14R

T14

R14

OPT

P14

P15

R15

T15

T16

R16

P16

I/O

N16

N15

I/O

N14

M16

M15

I/O

M14

I/O

L16

I/O

L15

L14

I/O

K16

I/O

K15

K14

J16

I/O

J15

I/O

J14

I/O

H16

I/O

H15

H14

G16

G15

G14

I/O

F16

I/O

F14

I/O

F15

R11

11R

11L

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5670 drw 02c

03/13/03

17L

DDQL

DDQR

IDT70T633/1S Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground.

4. A

18X

is a NC for IDT70T631.

5. Package body is approximately 20mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. Due to the restricted number of pins, JTAG is not supported in the DD-144 package.

DDQR

I/O

10L

I/O

10R

I/O

11L

I/O

11R

DDQL

I/O

12L

I/O

12R

DDQR

DDQL

I/O

13R

I/O

13L

I/O

14R

I/O

14L

DDQR

I/O

15R

I/O

15L

I/O

16R

I/O

16L

I/O

17R

I/O

17L

DDQL

1
2
3
4

5
6

7
8

9
10
11
12

13
14

15
16

17
18
19
20

21
22

23
24
25

26
27
28

29
30

31
32
33
34

35
36

108
107

106
105

104
103
102
101

100

98
97

96
95
94
93

92
91

90
89

88
87
86
85

84
83

82
81
80

79
78
77

76
75

74
73

(
4

)

I
N

OPT

DDQR

I/O

DDQL

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

OPT

(
4

)

I
N

70T633/1DD

DD-144

(5,6)

144-Pin TQFP

Top View

(7)

5670 drw 02a

03/13/03

Pin Configurations

(1,2,3,8)

(con't.)

IDT70T633/1S Preliminary
High-Speed 2.5V 512/256K x 18 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

NOTES:
1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground.

4. A

18X

is a NC for IDT70T631.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.

I/O

S S

INT

SEM

12L

16L

OPT

S S

BUSY

13L

17L

I/O

DD QR

S S

DD QL

I/O

DDQR

1 0L

14 L

18L(4)

I/O

11L

I/O

10L

I/O

11R

D DQ R

I/O

10 R

DD QL

S S

I/O

12L

D DQ R

I/O

12R

DD QL

D D

I/O

14L

D DQ R

DD QL

I/O

15R

I/O

7 R

D DQL

I/O

15 L

11L

7 L

I/O

S S

I/O

DD QL

I/O

D D

I/O

DDQ R

I/O

D DQL

I/O

S S

I/O

15 L

16R

12R

D D

SEM

INT

DDQ R

I/O

S S

I/O

17 R

17R

13R

S S

BUSY

S S

D DQ L

I/O

DDQR

I/O

17L

D DQ L

18R (4)

14R

1 0R

S S

I/O

S S

15R

11R

DD QL

I/O

OPT

I/O

70T633/1BF

BF-208

(5,6)

208-Ball BGA

Top View

(7)

5670 drw 02b

I/O

13L

I/O

14R

S S

I/O

13R

S S

I/O

16R

I/O

16L

D DQ R

S S

D DQ R

TDO

TDI

TCK

TMS

TRST

03/12/03

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70T631

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70T631