APRIL 2003

DSC-5632/1

256/128K x 36

MEMORY

ARRAY

Address

Decoder

17R(1)

Address
Decoder

Dout0-8_L

Dout9-17_L
Dout18-26_L
Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R
Dout27-35_R

B
E
0
L

B
E
1
L

B
E
2
L

B
E
3
L

B
E
3
R

B
E
2
R

B
E
1
R

B
E
0
R

I/O

0L-

I/O

35L

17L(1)

I/O

0R -

I/O

35R

Di n_L

ADDR_L

Di n_R

ADDR_R

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

SEM

INT

L(3)

BUSY

L(2,3)

BUSY

R(2,3)

SEM

INT

R(3)

4869 drw 01

CONTROL

LOGIC

(4)

JTAG

TC K

TRST

TMS

TDI

TD O

Functional Block Diagram

Full on-chip hardware support of semaphore signaling
between ports

Fully asynchronous operation from either port

Separate byte controls for multiplexed bus and bus
matching compatibility

Sleep Mode Inputs on both ports

Supports JTAG features compliant to IEEE 1149.1

Single 2.5V (±100mV) power supply for core

LVTTL-compatible, selectable 3.3V (±150mV)/2.5V (±100mV)
power supply for I/Os and control signals on each port

Available in a 256-ball Ball Grid Array, 208-pin Plastic Quad
Flatpack and 208-ball fine pitch Ball Grid Array.

Industrial temperature range (40°C to +85°C) is available
for selected speeds

Features

True Dual-Port memory cells which allow simultaneous
access of the same memory location

High-speed access
Commercial: 10/12/15ns (max.)
Industrial: 12ns (max.)

Dual chip enables allow for depth expansion without
external logic

IDT70T651/9 easily expands data bus width to 72 bits or
more using the Master/Slave select when cascading more
than one device

M/S = V

for BUSY output flag on Master,

M/S = V

for BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

HIGH-SPEED 2.5V
256/128K x 36

ASYNCHRONOUS DUAL-PORT

STATIC RAM

WITH 3.3V 0R 2.5V INTERFACE

PRELIMINARY

IDT70T651/9S

NOTES:
1. Address A

17x

is a NC for IDT70T659.

2. BUSY is an input as a Slave (M/S=V

) and an output when it is a Master (M/S=V

3. BUSY and INT are non-tri-state totem-pole outputs (push-pull).
4. The sleep mode pin shuts off all dynamic inputs, except JTAG inputs, when asserted. OPTx, BUSYx, INTx, M/S

and the sleep mode pins themselves (ZZx) are not affected during sleep mode.

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description

The IDT70T651/9 is a high-speed 256/128K x 36 Asynchronous

Dual-Port Static RAM. The IDT70T651/9 is designed to be used as a
stand-alone 9216/4608K-bit Dual-Port RAM or as a combination MAS-
TER/SLAVE Dual-Port RAM for 72-bit-or-more word system. Using the
IDT MASTER/SLAVE Dual-Port RAM approach in 72-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.

This device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (either CE

or CE

) permit the

on-chip circuitry of each port to enter a very low standby power mode.

The 70T651/9 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controlled by the OPT pins. The power supply for
the core of the device (V

) is at 2.5V.

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3)

NOTES:
1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. A

17X

is a NC for IDT70T659.

5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.

70T651/9BC

BC-256

(5,6)

256-Pin BGA

Top View

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

C14

OPT

B14

A14

A12

B12

C11

BUSY

D12

DDQR

D11

DDQR

C10

SEM

B11

A11

INT

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

15L

13L

DDQL

17L(4)

16L

TDO

I/O

20L

I/O

19R

I/O

19L

TDI

I/O

18L

I/O

18R

I/O

20R

I/O

21R

I/O

21L

I/O

22L

DDQL

I/O

23L

I/O

22R

I/O

23R

DDQL

I/O

24R

I/O

24L

I/O

25L

DDQR

I/O

26L

I/O

25R

I/O

26R

DDQR

I/O

27L

I/O

28R

I/O

27R

DDQL

I/O

29R

I/O

29L

I/O

28L

DDQL

I/O

30L

I/O

31R

I/O

30R

DDQR

I/O

32R

I/O

32L

I/O

31L

DDQR

I/O

33L

I/O

34R

I/O

33R

I/O

35R

I/O

34L

TMS

16R

I/O

35L

TRST

TCK

17R(4)

13R

15R

P12

P10

SEM

T11

INT

P11

BUSY

R12

T12

P13

R13

T13

12R

14R

T14

R14

OPT

P14

I/O

P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R11

11R

11L

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5632 drw 02f

03/18/03

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V) and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground.

4. A

17X

is a NC for IDT70T659.

5. Package body is approximately 28mm x 28mm x 3.5mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

70T651/9DR

DR-208

(5,6)

208-Pin

PQFP

Top View

(7)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

I
/
O

(
4

)

I
N

I
/
O

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

I
/
O

(
4

)

I
N

I
/
O

5632 drw 02d

03/18/03

Pin Configurations

(1,2,3)

(con't.)

IDT70T651/9S Preliminary
High-Speed 2.5V 256/128K x 36 Asynchronous Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configurations

(1,2,3)

(con't.)

NOTES:
1. All V

pins must be connected to 2.5V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(2.5V) and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground.

4. A

17X

is a NC for IDT70T659.

5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.

I/O

19L

I/O

18L

INT

SEM

12L

16L

S S

I/O

17L

OPT

I/O

20R

I/O

18R

BUSY

9 L

13L

17L (4)

I/O16L

DD QR

S S

DD QL

I/O

19R

DD QR

1 0L

14 L

I/O

15L

I/O

16R

I/O

22L

I/O

21L

I/O

20L

D D

I/O

23L

I/O

22R

D DQ R

I/O

21R

DD QL

I/O

23R

I/O

24L

S S

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DD QR

I/O

25R

DD QL

D D

I/O

29R

I/O

28L

D DQ R

DD QL

I/O

29L

I/O

30R

S S

I/O

14R

D DQ L

I/O

14L

15L

11L

7 L

I/O

12L

I/O

13R

S S

I/O

13L

S S

I/O

12R

I/O

11L

I/O

DD QL

I/O

10L

I/O

11R

D D

I/O

10R

DD QR

I/O

D DQL

I/O8R

S S

I/O

5 R

I/O

31L

I/O

31R

I/O

30L

16R

12R

SEM

INT

DD QR

I/O

S S

I/O

33L

I/O

34R

13R

BUSY

S S

D DQ L

I/O

DD QR

I/O

33R

I/O

34L

DD QL

17R(4)

14R

1 0R

S S

I/O

S S

I/O

S S

I/O

35L

D D

15R

11R

7 R

DD QL

I/O

OPT

I/O

70T651/9BF

BF-208

(5,6)

208-Ball

fpBGA

Top View

(7)

5632 drw 02e

I/O

27L

I/O

28R

S S

I/O

27R

S S

I/O

32R

I/O

32L

D DQ R

I/O

3 5R

S S

I/O

17R

DD QR

S S

I/O

15R

D D

TDO

TDI

TCK

TMS

TRST

03/18/03

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70T659

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70T659