2000 Integrated Device Technology, Inc.
1
JANUARY 2001
DSC-3740/4
I/O
Control
Address
Decoder
64Kx8
MEMORY
ARRAY
70V08
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
CE
0L
OE
L
R/
W
L
A
15L
A
0L
I/O
0-7L
A
15L
A
0L
SEM
L
I
NT
L
(2)
BUSY
L
(1,2)
R/
W
L
CE
0L
OE
L
I/O
Control
Address
Decoder
OE
R
R/
W
R
CE
0R
A
15R
A
0R
A
15R
A
0R
I/O
0-7R
SEM
R
INT
R
(2)
R
BUSY
(1,2)
M/
S
(1)
CE
1L
R/
W
R
CE
0R
OE
R
CE
1R
3740 drw 01
1L
CE
1R
CE
Functional Block Diagram
more using the Master/Slave select when cascading more
than one device
x
x
x
x
x
M/
S = V
IH
for
BUSY output flag on Master,
M/
S = V
IL
for
BUSY input on Slave
x
x
x
x
x
Busy and Interrupt Flags
x
x
x
x
x
On-chip port arbitration logic
x
x
x
x
x
Full on-chip hardware support of semaphore signaling
between ports
x
x
x
x
x
Fully asynchronous operation from either port
x
x
x
x
x
LVTTL-compatible, single 3.3V (0.3V) power supply
x
x
x
x
x
Available in a 100-pin TQFP
x
x
x
x
x
Industrial temperature range (40C to +85C) is available
for selected speeds
Features
x
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
x
x
x
x
High-speed access
Commercial: 15/20/25/35ns (max.)
x
x
x
x
x
Low-power operation
IDT70V08S
Active: 550mW (typ.)
Standby: 5mW (typ.)
IDT70V08L
Active: 550mW (typ.)
Standby: 1mW (typ.)
x
x
x
x
x
Dual chip enables allow for depth expansion without
external logic
x
x
x
x
x
IDT70V08 easily expands data bus width to 16 bits or
HIGH-SPEED
64K x 8 DUAL-PORT
STATIC RAM
IDT70V08S/L
NOTES:
1.
BUSY is an input as a Slave (M/S-V
IL
) and an output when it is a Master (M/
S-V
IH
).
2.
BUSY and INT are non-tri-state totem-pole outputs (push-pull).
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V08 is a high-speed 64K x 8 Dual-Port Static RAM. The
IDT70V08 is designed to be used as a stand-alone 512K-bit Dual-Port
RAM or as a combination MASTER/SLAVE Dual-Port RAM for 16-bit-
or-more word system. Using the IDT MASTER/SLAVE Dual-Port
RAM approach in 16-bit or wider memory system applications results
in full-speed, error-free operation without the need for additional
discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature controlled by the chip enables (either
CE
0
or CE
1
)
permit the on-chip circuitry of each port to enter a very low standby
power mode.
Fabricated using IDT's CMOS high-performance technology,
these devices typically operate on only 550mW of power.
The IDT70V08 is packaged in a 100-pin Thin Quad Flatpack
(TQFP).
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations
(1,2,3)
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
54
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V08PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
GND
GND
OE
R
R/
W
R
SEM
R
CE
1R
CE
0R
NC
NC
GND
A
15R
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
NC
3740 drw 02
NC
NC
GND
OE
L
R/
W
L
SEM
L
CE
1L
CE
0L
NC
NC
NC
Vcc
NC
A
15L
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
N
C
N
C
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
V
c
c
I
/
O
2
R
I
/
O
0
R
G
N
D
V
c
c
I
/
O
0
L
I
/
O
1
L
G
N
D
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
G
N
D
N
C
N
C
N
C
N
C
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
I
N
T
R
B
U
S
Y
R
M
/
S
B
U
S
Y
L
I
N
T
L
N
C
A
0
L
G
N
D
A
2
L
A
3
L
A
5
L
A
6
L
N
C
N
C
A
1
L
A
4
L
,
3
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
Absolute Maximum Ratings
(1)
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage
(1,2)
Pin Names
Capacitance
(1)
(T
A
= +25C, f = 1.0mhz)
NOTES:
1. This parameter is determined by device characterization but is not produc-
tion tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
N
OTES:
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.
V
TERM
must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 0.3V.
NOTES:
1.
V
IL
> -1.5V for pulse width less than 10ns.
2.
V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2.
Industrial temperature: for specific speeds, packages and powers contact yours
sales office.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50
mA
3740 tbl 01
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
3740 tbl 02
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
3740 tbl 03
Left Port
Right Port
Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
15L
A
0R
- A
15R
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power
GND
Ground
3740 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
CC
+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
3740 tbl 05
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Truth Table III Semaphore Read/Write Control
(1)
Truth Table I Chip Enable
(1,2)
NOTES:
1.
Chip Enable references are shown above with the actual
CE
0
and CE
1
levels;
CE is a reference only.
2.
'H' = V
IH
and 'L' = V
IL
.
3.
CMOS standby requires 'X' to be either < 0.2V or >V
CC
-0.2V.
Truth Table II Non-Contention Read/Write Control
NOTES:
1.
A
0L
-- A
15L
A
0R
-- A
15R
2.
Refer to Chip Enable Truth Table.
NOTES:
1. There are eight semaphore flags written to I/O
0
and read from all the I/Os (I/O
0
-I/O
7
). These eight semaphore flags are addressed by A
0
-A
2
.
2. Refer to Chip Enable Truth Table.
CE
CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
< 0.2V
>V
CC
-0.2V
Port Selected (CMOS Active)
H
V
IH
X
Port Deselected (TTL Inactive)
X
V
IL
Port Deselected (TTL Inactive)
>V
CC
-0.2V
X
(3)
Port Deselected (CMOS Inactive)
X
(3)
<0.2V
Port Deselected (CMOS Inactive)
3740 tbl 06
Inputs
(1)
Outputs
Mode
CE
(2)
R/
W
OE
SEM
I/O
0-7
H
X
X
H
High-Z
Deselected: Power-Down
L
L
X
H
DATA
IN
Write to Memory
L
H
L
H
DATA
OUT
Read Memory
X
X
H
X
High-Z
Outputs Disabled
3740 tbl 07
Inputs
(1)
Outputs
Mode
CE
(2)
R/
W
OE
SEM
I/O
0-7
H
H
L
L
DATA
OUT
Read Semaphore Flag Data Out
H
X
L
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
______
Not Allowed
3740 tbl 08
5
IDT70V08S/L
High-Speed 64K x 8 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6,7)
(V
CC
= 3.3V 0.3V)
NOTES:
1. 'X' in part numbers indicates power rating (S or L)
2. V
CC
= 3.3V, T
A
= +25C, and are not production tested. I
CCDC
= 90mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using "AC Test Conditions" of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
NOTES:
1. At Vcc
<
2.0V, input leakages are undefined.
2. Refer to Chip Enable Truth Table.
Symbol
Parameter
Test Conditions
70V08S
70V08L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
CE
(2)
= V
IH
, V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
3740 tbl 09
Symbol
Parameter
Test Condition
Version
70V08X15
Com'l Only
Typ.
(2)
Max
70V08X20
Com'l Only
Typ.
(2)
Max
Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L
S
L
170
170
260
265
165
165
255
220
mA
IND
S
L
____
____
____
____
____
____
____
____
I
SB1
Standby Current
(Both Ports - TTL Level
Inputs)
CE
L
=
CE
R
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
COM'L
S
L
44
44
70
60
39
39
60
50
mA
IND
S
L
____
____
____
____
____
____
____
____
I
SB2
Standby Current
(One Port - TTL Level Inputs)
CE
"A"
= V
IL
and CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
COM'L
S
L
115
115
160
145
105
105
155
140
mA
IND
S
L
____
____
____
____
____
____
____
____
I
SB3
Full Standby Current (Both
Ports - All CMOS Level
Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
= SEM
L
> V
CC
- 0.2V
COM'L
S
L
1.0
0.2
6
3
1.0
0.2
6
3
mA
IND
S
L
____
____
____
____
____
____
____
____
I
SB4
Full Standby Current
(One Port - All CMOS Level
Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L
S
L
115
115
155
140
105
105
150
135
mA
IND
S
L
____
____
____
____
____
____
____
____
3740 tbl 10a
PDF 
ZIP