6.01

JANUARY 2001

DSC 3603/7

Features:

True Dual-Ported memory cells which allow simultaneous
access of the same memory location

High-speed access
Industrial: 35ns (max.)
Commercial: 15/20/25/35/55ns (max.)

Low-power operation
 IDT70V27S

Active: 500mW (typ.)
Standby: 3.3mW (typ.)

 IDT70V27L

Active: 500mW (typ.)
Standby: 660

W (typ.)

Separate upper-byte and lower-byte control for bus
matching capability

Dual chip enables allow for depth expansion without
external logic

IDT70V27S/L

IDT70V27 easily expands data bus width to 32 bits or more
using the Master/Slave select when cascading more than
one device

S = V

for

BUSY output flag on Master,

S = V

for

BUSY input on Slave

Busy and Interrupt Flags

On-chip port arbitration logic

Full on-chip hardware support of semaphore signaling
between ports

Fully asynchronous operation from either port

LVTTL-compatible, single 3.3V (±0.3V) power supply

Available in 100-pin Thin Quad Flatpack (TQFP), 108-pin
Ceramic Pin Grid Array (PGA), and 144-pin Fine Pitch BGA
(fpBGA)

Industrial temperature range (-40°C to +85°C) is available
for selected speeds

I/O

Control

Address

Decoder

32Kx16

MEMORY

ARRAY

70V27

ARBITRATION

INTERRUPT

SEMAPHORE

LOGIC

14L

SEM

INT

(2)

BUSY

(1,2)

I/O

Control

Address

Decoder

14R

SEM

INT

(2)

BUSY

(1,2)

(2)

3603 drw 01

I/O

0-7L

I/O

8-15L

I/O

0-7R

I/O

8-15R

NOTES:
1)

BUSY is an input as a Slave (M/S=V

) and an output as a Master (M/

S=V

BUSY and INT are non-tri-state totem-pole outputs (push-pull).

HIGH-SPEED 3.3V
32K x 16 DUAL-PORT
STATIC RAM

Functional Block Diagram

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Description:

The IDT70V27 is a high-speed 32K x 16 Dual-Port Static RAM,

designed to be used as a stand-alone 512K-bit Dual-Port RAM or as a
combination MASTER/SLAVE Dual-Port RAM for 32-bit and wider word
systems. Using the IDT MASTER/SLAVE Dual-Port RAM approach in 32-
bit or wider memory system applications results in full-speed, error-free
operation without the need for additional discrete logic.

The device provides two independent ports with separate control,

address, and I/O pins that permit independent, asynchronous access for

reads or writes to any location in memory. An automatic power down
feature controlled by the chip enables (

and

) permits the on-chip

circuitry of each port to enter a very low standby power mode.

Fabricated using IDT's CMOS high-performance technology,

these devices typically operate on only 500mW of power. The IDT70V27
is packaged in a 100-pin Thin Quad Flatpack (TQFP), a 108-pin ceramic
Pin Grid Array (PGA), and a 144-pin Fine Pitch BGA (fp BGA).

Pin Configurations

(1,2,3)

NOTES:
1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.

INDEX

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

IDT70V27PF

PN100-1

(4)

100-PIN TQFP

TOP VIEW

(5)

GND

SEM

GND

12R

13R

11R

10R

14R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

GND

3603 drw 02

I/O

15L

GND

SEM

Vcc

14L

13L

12L

11L

10L

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

GND

I
/
O

I
N

I
/
O

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Pin Configurations

(1,2,3)

(con't.)

NOTES:
1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground supply.
3. Package body is approximately 12mm x 12mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.

3603 drw 02a

IDT70V27BF

BF144-1

(4)

144-Pin fpBGA

Top View

(5)

BUSY

11L

I/O

GND

I/O

GND

I/O

SEM

GND

I/O

14R

GND

I/O1

I/O

12R

GND

I/O

10R

12L

13L

I/O

15L

I/O

14L

I/O

10L

I/0

13L

I/O

11R

I/O

13R

INT

GND

BUSY

10L

14L

A10

A11

A12

A13

SEM

GND

I/O

12L

I/O

11L

I/O

B10

B11

B12

B13

C10

C11

C12

C13

D10

D11

D12

D13

E10

E11

E12

E13

F10

F11

F12

F13

G10

G11

G12

G13

H10

H11

H12

H13

J10

J11

J12

J13

K10

K11

K12

K13

L10

L11

L12

L13

M10

M11

M12

M13

N10

N11

N12

N13

INT

10R

11R

12R

13R

14R

I/O

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Pin Configurations

(1,2,3)

(con't.)

3603 drw 03

100

103

101

105

104

IDT70V27G

G108-1

(4)

108-PIN PGA

TOP VIEW

(5)

102

106

107

108

INDEX

GND

SEM

GND

12R

13R

11R

10R

GND

SEM

Vcc

14L

13L

12L

11L

10L

I/O

GND

Vcc

I/O

GND

I/O

Vcc

INT

BUSY

INT

GND

14R

I/O

10R

I/O

11R

I/O

12R

I/O

13R

I/O

14R

I/O

15R

I/O

10L

I/O

11L

I/O

12L

I/O

13L

I/O

14L

GND

I/O

15L

Left Port

Right Port

Names

, CE

Chip Enable

R/W

Read/Write Enable

Output Enable

- A

14L

- A

14R

Address

I/O

- I/O

15L

I/O

- I/O

15R

Data Input/Output

SEM

Semaphore Enable

Upper Byte Select

Lower Byte Select

INT

Interrupt Flag

BUSY

Busy Flag

M/S

Master or Slave Select

Power

GND

Ground

3603 tbl 01

Pin Names

NOTES:
1. All V

pins must be connected to power supply.

2. All GND pins must be connected to ground supply.
3. Package body is approximately 1.21in x 1.21in x .16in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Truth Table II Non-Contention Read/Write Control

NOTES:

1. Chip Enable references are shown above with the actual

and CE

levels,

CE is a reference only.

2. Port "A" and "B" references are located where

CE is used.

3. "H" = V

and "L" = V

Truth Table I Chip Enable

(1,2,3)

Truth Table III Semaphore Read/Write Control

NOTES:
1. A

-- A

14L

-- A

14R.

2. Refer to Chip Enable Truth Table.

NOTES:
1. There are eight semaphore flags written to I/O

and read from all the I/Os (I/O

-I/O

). These eight semaphore flags are addressed by A

-A

2. Refer to Chip Enable Truth Table.

Mode

Port Selected (TTL Active)

< 0.2V

-0.2V

Port Selected (CMOS Active)

Port Deselected (TTL Inactive)

-0.2V

Port Deselected (CMOS Inactive)

<0.2V

Port Deselected (CMOS Inactive)

3603 tbl 02

Inputs

(1)

Outputs

Mode

(2)

SEM

I/O

8-15

I/O

0-7

High-Z

Deselected: Power-Down

High-Z

Both Bytes Deselected

DATA

High-Z

Write to Upper Byte Only

High-Z

DATA

Write to Lower Byte Only

DATA

Write to Both Bytes

DATA

OUT

High-Z

Read Upper Byte Only

High-Z

DATA

OUT

Read Lower Byte Only

DATA

OUT

DATA

OUT

Read Both Bytes

High-Z

Outputs Disabled

3603 tbl 03

Inputs

(1)

Outputs

Mode

(2)

SEM

I/O

8-15

I/O

0-7

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

DATA

OUT

DATA

OUT

Read Data in Semaphore Flag

DATA

Write I/O

into Semaphore Flag

DATA

Write I/O

into Semaphore Flag

______

Not Allowed

______

Not Allowed

3603 tbl 04

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Capacitance

(1)

= +25°C, f = 1.0mhz)TQFP ONLY

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V ± 0.3V)

NOTE:

1. At Vcc

2.0V, input leakages are undefined.

Maximum Operating Temperature

and Supply Voltage

(1,2)

Recommended DC Operating

Conditions

(1)

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS

may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.

2. V

TERM

must not exceed Vcc + 0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> Vcc + 0.3V.

Absolute Maximum Ratings

(1)

NOTES:
1. V

> -1.5V for pulse width less than 10ns.

2. V

TERM

must not exceed Vcc + 0.3V.

NOTES:
1. This parameter is determined by device characterization but is not

production tested.

2. 3dV represents the interpolated capacitance when the input and output signals

switch from 0V to 3V or from 3V to 0V.

NOTES:
1. This is the parameter T

. This is the "instant on" case temperature.

2. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage
with Respect
to GND

-0.5 to +4.6

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-65 to +150

OUT

DC Output
Current

3603 tbl 05

Grade

Ambient

Temperature

GND

Vcc

Commercial

C to +70

3.3V

0.3V

Industrial

-40

C to +85

3.3V

0.3V

3603 tbl 06

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

Output
Capacitance

OUT

= 3dV

3603 tbl 08

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

3.0

3.3

3.6

GND

Ground

Input High Voltage

2.0

____

+0.3V

(2)

Input Low Voltage

-0.3

(1)

____

0.8

3603 tbl 07

Symbol

Parameter

Test Conditions

70V27S

70V27L

Unit

Min.

Max.

Min.

Max.

Input Leakage Current

(1)

= 3.6V, V

= 0V to V

___

µ A

Output Leakage Current

CE = V

, V

OUT

= 0V to V

___

µ A

Output Low Voltage

= 4mA

___

0.4

___

0.4

Output High Voltage

= -4mA

2.4

___

2.4

___

3603 tbl 09

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(1,6,7)

= 3.3V ± 0.3V)

NOTES:
1.

'X' in part numbers indicates power rating (S or L).

= 3.3V, T

= +25°C, and are not production tested. I

CCDC

= 90mA (Typ.)

At f = f

MAX

address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t

RC,

and using "AC Test Conditions" of input

levels of GND to 3V.

f = 0 means no address or control lines change.

Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.

70V27X15

Com'l Only

70V27X20

Com'l Only

70V27X25

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.

(2)

Max.

Typ.

(2)

Max.

Typ.

(2)

Max.

Unit

Dynamic Operating
Current
(Both Ports Active)

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L

S
L

170
170

260
225

165
165

255
220

145
145

245
210

IND'L

S
L

____

145
145

280
245

SB1

Standby Current
(Bo th Ports - TTL Level
Inputs)

= V

SEM

= V

f = f

MAX

(3)

COM'L

S
L

44
44

70
60

39
39

60
50

27
27

50
40

IND'L

S
L

____

27
27

60
50

SB2

Standby Current
(One Port - TTL Level
Inputs)

"A"

= V

and

"B"

= V

(5)

Active Port Outputs Disabled,

f=f

MAX

(3)

SEM

= V

COM'L

S
L

115
115

160
145

105
105

155
140

90
90

150
135

IND'L

S
L

____

90
90

170
150

SB3

Full Standby Current
(Both Ports - All
CMOS Level Inputs)

Both Ports

and

> V

- 0.2V

> V

- 0.2V or

< 0.2V, f = 0

(4)

SEM

> V

- 0.2V

COM'L

S
L

1.0
0.2

6
3

1.0
0.2

6
3

1.0
0.2

6
3

IND'L

S
L

____

1.0
0.2

SB4

Full Standby Current
(One Port - All CMOS
Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

SEM

> V

- 0.2V

> V

- 0.2V or V

< 0.2V

Active Port Outputs Disabled
f = f

MAX

(3)

COM'L

S
L

115
115

155
140

105
105

150
135

90
90

145
130

IND'L

S
L

____

90
90

170
145

3603 tbl 10a

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

AC Test Conditions

Figure 1. AC Output Test Load

3603 drw 04

590

30pF

435

3.3V

DATA

OUT

BUSY

INT

590

5pF*

435

3.3V

DATA

OUT

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns Max.

1.5V

Figures 1 and 2

3603 tbl 11

Figure 2. Output Test Load

(for t

, t

)

*Including scope and jig.

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(1,6,7)

= 3.3V ± 0.3V)

NOTES:
1.

'X' in part numbers indicates power rating (S or L).

= 3.3V, T

= +25°C, and are not production tested. I

CCDC

= 90mA (Typ.)

At f = f

MAX

address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t

RC,

and using "AC Test Conditions" of input

levels of GND to 3V.

f = 0 means no address or control lines change.

Port "A" may be either left or right port. Port "B" is the opposite from port "A".

6. Refer to Chip Enable Truth Table.
7. Industrial temperature: for other speeds, packages and powers contact your sales office.

70V27X35

Com'l & Ind

70V27X55

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.

(2)

Max.

Typ.

(2)

Max.

Unit

Dynamic Operating Current
(Both Ports Active)

CE = V

, Outputs Disabled

SEM = V

f = f

MAX

(3)

COM'L

S
L

135
135

235
190

125
125

225
180

IND'L

S
L

135
135

270
235

125
125

260
225

SB1

Standby Current
(Bo th Ports - TTL Level
Inputs)

= V

SEM

= V

f = f

MAX

(3)

COM'L

S
L

22
22

45
35

15
15

40
30

IND'L

S
L

22
22

55
45

15
15

50
40

SB2

Standby Current
(One Port - TTL Level
Inputs)

"A"

= V

and

"B"

= V

(5)

Active Port Outputs Disabled,

f=f

MAX

(3)

SEM

= V

COM'L

S
L

85
85

140
125

75
75

140
125

IND'L

S
L

85
85

160
140

75
75

160
140

SB3

Full Standby Current (Both
Ports - All CMOS Level
Inputs)

Both Ports

and

> V

- 0.2V

> V

- 0.2V or

< 0.2V, f = 0

(4)

SEM

> V

- 0.2V

COM'L

S
L

1.0
0.2

6
3

1.0
0.2

6
3

IND'L

S
L

1.0
0.2

SB4

Full Standby Current
(One Port - All CMOS
Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

SEM

> V

- 0.2V

> V

- 0.2V or V

< 0.2V

Active Port Outputs Disabled
f = f

MAX

(3)

COM'L

S
L

85
85

135
120

75
75

135
120

IND'L

S
L

85
85

160
135

75
75

160
135

3603 tbl 10b

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

AC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(4, 6)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. To access RAM,

CE = V

and

SEM = V

. To access semaphore,

CE= V

and

SEM = V

4. 'X' in part numbers indicates power rating (S or L).
5. Refer to Chip Enable Truth Table.
6. Industrial temperature: for other speeds, packages and powers contact your sales office.

70V27X15

Com'l Only

70V27X20

Com'l Only

70V27X25

Com'l Only

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

____

Address Access Time

____

ACE

Chip Enable Access Time

(3)

____

ABE

Byte Enable Access Time

(3)

____

AOE

Output Enable Access Time

____

Output Hold from Address Change

____

Output Low-Z Time

(1,2)

____

Output High-Z Time

(1,2)

____

Chip Enable to Power Up Time

(2,5)

____

Chip Disable to Power Down Time

(2,5)

____

SOP

Semaphore Flag Update Pulse (

OE or SEM)

____

SAA

Semaphore Address Access Time

____

3603 tbl 12a

70V27X35

Com'l & Ind

70V27X55

Com'l Only

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

READ CYCLE

Read Cycle Time

____

Address Access Time

____

ACE

Chip Enable Access Time

(3)

____

ABE

Byte Enable Access Time

(3)

____

AOE

Output Enable Access Time

____

Output Hold from Address Change

____

Output Low-Z Time

(1,2)

____

Output High-Z Time

(1,2)

____

Chip Enable to Power Up Time

(2,5)

____

Chip Disable to Power Down Time

(2,5)

____

SOP

Semaphore Flag Update Pulse (

OE or SEM)

____

SAA

Semaphore Address Access Time

____

3603 tbl 12b

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

CE= V

and

SEM = V

. To access semaphore,

CE = V

and

SEM = V

. Either condition must be valid for the entire t

time. Refer to Chip Enable

Truth Table.

4. The specification for t

must be met by the device supplying write data to the RAM under all operating conditions. Although t

and t

values will vary over voltage

and temperature, the actual t

will always be smaller than the actual t

5. 'X' in part numbers indicates power rating (S or L).
6. Industrial temperature: for other speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage

(5,6)

Symbol

Parameter

70V27X15

Com'l Only

70V27X20

Com'l Only

70V27X25

Com'l Only

Unit

Min.

Max.

Min.

Max.

Min.

Max.

WRITE CYCLE

Write Cycle Time

____

Chip Enable to End-of-Write

(3)

____

Address Valid to End-of-Write

____

Address Set-up Time

(3)

____

Write Pulse Width

____

Write Recovery Time

____

Data Valid to End-of-Write

____

Output High-Z Time

(1,2)

____

Data Hold Time

(4)

____

Write Enable to Output in High-Z

(1,2)

____

Output Active from End-of-Write

(1,2,4)

____

SWRD

SEM Flag Write to Read Time

____

SPS

SEM Flag Contention Window

____

3603 tbl 13a

Symbol

Parameter

70V27X35

Com'l & Ind

70V27X55

Com'l Only

Unit

Min.

Max.

Min.

Max.

WRITE CYCLE

Write Cycle Time

____

Chip Enable to End-of-Write

(3)

____

Address Valid to End-of-Write

____

Address Set-up Time

(3)

____

Write Pulse Width

____

Write Recovery Time

____

Data Valid to End-of-Write

____

Output High-Z Time

(1,2)

____

Data Hold Time

(4)

____

Write Enable to Output in High-Z

(1,2)

____

Output Active from End-of-Write

(1,2,4)

____

SWRD

SEM Flag Write to Read Time

____

SPS

SEM Flag Contention Window

____

3603 tbl 13b

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Timing Waveform of Write Cycle No. 1, R/W Controlled Timing

(1,5,8)

NOTES:
1. R/

W or CE or UB and LB must be HIGH during all address transitions.

2. A write occurs during the overlap (t

or t

) of a LOW

CE and a LOW R/W for memory array writing cycle.

3. t

is measured from the earlier of

CE or R/W (or SEM or R/W) going HIGH to the end of write cycle.

4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the

CE or SEM LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.

6. Timing depends on which enable signal is asserted last,

CE or R/W.

7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load (Figure

2).

8. If

OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t

or (t

+ t

) to allow the I/O drivers to turn off and data to be placed

on the bus for the required t

. If

OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the

specified t

9. To access RAM,

CE = V

and

SEM = V

. To access semaphore,

CE = V

and

SEM = V

. t

must be met for either condition.

10. Refer to Chip Enable Truth Table.

Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing

(1,5)

DATA

OUT

(2)

ADDRESS

DATA

(6)

(4)

(7)

3603 drw 07

(9)

SEM

(9,10)

(7)

(3)

3603 drw 08

ADDRESS

DATA

(3)

(2)

(6)

SEM

(9,10)

(9)

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Timing Waveform of Semaphore Read after Write Timing, Either Side

(1)

NOTES:
1. D

= D

= V

, or both

UB & LB = V

(refer to Chip Enable Truth Table).

2. All timing is the same for left and right ports. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
3. This parameter is measured from R/

"A"

SEM

"A"

going HIGH to R/W

"B"

SEM

"B"

going HIGH.

4. If t

SPS

is not satisfied, there is no guarantee which side will be granted the semaphore flag.

SEM

3603 drw 09

SOP

I/O

VALID ADDRESS

SAA

ACE

VALID ADDRESS

DATA

VALID

DATA

OUT

SWRD

AOE

Read Cycle

Write Cycle

-A

VALID

(2)

NOTES:
1.

= V

UB and LB = V

for the duration of the above timing (both write and read cycle), refer to Chip Enable Truth Table.

2. "DATA

OUT

VALID" represents all I/O's (I/O

-I/O

) equal to the semaphore value.

SEM

"A"

3603 drw 10

SPS

MATCH

"A"

MATCH

0"A"

-A

2"A"

SIDE

"A"

(2)

SEM

"B"

0"B"

-A

2"B"

SIDE

(2)

"B"

Timing Waveform of Semaphore Write Contention

(1,3,4)

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

NOTES:
1. Port-to-port delay through RAM cells from writing port to reading port, refer to "Timing Waveform of Write with Port-to-Port Read and

BUSY (M/S = V

)".

2. To ensure that the earlier of the two ports wins.
3. t

BDD

is a calculated parameter and is the greater of 0, t

WDD

(actual), or t

DDD

(actual).

4. To ensure that the write cycle is inhibited on port "B" during contention on port "A".
5. To ensure that a write cycle is completed on port "B" after contention on port "A".
6. 'X' in part numbers indicates power rating (S or L).
7. Industrial temperature: for other speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(6,7)

70V27X15

Com'l Only

70V27X20

Com'l Only

70V27X25

Com'l Only

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

BUSY TIMING (M/

S=V

)

BAA

BUSY Access Time from Address Match

____

BDA

BUSY Disable Time from Address Not Matched

____

BAC

BUSY Access Time from Chip Enable Low

____

BDC

BUSY Disable Time from Chip Enable High

____

APS

Arbitration Priority Set-up Time

(2)

____

BDD

BUSY Disable to Valid Data

(3)

____

Write Hold After

BUSY

(5)

____

BUSY TIMING (M/

S=V

)

BUSY Input to Write

(4)

____

Write Hold After

BUSY

(5)

____

PORT-TO-PORT DELAY TIMING

WDD

Write Pulse to Data Delay

(1)

____

DDD

Write Data Valid to Read Data Delay

(1)

____

3603 tbl 14a

70V27X35 Com'l

& Ind

70V27X55

Com'l Only

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

BUSY TIMING (M/

S=V

)

BAA

BUSY Access Time from Address Match

____

BDA

BUSY Disable Time from Address Not Matched

____

BAC

BUSY Access Time from Chip Enable Low

____

BDC

BUSY Disable Time from Chip Enable High

____

APS

Arbitration Priority Set-up Time

(2)

____

BDD

BUSY Disable to Valid Data

(3)

____

Write Hold After

BUSY

(5)

____

BUSY TIMING (M/S=V

)

BUSY Input to Write

(4)

____

Write Hold After

BUSY

(5)

____

PORT-TO-PORT DELAY TIMING

WDD

Write Pulse to Data Delay

(1)

____

DDD

Write Data Valid to Read Data Delay

(1)

____

3603 tbl 14b

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Waveform of BUSY Arbitration Cycle Controlled by Address Match

Timing

(M/S = V

)

(1)

NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. If t

APS

is not satisfied, the busy signal will be asserted on one side or another but there is no guarantee on which side busy will be asserted.

3. Refer to Chip Enable Truth Table.

Waveform of BUSY Arbitration Controlled by CE Timing

(M/S = V

)

(1,3)

NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. Industrial temperature: for other speeds, packages and powers contact your sales office.

AC Electrical Characteristics Over the

Operating Temperature and Supply Voltage Range

(1,2)

3603 drw 13

ADDR

"A"

and

"B"

ADDRESSES MATCH

"B"

BUSY

"B"

APS

BAC

BDC

(2)

"A"

3603 drw 14

ADDR

"A"

ADDRESS "N"

ADDR

"B"

BUSY

"B"

APS

BAA

BDA

(2)

MATCHING ADDRESS "N"

Symbol

Parameter

70V27X15

Com'l Only

70V27X20

Com'l Only

70V27X25

Com'l Only

Unit

Min.

Max.

Min.

Max.

Min.

Max.

INTERRUPT TIMING

Address Set-up Time

____

Write Recovery Time

____

INS

Interrupt Set Time

____

INR

Interrupt Reset Time

____

3603 tbl 15a

Symbol

Parameter

70V27X35

Com'l &Ind

70V27X55

Com'l Only

Unit

Min.

Max.

Min.

Max.

INTERRUPT TIMING

Address Set-up Time

____

Write Recovery Time

____

INS

Interrupt Set Time

____

INR

Interrupt Reset Time

____

3603 tbl 15b

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Waveform of Interrupt Timing

(1,5)

Truth Table IV Interrupt Flag

(1,4)

NOTES:
1. Assumes

BUSY

2. If

BUSY

= V

, then no change.

3. If

BUSY

= V

, then no change.

4. Refer to Chip Enable Truth Table.

NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. See Interrupt Truth Table.
3. Timing depends on which enable signal (

or R/

W) is asserted last.

4. Timing depends on which enable signal (

CE or R/W) is de-asserted first.

5. Refer to Chip Enable Truth Table.

3603 drw 15

ADDR

"A"

INTERRUPT SET ADDRESS

"A"

(3)

(4)

INS

(3)

INT

"B"

(2)

3603 drw 16

ADDR

"B"

INTERRUPT CLEAR ADDRESS

"B"

(3)

INR

(3)

INT

"B"

(2)

Left Port

Right Port

Function

14L

-A

INT

14R

-A

INT

7FFF

(2)

Set Right

INT

Flag

7FFF

(3)

Reset Right

INT

Flag

(3)

7FFE

Set Left

INT

Flag

7FFE

(2)

Reset Left

INT

Flag

3603 tbl 16

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

Truth Table V Address BUSY Arbritration

(4)

NOTES:
1. Pins

BUSY

and

BUSY

are both outputs when the part is configured as a master. Both are inputs when configured as a slave.

BUSY

outputs on the IDT70V27 are

push-pull, not open drain outputs. On slaves the

BUSY input internally inhibits writes.

2. "L" if the inputs to the opposite port were stable prior to the address and enable inputs of this port. "H" if the inputs to the opposite port became stable after the address

and enable inputs of this port. If t

APS

is not met, either

BUSY

= LOW will result.

BUSY

and

BUSY

outputs can not be LOW simultaneously.

3. Writes to the left port are internally ignored when

BUSY

outputs are driving LOW regardless of actual logic level on the pin. Writes to the right port are internally ignored

when

BUSY

outputs are driving LOW regardless of actual logic level on the pin.

4. Refer to Chip Enable Truth Table.

Truth Table VI Example of Semaphore Procurement Sequence

(1,2)

NOTES:
1. This table denotes a sequence of events for only one of the eight semaphores on the IDT70V27.
2. There are eight semaphore flags written to via I/O

and read from all the I/O's (I/O

-I/O

). These eight semaphores are addressed by A

- A

Functional Description

The IDT70V27 provides two ports with separate control, address and

I/O pins that permit independent access for reads or writes to any location
in memory. The IDT70V27 has an automatic power down feature
controlled by

and CE

. The

and

control the on-chip power

down circuitry that permits the respective port to go into a standby mode
when not selected (

CE HIGH). When a port is enabled, access to the entire

memory array is permitted.

Interrupts

If the user chooses the interrupt function, a memory location (mail box

or message center) is assigned to each port. The left port interrupt flag
(

INT

) is asserted when the right port writes to memory location 7FFE

(HEX), where a write is defined as

= R/

= V

per the Truth Table

IV. The left port clears the interrupt through access of address location

7FFE when

= V

, R/

W is a "don't care". Likewise, the right

port interrupt flag (

INT

) is asserted when the left port writes to memory

location 7FFF (HEX) and to clear the interrupt flag (

INT

), the

right port must read the memory location 7FFF. The message (16 bits) at
7FFE or 7FFF is user-defined since it is an addressable SRAM location.
If the interrupt func-tion is not used, address locations 7FFE and 7FFF are
not used as mail boxes, but as part of the random access memory. Refer
to Truth Table IV for the interrupt operation.

Busy Logic

Busy Logic provides a hardware indication that both ports of the RAM

have accessed the same location at the same time. It also allows one of the
two accesses to proceed and signals the other side that the RAM is "Busy".
The

BUSY pin can then be used to stall the access until the operation on

Inputs

Outputs

Function

-A

14L

-A

14R

BUSY

(1)

BUSY

(1)

NO MATCH

Normal

MATCH

Normal

MATCH

Normal

MATCH

(2)

Write Inhibit

(3)

3603 tbl 17

Functions

D0 - D15 Left

- D

Right

Status

No Action

Semaphore free

Left Port Writes "0" to Semaphore

Left port has semaphore token

Right Port Writes "0" to Semaphore

No change. Right side has no write access to semaphore

Left Port Writes "1" to Semaphore

Right port obtains semaphore token

Left Port Writes "0" to Semaphore

No change. Left port has no write access to semaphore

Right Port Writes "1" to Semaphore

Left port obtains semaphore token

Left Port Writes "1" to Semaphore

Semaphore free

Right Port Writes "0" to Semaphore

Right port has semaphore token

Right Port Writes "1" to Semaphore

Semaphore free

Left Port Writes "0" to Semaphore

Left port has semaphore token

Left Port Writes "1" to Semaphore

Semaphore free

3603 tbl 18

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

the other side is completed. If a write operation has been attempted from
the side that receives a

BUSY indication, the write signal is gated internally

to prevent the write from proceeding.

The use of

BUSY logic is not required or desirable for all applications.

In some cases it may be useful to logically OR the

BUSY outputs together

and use any

BUSY indication as an interrupt source to flag the event of

an illegal or illogical operation. If the write inhibit function of

BUSY logic is

not desirable, the

BUSY logic can be disabled by placing the part in slave

mode with the M/

S pin. Once in slave mode the BUSY pin operates solely

as a write inhibit input pin. Normal operation can be programmed by tying
the

BUSY pins HIGH. If desired, unintended write operations can be

prevented to a port by tying the

BUSY pin for that port LOW.

The

BUSY outputs on the IDT 70V27 RAM in master mode, are push-

pull type outputs and do not require pull up resistors to operate. If these
RAMs are being expanded in depth, then the

BUSY indication for the

resulting array requires the use of an external AND gate.

Width Expansion with BUSY Logic

Master/Slave Arrays

When expanding an IDT70V27 RAM array in width while using

BUSY

Figure 3. Busy and chip enable routing for both width and depth

expansion with IDT70V27 RAMs.

logic, one master part is used to decide which side of the RAM array
will receive a

BUSY indication, and to output that indication. Any number

of slaves to be addressed in the same address range as the master, use
the busy signal as a write inhibit signal. Thus on the IDT70V27 RAM the
BUSY pin is an output if the part is used as a master (M/S pin = V

), and

the

BUSY pin is an input if the part is used as a slave (M/S pin = V

) as

shown in Figure 3.

If two or more master parts were used when expanding in width, a split

decision could result with one master indicating

BUSY on one side of the

array and another master indicating

BUSY on one other side of the array.

This would inhibit the write operations from one port for part of a word and
inhibit the write operations from the other port for the other part of the word.

The

BUSY arbitration, on a master, is based on the chip enable and

address signals only. It ignores whether an access is a read or write. In
a master/slave array, both address and chip enable must be valid long
enough for a

BUSY flag to be output from the master before the actual write

pulse can be initiated with either the R/

W signal or the byte enables. Failure

to observe this timing can result in a glitched internal write inhibit signal and
corrupted data in the slave.

Semaphores

The IDT70V27 is a fast Dual-Port 32K x 16 CMOS Static RAM with

an additional 8 address locations dedicated to binary semaphore flags.
These flags allow either processor on the left or right side of the Dual-Port
RAM to claim a privilege over the other processor for functions defined by
the system designer's software. As an example, the semaphore can be
used by one processor to inhibit the other from accessing a portion of the
Dual-Port RAM or any other shared resource.

The Dual-Port RAM features a fast access time, and both ports are

completely independent of each other. This means that the activity on the
left port in no way slows the access time of the right port. Both ports are
identical in function to standard CMOS Static RAM and can be read from,
or written to, at the same time with the only possible conflict arising from the
simultaneous writing of, or a simultaneous READ/WRITE of, a non-
semaphore location. Semaphores are protected against such ambiguous
situations and may be used by the system program to avoid any conflicts
in the non-semaphore portion of the Dual-Port RAM. These devices have
an automatic power-down feature controlled by

CE the Dual-Port RAM

enable, and

SEM, the semaphore enable. The CE and SEM pins control

on-chip power down circuitry that permits the respective port to go into
standby mode when not selected. This is the condition which is shown in
Truth Table II where

and

SEM are both HIGH.

Systems which can best use the IDT70V27 contain multiple processors

or controllers and are typically very high-speed systems which are
software controlled or software intensive. These systems can benefit from
a performance increase offered by the IDT70V27's hardware sema-
phores, which provide a lockout mechanism without requiring complex
programming.

Software handshaking between processors offers the maximum in

system flexibility by permitting shared resources to be allocated in varying
configurations. The IDT70V27 does not use its semaphore flags to control
any resources through hardware, thus allowing the system designer total
flexibility in system architecture.

An advantage of using semaphores rather than the more common

methods of hardware arbitration is that wait states are never incurred in
either processor. This can prove to be a major advantage in very high-
speed systems.

How the Semaphore Flags Work

The semaphore logic is a set of eight latches which are independent

of the Dual-Port RAM. These latches can be used to pass a flag, or token,
from one port to the other to indicate that a shared resource is in use. The
semaphores provide a hardware assist for a use assignment method
called "Token Passing Allocation." In this method, the state of a semaphore
latch is used as a token indicating that shared resource is in use. If the left
processor wants to use this resource, it requests the token by setting the
latch. This processor then verifies its success in setting the latch by reading
it. If it was successful, it proceeds to assume control over the shared
resource. If it was not successful in setting the latch, it determines that the
right side processor has set the latch first, has the token and is using the
shared resource. The left processor can then either repeatedly request
that semaphore's status or remove its request for that semaphore to perform
another task and occasionally attempt again to gain control of the token via
the set and test sequence. Once the right side has relinquished the token,
the left side should succeed in gaining control.

The semaphore flags are active low. A token is requested by writing

a zero into a semaphore latch and is released when the same side writes

3603 drw 17

MASTER
Dual Port RAM

BUSY

MASTER
Dual Port RAM

BUSY

SLAVE
Dual Port RAM

BUSY

SLAVE
Dual Port RAM

BUSY

Commercial and Industrial Temperature Range

IDT 70V27S/L
High-Speed 3.3V 32K x 16 Dual-Port Static RAM

3603 drw 18

WRITE

SEMAPHORE

REQUEST FLIP FLOP

SEMAPHORE

REQUEST FLIP FLOP

L PORT

R PORT

SEMAPHORE

READ

SEMAPHORE
READ

a one to that latch.

The eight semaphore flags reside within the IDT70V27 in a separate

memory space from the Dual-Port RAM. This address space is accessed
by placing a low input on the

SEM pin (which acts as a chip select for the

semaphore flags) and using the other control pins (Address,

OE, and

W) as they would be used in accessing a standard Static RAM. Each

of the flags has a unique address which can be accessed by either side
through address pins A

. When accessing the semaphores, none of

the other address pins has any effect.

When writing to a semaphore, only data pin D

is used. If a low level

is written into an unused semaphore location, that flag will be set to a zero
on that side and a one on the other side (see Table VI). That semaphore
can now only be modified by the side showing the zero. When a one is
written into the same location from the same side, the flag will be set to a
one for both sides (unless a semaphore request from the other side is
pending) and then can be written to by both sides. The fact that the side
which is able to write a zero into a semaphore subsequently locks out writes
from the other side is what makes semaphore flags useful in interprocessor
communications. (A thorough discussion on the use of this feature follows
shortly.) A zero written into the same location from the other side will be
stored in the semaphore request latch for that side until the semaphore is
freed by the first side.

When a semaphore flag is read, its value is spread into all data bits so

that a flag that is a one reads as a one in all data bits and a flag containing
a zero reads as all zeros. The read value is latched into one side's output
register when that side's semaphore select (

SEM) and output enable (OE)

signals go active. This serves to disallow the semaphore from changing
state in the middle of a read cycle due to a write cycle from the other side.
Because of this latch, a repeated read of a semaphore in a test loop must
cause either signal (

SEM or OE) to go inactive or the output will never

change.

A sequence WRITE/READ must be used by the semaphore in order

to guarantee that no system level contention will occur. A processor
requests access to shared resources by attempting to write a zero into a
semaphore location. If the semaphore is already in use, the semaphore
request latch will contain a zero, yet the semaphore flag will appear as a
one, a fact which the processor will verify by the subsequent read (see
Table VI). As an example, assume a processor writes a zero to the left port
at a free semaphore location. On a subsequent read, the processor will
verify that it has written successfully to that location and will assume control
over the resource in question. Meanwhile, if a processor on the right side
attempts to write a zero to the same semaphore flag it will fail, as will be
verified by the fact that a one will be read from that semaphore on the right
side during the subsequent read. Had a sequence of READ/WRITE been
used instead, system contention problems could have occurred during the

gap between the read and write cycles.

It is important to note that a failed semaphore request must be followed

by either repeated reads or by writing a one into the same location. The
reason for this is easily understood by looking at the simple logic diagram
of the semaphore flag in Figure 4. Two semaphore request latches feed

Figure 4. IDT70V27 Semaphore Logic

into a semaphore flag. Whichever latch is first to present a zero to the
semaphore flag will force its side of the semaphore flag low and the other
side high. This condition will continue until a one is written to the same
semaphore request latch. Should the other side's semaphore request latch
have been written to a zero in the meantime, the semaphore flag will flip
over to the other side as soon as a one is written into the first side's request
latch. The second side's flag will now stay low until its semaphore request
latch is written to a one. From this it is easy to understand that, if a semaphore
is requested and the processor which requested it no longer needs the
resource, the entire system can hang up until a one is written into that
semaphore request latch.

The critical case of semaphore timing is when both sides request a

single token by attempting to write a zero into it at the same time. The
semaphore logic is specially designed to resolve this problem. If simulta-
neous requests are made, the logic guarantees that only one side receives
the token. If one side is earlier than the other in making the request, the first
side to make the request will receive the token. If both requests arrive at
the same time, the assignment will be arbitrarily made to one port or the
other.

One caution that should be noted when using semaphores is that

semaphores alone do not guarantee that access to a resource is secure.
As with any powerful programming technique, if semaphores are misused
or misinterpreted, a software error can easily happen.

Initialization of the semaphores is not automatic and must be handled

via the initialization program at power-up. Since any semaphore request
flag which contains a zero must be reset to a one, all semaphores on both
sides should have a one written into them at initialization from both sides
to assure that they will be free when needed.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70V27

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70V27