ChipFind - документация

Электронный компонент: 70V3319

Скачать:  PDF   ZIP
2002 Integrated Device Technology, Inc.
AUGUST 2002
DSC 5623/6
1
.unctional Block Diagram
.eatures:
x
True Dual-Port memory cells which allow simultaneous
access of the same memory location
x
High-speed data access
Commercial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)
Industrial: 4.2ns (133MHz) (max.)
x
Selectable Pipelined or Flow-Through output mode
Due to limited pin count PL/
FT
option is not supported
on the 128-pin TQFP package. Device is pipelined
outputs only on each port.
x
Counter enable and repeat features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
6ns cycle time, 166MHz operation (6Gbps bandwidth)
Fast 3.6ns clock to data out
1.7ns setup to clock and 0.5ns hold on all control, data, and
address inputs @ 166MHz
Data input, address, byte enable and control registers
Self-timed write allows fast cycle time
x
Separate byte controls for multiplexed bus and bus
matching compatibility
x
Dual Cycle Deselect (DCD) for Pipelined Output mode
x
LVTTL- compatible, single 3.3V (150mV) power supply
for core
x
LVTTL compatible, selectable 3.3V (150mV) or 2.5V
(100mV) power supply for I/Os and control signals on
each port
x
Industrial temperature range (-40C to +85C) is
available at 133MHz.
x
Available in a 128-pin Thin Quad Flatpack, 208-pin fine
pitch Ball Grid Array, and 256-pin Ball
Grid Array
x
Supports JTAG features compliant to IEEE 1149.1
Due to limited pin count, JTAG is not supported on the
128-pin TQFP package.
HIGH-SPEED 3.3V
256/128K x 18
SYNCHRONOUS
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE
IDT70V3319/99S
Dout0-8_L
B
W
0
L
B
W
1
L
Din_L
OE
L
UB
L
LB
L
R/
W
L
CE
0L
CE
1L
ab
FT
/PIPE
L
0/1
1b 0b 1a 0a
1
0
1/0
0b 1b
0a 1a
a
b
FT
/PIPE
L
1/0
REPEAT
R
A
17R(1)
A
0R
CNTEN
R
ADS
R
Dout0-8_R
Dout9-17_R
I/O
0R
- I/O
17R
Din_R
ADDR_R
OE
R
UB
R
LB
R
R/
W
R
CE
0R
CE
1R
FT
/PIPE
R
CLK
R
,
Counter/
Address
Reg.
B
W
1
R
B
W
0
R
FT
/PIPE
R
Counter/
Address
Reg.
CNTEN
L
ADS
L
REPEAT
L
Dout9-17_L
I/O
0L
- I/O
17L
A
17L(1)
A
0L
ADDR_L
5623 tbl 01
256K x 18
MEMORY
ARRAY
CLK
L
,
JTAG
TCK
TRST
TMS
TDO
TDI
ba
0/1
0b 1b
0a 1a
1
0
1/0
1b 0b
1a 0a
a
b
1/0
NOTE:
1. A
17
is a NC for IDT70V3399.
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
2
Description:
The IDT70V3319/99 is a high-speed 256/128K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3319/99 has been optimized for applications having unidirectional
or bidirectional data flow in bursts. An automatic power down feature,
controlled by
CE
0
and CE
1,
permits the on-chip circuitry of each port to
enter a very low standby power mode.
The 70V3319/99 can support an operating voltage of either 3.3V or
2.5V on one or both ports, controllable by the OPT pins. The power supply
for the core of the device (V
DD
) remains at 3.3V.
Pin Configuration
(1,2,3,4,5)
NOTES:
1. A
17
is a NC for IDT70V3399.
2. All V
DD
pins must be connected to 3.3V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
17
16
15
14
12
13
10
9
8
7
6
5
4
3
2
1
11
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
U
I/O
9L
NC
V
SS
TDO
A
2L
A
4L
CLK
L
A
8L
A
12L
A
16L
NC
OPT
L
NC
V
SS
NC
TDI
A
1L
A
5L
A
9L
A
13L
A
17L(1)
V
DDQL
I/O
9R
V
DDQR
PIPE/
FT
L
A
3L
A
6L
NC
A
10L
A
14L
NC
NC
NC
V
SS
I/O
10L
NC
NC
I/O
11L
NC
V
DDQR
I/O
10R
NC
I/O
11R
NC
V
SS
V
DD
NC
I/O
12L
V
DD
V
SS
V
SS
NC
V
SS
I/O
12R
REPEAT
R
NC
I/O
14L
V
DDQR
V
DDQL
I/O
15R
NC
V
SS
NC
NC
A
15L
A
11L
A
7L
A
0L
NC
I/O
7L
NC
I/O
6L
I/O
8R
UB
L
NC
I/O
8L
V
DDQL
CE
0L
CE
1L
LB
L
REPEAT
L
OE
L
I/O
0L
I/O
2L
I/O
1R
ADS
R
R/
W
R
NC
I/O
16R
I/O
15L
TRST
A
13R
A
12R
NC
V
DD
CLK
R
I/O
0R
NC
NC
NC
NC
A
17R(1)
TCK
TMS
A
5R
A
9R
CE
0R
CE
1R
V
DD
V
SS
NC
NC
NC
A
16R
NC
NC
A
14R
A
10R
UB
R
V
SS
V
DDQL
I/O
1L
I/O
2R
NC
NC
NC
A
15R
A
11R
A
7R
LB
R
OE
R
V
SS
NC
V
DDQL
OPT
R
NC
70V3319/99BF
BF-208
(6)
208-Pin fpBGA
Top View
(7)
5623 drw 02c
I/O
14R
V
DDQL
V
SS
V
DDQR
NC
NC
NC
NC
I/O
7R
NC
R/
W
L
NC
ADS
L
V
DDQL
I/O
13R
CNTEN
L
V
SS
I/O
13L
V
SS
I/O
16L
V
DDQR
V
SS
I/O
17R
I/O
17L
V
DDQL
V
SS
PIPE/
FT
R
A
8R
CNTEN
R
A
6R
A
3R
A
1R
A
2R
A
0R
I/O
3L
I/O
4L
A
4R
V
DD
V
SS
V
SS
V
SS
V
DDQR
V
DDQL
V
SS
V
DDQR
V
SS
I/O
3R
I/O
4R
V
SS
V
DDQR
V
SS
V
DD
V
SS
V
DD
V
SS
I/O
5R
I/O
5L
V
DDQR
I/O
6R
V
SS
V
SS
V
DDQL
V
DD
V
SS
V
DDQR
V
SS
V
SS
V
DD
V
DD
V
SS
V
DD
V
SS
08/01/02
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
3
Pin Configuration
(1,2,3,4,5)
(con't.)
NOTES:
1. A
17
is a NC for IDT70V3399.
2. All V
DD
pins must be connected to 3.3V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is
set to V
IL
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
70V3319/99BC
BC-256
(6)
256-Pin BGA
Top View
(7)
E16
I/O
7R
D16
I/O
8R
C16
I/O
8L
B16
NC
A16
NC
A15
NC
B15
NC
C15
NC
D15
NC
E15
I/O
7L
E14
NC
D14
NC
D13
V
DD
C12
A
6L
C14
OPT
L
B14
V
DD
A14
A
0L
A12
A
5L
B12
A
4L
C11
ADS
L
D12
V
DDQR
D11
V
DDQR
C10
CLK
L
B11
REPEAT
L
A11
CNTEN
L
D8
V
DDQR
C8
NC
A9
CE
1L
D9
V
DDQL
C9
LB
L
B9
CE
0L
D10
V
DDQL
C7
A
7L
B8
UB
L
A8
NC
B13
A
1L
A13
A
2L
A10
OE
L
D7
V
DDQR
B7
A
9L
A7
A
8L
B6
A
12L
C6
A
10L
D6
V
DDQL
A5
A
14L
B5
A
15L
C5
A
13L
D5
V
DDQL
A4
B4
NC
C4
A
16L
D4
PIPE/
FT
L
A3
NC
B3
TDO
C3
V
SS
D3
NC
D2
I/O
9R
C2
I/O
9L
B2
NC
A2
TDI
A1
NC
B1
NC
C1
NC
D1
NC
E1
I/O
10R
E2
I/O
10L
E3
NC
E4
V
DDQL
F1
I/O
11L
F2
NC
F4
V
DDQL
G1
NC
G2
NC
G3
I/O
12L
G4
V
DDQR
H1
NC
H2
I/O
12R
H3
NC
H4
V
DDQR
J1
I/O
13L
J2
I/O
14R
J3
I/O
13R
J4
V
DDQL
K1
NC
K2
NC
K3
I/O
14L
K4
V
DDQL
L1
I/O
15L
L2
NC
L3
I/O
15R
L4
V
DDQR
M1
I/O
16R
M2
I/O
16L
M3
NC
M4
V
DDQR
N1
NC
N2
I/O
17R
N3
NC
N4
PIPE/
FT
R
P1
NC
P2
I/O
17L
P3
TMS
P4
A
16R
R1
NC
R2
NC
R3
TRST
R4
NC
T1
NC
T2
TCK
T3
NC
T4
A
17R
(1)
P5
A
13R
R5
A
15R
P12
A
6R
P8
NC
P9
LB
R
R8
UB
R
T8
NC
P10
CLK
R
T11
CNTEN
R
P11
ADS
R
R12
A
4R
T12
A
5R
P13
A
3R
P7
A
7R
R13
A
1R
T13
A
2R
R6
A
12R
T5
A
14R
T14
A
0R
R14
OPT
R
P14
NC
P15
NC
R15
NC
T15
NC
T16
NC
R16
NC
P16
I/O
0L
N16
NC
N15
I/O
0R
N14
NC
M16
NC
M15
I/O
1L
M14
I/O
1R
L16
I/O
2R
L15
NC
L14
I/O
2L
K16
I/O
3L
K15
NC
K14
NC
J16
I/O
4L
J15
I/O
3R
J14
I/O
4R
H16
I/O
5R
H15
NC
H14
NC
G16
NC
G15
NC
G14
I/O
5L
F16
I/O
6L
F14
I/O
6R
F15
NC
R9
CE
0R
R11
REPEAT
R
T6
A
11R
T9
CE
1R
A6
A
11L
B10
R/
W
L
C13
A
3L
P6
A
10R
R10
R/
W
R
R7
A
9R
T10
OE
R
T7
A
8R
,
E5
V
DD
E6
V
DD
E7
V
SS
E8
V
SS
E9
V
SS
E10
V
SS
E11
V
DD
E12
V
DD
E13
V
DDQR
F5
V
DD
F6
V
SS
F8
V
SS
F9
V
SS
F10
V
SS
F12
V
DD
F13
V
DDQR
G5
V
SS
G6
V
SS
G7
V
SS
G8
V
SS
G9
V
SS
G10
V
SS
G11
V
SS
G12
V
SS
G13
V
DDQL
H5
V
SS
H6
V
SS
H7
V
SS
H8
V
SS
H9
V
SS
H10
V
SS
H11
V
SS
H12
V
SS
H13
V
DDQL
J5
V
SS
J6
V
SS
J7
V
SS
J8
V
SS
J9
V
SS
J10
V
SS
J11
V
SS
J12
V
SS
J13
V
DDQR
K5
V
SS
K6
V
SS
K7
V
SS
K8
V
SS
L5
V
DD
L6
V
SS
L7
V
SS
L8
V
SS
M5
V
DD
M6
V
DD
M7
V
SS
M8
V
SS
N5
V
DDQR
N6
V
DDQR
N7
V
DDQL
N8
V
DDQL
K9
V
SS
K10
V
SS
K11
V
SS
K12
V
SS
L9
V
SS
L10
V
SS
L11
V
SS
L12
V
DD
M9
V
SS
M10
V
SS
M11
V
DD
M12
V
DD
N9
V
DDQR
N10
V
DDQR
N11
V
DDQL
N12
V
DDQL
K13
V
DDQR
L13
V
DDQL
M13
V
DDQL
N13
V
DD
F7
V
SS
F11
V
SS
5623 drw 02d
,
F3
I/O
11R
08/01/02
A
17L
(1)
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
4
Pin Configuration
(1,2,3,4,5,8,9)
(con't.)
NOTES:
1. A
17
is a NC for IDT70V3399.
2. All V
DD
pins must be connected to 3.3V power supply.
3. All V
DDQ
pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V
IH
(3.3V), and 2.5V if OPT pin for that port is set to V
IL
(0V).
4. All V
SS
pins must be connected to ground supply.
5. Package body is approximately 14mm x 20mm x 1.4mm.
6. This package code is used to reference the package diagram.
7. This text does not indicate orientation of the actual part-marking.
8. PIPE/
FT option in PK-128 is not supported due to limitation in pin count. Device is pipelined outputs only on each port.
9. Due to the limited pin count, JTAG is not supported in the PK-128 package.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
A
14L
A
15L
A
16L
A
17L(1)
IO
9L
IO
9R
V
DDQL
V
SS
IO
10L
IO
10R
V
DDQR
V
SS
IO
11L
IO
11R
IO
12L
IO
12R
V
DD
V
DD
V
SS
V
SS
IO
13R
IO
13L
IO
14R
IO
14L
IO
15R
IO
15L
V
DDQL
V
SS
IO
16R
IO
16L
V
DDQR
V
SS
IO
17R
IO
17L
A
17R(1)
A
16R
A
15R
A
14R
A
1R
A
0R
OPT
R
IO
0L
IO
0R
V
DDQR
V
SS
IO
1L
IO
1R
V
DDQL
V
SS
IO
2L
IO
2R
IO
3L
IO
3R
IO
4L
IO
4R
V
SS
V
SS
V
DD
V
DD
IO
5L
IO
5R
V
DDQR
V
SS
IO
7R
IO
7L
V
DDQL
V
SS
V
SS
IO
8R
IO
8L
V
SS
OPT
L
A
0L
A
1L
IO
6R
IO
6L
70V3319/99PRF
PK-128
(6)
128-Pin TQFP
Top View
(7)
5623 drw 02a
A
1
3
L
A
1
2
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
U
B
L
L
B
L
C
E
1
L
C
E
0
L
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
L
O
E
L
R
/
W
L
A
D
S
L
C
N
T
E
N
L
R
E
P
E
A
T
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
3
R
A
1
2
R
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
U
B
R
L
B
R
C
E
1
R
C
E
0
R
V
D
D
V
D
D
V
S
S
V
S
S
C
L
K
R
O
E
R
R
/
W
R
A
D
S
R
C
N
T
E
N
R
R
E
P
E
A
T
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
.
08/06/02
6.42
IDT70V3319/99S
High-Speed 3.3V 256/128K x 18 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
5
Pin Names
Left Port
Right Port
Names
CE
0L
,
CE
1L
CE
0R
,
CE
1R
Chip Enables
(6)
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
17L
(1)
A
0R
- A
17R
(1)
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
PIPE/
FT
L
(5)
PIPE/
FT
R
(5)
Pipeline/Flow-Through
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
REPEAT
L
REPEAT
R
Counter Repeat
(4)
UB
L
UB
R
Upper Byte Enable (I/O
9
-I/O
17
)
(6)
LB
L
LB
R
Lower Byte Enable (I/O
0
-I/O
8
)
(6)
V
DDQL
V
DDQR
Power (I/O Bus) (3.3V or 2.5V)
(2)
OPT
L
OPT
R
Option for selecting V
DDQX
(2,3)
V
DD
Power (3.3V)
(2)
V
SS
Ground (0V)
TDI
Test Data Input
TDO
Test Data Output
TCK
Test Logic Clock (10MHz)
TMS
Test Mode Select
TRST
Reset (Initialize TAP Controller)
5623 tbl 01
1. A
17
is a NC for IDT70V3399.
2. V
DD
, OPT
X
, and V
DDQX
must be set to appropriate operating levels prior to
applying inputs on the I/Os and controls for that port.
3. OPT
X
selects the operating voltage levels for the I/Os and controls on that port.
If OPT
X
is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V
levels and V
DDQX
must be supplied at 3.3V. If OPT
X
is set to VIL (0V), then that
port's I/Os and address controls will operate at 2.5V levels and V
DDQX
must be
supplied at 2.5V. The OPT pins are independent of one another--both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.
4. When
REPEAT
X
is asserted, the counter will reset to the last valid address loaded
via
ADS
X
.
5. PIPE/
FT option in PK-128 package is not supported due to limitation in pin count.
Device is pipelined output mode only on each port.
6. Chip Enables and Byte Enables are double buffered when PL/
FT = V
IH
, i.e., the
signals take two cycles to deselect.
NOTES: