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Электронный компонент: 70V34

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2002 Integrated Device Technology, Inc.
JULY 2002
DSC-5624/3
1
PRELIMINARY
IDT70V35/34S/L
HIGH-SPEED 3.3V
8/4K x 18 DUAL-PORT
STATIC RAM
x
x
x
x
x
IDT70V35/34 easily expands data bus width to 36 bits or
more using the Master/Slave select when cascading more
than one device
x
x
x
x
x
M/
S = V
IH
for
BUSY output flag on Master
M/
S = V
IL
for
BUSY input on Slave
x
x
x
x
x
BUSY and Interrupt Flag
x
x
x
x
x
On-chip port arbitration logic
x
x
x
x
x
Full on-chip hardware support of semaphore signaling
between ports
x
x
x
x
x
Fully asynchronous operation from either port
x
x
x
x
x
LVTTL-compatible, single 3.3V (0.3V) power supply
x
x
x
x
x
Available in a 100-pin TQFP
x
x
x
x
x
Industrial temperature range (-40C to +85C) is available
for selected speeds
.unctional Block Diagram
NOTES:
1. A
12
is a NC for IDT70V34.
2. (MASTER):
BUSY is output; (SLAVE): BUSY is input.
3.
BUSY outputs and INT outputs are non-tri-stated push-pull.
.eatures
x
x
x
x
x
True Dual-Ported memory cells which allow simultaneous
reads of the same memory location
x
x
x
x
x
High-speed access
Commercial: 15/20/25ns (max.)
Industrial: 20ns
x
x
x
x
x
Low-power operation
IDT70V35/34S
Active: 430mW (typ.)
Standby: 3.3mW (typ.)
IDT70V35/34L
Active: 415mW (typ.)
Standby: 660
W (typ.)
x
x
x
x
x
Separate upper-byte and lower-byte control for multiplexed
bus compatibility
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
INTERRUPT
SEMAPHORE
LOGIC
Address
Decoder
I/O
Control
R/
W
L
BUSY
L
A
12L
(1)
A
0L
5624 drw 01
UB
L
LB
L
CE
L
OE
L
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
CE
L
OE
L
R/
W
L
SEM
L
INT
L
M/
S
R/
W
R
BUSY
R
UB
R
LB
R
CE
R
OE
R
I/O
9R
-I/O
17R
I/O
0R
-I/O
8R
A
12R
(1)
A
0R
R/
W
R
SEM
R
INT
R
CE
R
OE
R
(3)
(2,3)
(2,3)
(3)
13
13
,
6.42
IDT70V35/34S/L
PRELIMINARY
High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description
The IDT70V35/34 is a high-speed 8/4K x 18 Dual-Port Static RAM.
The IDT70V35/34 is designed to be used as a stand-alone Dual-Port RAM
or as a combination MASTER/SLAVE Dual-Port RAM for 36-bit or wider
memory system applications results in full-speed, error-free operation
without the need for additional discrete logic.
This device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature controlled by
CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 430mW of power.
The IDT70V35/34 is packaged in a plastic 100-pin Thin Quad
Flatpack.
Pin Configurations
(1,2,3,4)
NOTES:
1. A
12
is a NC for IDT70V34.
2. All V
CC
pins must be connected to power supply.
3. All GND pins must be connected to ground.
4. PN100-1 package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part marking.
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V35/34PF
PN100-1
(5)
100-Pin TQFP
Top View
(6)
N/C
N/C
I/O
8L
I/O
17L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
GND
I/O
15L
I/O
16L
V
CC
GND
I/O
0R
I/O
1R
I/O
2R
I/O
3R
V
CC
I/O
4R
I/O
5R
I/O
6R
I/O
8R
I/O
17R
N/C
N/C
5624 drw 02
N/C
N/C
N/C
N/C
A
5L
A
4L
A
3L
A
2L
A
1L
A
0L
INT
L
GND
M/
S
BUSY
R
INT
R
A
0R
N/C
N/C
N/C
N/C
BUSY
L
A
1R
A
2R
A
3R
A
4R
I
/
O
1
0
L
I
/
O
9
L
I
/
O
7
L
I
/
O
6
L
I
/
O
5
L
I
/
O
4
L
I
/
O
3
L
I
/
O
2
L
G
N
D
I
/
O
1
L
I
/
O
0
L
O
E
L
V
C
C
R
/
W
L
S
E
M
L
C
E
L
U
B
L
L
B
L
A
1
1
L
A
1
0
L
A
9
L
A
8
L
A
7
L
A
6
L
I
/
O
7
R
I
/
O
9
R
I
/
O
1
0
R
I
/
O
1
1
R
I
/
O
1
2
R
I
/
O
1
3
R
I
/
O
1
4
R
I
/
O
1
5
R
G
N
D
I
/
O
1
6
R
O
E
R
R
/
W
R
S
E
M
R
C
E
R
U
B
R
L
B
R
G
N
D
A
1
1
R
A
1
0
R
A
9
R
A
8
R
A
7
R
A
6
R
A
5
R
A
1
2
L
(
1
)
A
1
2
R
(
1
)
,
07/02/02
6.42
IDT70V35/34S/L
PRELIMINARY
High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Truth Table I: Non-Contention Read/Write Control
Truth Table II: Semaphore Read/Write Control
(1)
NOTE:
1.
A
0L
-- A
12L
A
0R
-- A
12R
NOTE:
1. There are eight semaphore flags written to via I/O
0
and read from all of the I/O's (I/O
0
-I/O
17
). These eight semaphores are addressed by A
0
-A
2
.
Inputs
(1)
Outputs
Mode
CE
R/
W
OE
UB
LB
SEM
I/O
9-17
I/O
0-8
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power Down
X
X
X
H
H
H
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATA
IN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATA
IN
Write to Lower Byte Only
L
L
X
L
L
H
DATA
IN
DATA
IN
Write to Both Bytes
L
H
L
L
H
H
DATA
OUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATA
OUT
Read Lower Byte Only
L
H
L
L
L
H
DATA
OUT
DATA
OUT
Read Both Bytes
X
X
H
X
X
X
High-Z
High-Z
Outputs Disabled
5624 tbl 02
Inputs
Outputs
Mode
CE
R/
W
OE
UB
LB
SEM
I/O
9-17
I/O
0-8
H
H
L
X
X
L
DATA
OUT
DATA
OUT
Read Data in Semaphore Flag
X
H
L
H
H
L
DATA
OUT
DATA
OUT
Read Data in Semaphore Flag
H
X
X
X
L
DATA
IN
DATA
IN
Write I/O
0
into Semaphore Flag
X
X
H
H
L
DATA
IN
DATA
IN
Write I/O
0
into Semaphore Flag
L
X
X
L
X
L
____
____
Not Allowed
L
X
X
X
L
L
____
____
Not Allowed
5624 tbl 03
Pin Names
Left Port
Right Port
Names
CE
L
CE
R
Chip Enable
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
12L
(1)
A
0R
- A
12R
(1)
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
SEM
L
SEM
R
Semaphore Enable
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lower Byte Select
INT
L
INT
R
Interrupt Flag
BUSY
L
BUSY
R
Busy Flag
M/S
Master or Slave Select
V
CC
Power (3.3V)
GND
Ground (0V)
5624 tbl 01
1. A
12
is a NC for IDT70V34.
6.42
IDT70V35/34S/L
PRELIMINARY
High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Absolute Maximum Ratings
(1)
Maximum Operating Temperature
and Supply Voltage
(1)
Capacitance
(1)
(T
A
= +25C, f = 1.0MHz)
Recommended DC Operating
Conditions
NOTES:
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.
V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV references the interpolated capacitance when the input and output
signals switch from 0V to 3V or from 3V to 0V.
NOTE:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1.
V
IL
> -1.5V for pulse width less than 10ns.
2.
V
TERM
must not exceed Vcc + 0.3V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50
mA
5624 tbl 04
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
5624 tbl 05
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
CC
+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5624 tbl 06
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
5624 tbl 07
Symbol
Parameter
Test Conditions
70V35/34S
70V35/34L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Currentt
(1)
CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
5624 tbl 08
6.42
IDT70V35/34S/L
PRELIMINARY
High-Speed 8/4K x 18 Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1)
(V
CC
= 3.3V 0.3V)
NOTES:
1. 'X' in part number indicates power rating (S or L)
2. V
CC
= 3.3V, T
A
= +25C, and are not production tested. Icc dc
=
115mA (typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using "AC Test Conditions" of input levels of GND
to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
70V35/34X15
Com'l Only
70V35/34X20
Com'l
& Ind
70V35/34X25
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
(2)
Max.
Typ.
(2)
Max.
Typ.
(2)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L
S
L
150
140
215
185
140
130
200
175
130
125
190
165
mA
IND
S
L
____
____
____
____
140
130
225
195
____
____
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
R
and
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
COM'L
S
L
25
20
35
30
20
15
30
25
16
13
30
25
mA
MIL &
IND
S
L
____
____
____
____
20
15
45
40
____
____
____
____
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
COM'L
S
L
85
80
120
110
80
75
110
100
75
72
110
95
mA
MIL &
IND
S
L
____
____
____
____
80
75
130
115
____
____
____
____
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
-0.2V
COM'L
S
L
1.0
0.2
5
2.5
1.0
0.2
5
2.5
1.0
0.2
5
2.5
mA
MIL &
IND
S
L
____
____
____
____
1.0
0.2
15
5
____
____
____
____
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
-0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled,
f = f
MAX
(3)
COM'L
S
L
85
80
125
105
80
75
115
100
75
70
105
90
mA
MIL &
IND
S
L
____
____
____
____
80
75
130
115
____
____
____
____
5624 tbl 09
AC Test Conditions
Figure 1. AC Output Test Load
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1 and 2
5624 tbl 10
Figure 2. Output Test
Load
(For t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
5624 drw 03
590
30pF
435
3.3V
DATA
OUT
BUSY
INT
590
5pF*
435
3.3V
DATA
OUT
,
Timing of Power-Up Power-Down
CE
5624 drw 04
t
PU
I
CC
I
SB
t
PD
50%
50%
,