APRIL 2001

DSC 4831/8

Functional Block Diagram

Features:

True Dual-Port memory cells which allow simultaneous
access of the same memory location

High-speed clock to data access
Commercial: 4.2/5/6ns (max.)
Industrial: 5/6ns (max)

Pipelined output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
Fast 4.2ns clock to data out
1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

Data input, address, byte enable and control registers
Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus
matching compatibility

LVTTL- compatible, single 3.3V (±150mV) power supply for
core

LVTTL- compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is
available for selected speeds

Available in a 208-pin Plastic Quad Flatpack (PQFP),
208-ball fine-pitch Ball Grid Array, and 256-pin Ball
Grid Array

HIGH-SPEED 3.3V 16K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

IDT70V3569S

CNTRST

Counter/

Address

Reg.

13R

Counter/

Address

Reg.

CNTEN

ADS

CNTEN

ADS

CNTRST

Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R
Dout27-35_R

B
W
0
L

B
W
1
L

B
W
2
L

B
W
3
L

B
W
3
R

B
W
2
R

B
W
1
R

B
W
0
R

I/O

- I/O

35L

13L

I/O

- I/O

35R

Din_L

ADDR_L

Din_R

ADDR_R

4831 tbl 01

16K x 36

MEMORY

ARRAY

CLK

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V3569 is a high-speed 16K x 36 bit synchronous Dual-Port

RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times. With an input data register, the IDT70V3569 has been
optimized for applications having unidirectional or bidirectional data flow

in bursts. An automatic power down feature, controlled by

and CE

permits the on-chip circuitry of each port to enter a very low standby power
mode.

The 70V3569 can support an operating voltage of either 3.3V or

2.5V on one or both ports, controllable by the OPT pins. The power
supply for the core of the device (V

) remains at 3.3V.

Pin Configuration

(1,2,3,4)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

A17

B17

I/O

15R

C17

D17

I/O

14R

E16

E17

I/O

13L

D16

I/O

14L

C16

I/O

15L

B16

I/O

16L

A16

I/O

17L

A15

OPT

B15

DDQR

C15

I/O

16R

D15

DDQL

E15

I/O

13R

E14

I/O

12L

D14

I/O

17R

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

D12

D11

CNTRST

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

13L

11L

I/O

20L

I/O

18R

DDQR

I/O

21L

I/O

19R

I/O

20R

DDQL

I/O

22L

I/O

23L

I/O

22R

DDQR

I/O

21R

DDQL

I/O

23R

I/O

24L

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DDQR

I/O

25R

DDQL

I/O

28R

I/O

27R

I/O

29R

I/O

28L

DDQR

I/O

27L

DDQL

I/O

29L

I/O

30R

I/O

31L

I/O

31R

I/O

30L

I/O

32R

I/O

32L

DDQR

I/O

35R

I/O

33L

I/O

34R

I/O

33R

I/O

34L

DDQL

I/O

35L

11R

P12

CNTEN

U10

P10

T11

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

13R

U14

T14

R14

P14

I/O

P15

I/O

R15

DDQL

T15

I/O

U15

OPT

U16

I/O

U17

I/O

T16

T17

I/O

R17

DDQR

R16

I/O

P17

I/O

P16

N17

I/O

N16

I/O

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

I/O

M14

L17

I/O

L16

L15

I/O

L14

I/O

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

10R

H16

H15

H14

G17

I/O

11R

G16

I/O

10L

G15

DDQL

G14

I/O

F17

DDQR

F16

I/O

11L

F14

70V3569BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

F15

I/O

12R

R11

ADS

B10

C13

R10

T10

10R

4831 drw 02c

12L

18L

19L

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

70V3569BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

CNTRST

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

13L

DDQL

I/O

20L

I/O

19R

I/O

19L

I/O

18L

I/O

18R

I/O

20R

I/O

21R

I/O

21L

I/O

22L

DDQL

I/O

23L

I/O

22R

I/O

23R

DDQL

I/O

24R

I/O

24L

I/O

25L

DDQR

I/O

26L

I/O

25R

I/O

26R

DDQR

I/O

27L

I/O

28R

I/O

27R

DDQL

I/O

29R

I/O

29L

I/O

28L

DDQL

I/O

30L

I/O

31R

I/O

30R

DDQR

I/O

32R

I/O

32L

I/O

31L

DDQR

I/O

33L

I/O

34R

I/O

33R

I/O

35R

I/O

34L

I/O

35L

13R

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

T14

R14

OPT

P14

I/O

P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R11

CNTRST

11R

11L

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

4831 drw 02d

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

70V3569DR

DR-208

(5)

208-Pin PQFP

Top View

(6)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

I
/
O

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

I
/
O

4831 drw 02a

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST = V

3. OE is an asynchronous input signal.
4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table IRead/Write and Enable Control

(1,2,3,4)

Pin Names

Left Port

Right Port

Names

Chip Enables

R/W

Read/Write Enable

Output Enable

- A

13L

- A

13R

Address

I/O

- I/O

35L

I/O

- I/O

35R

Data Input/Output

CLK

Clock

ADS

Address Strobe Enable

CNTEN

Counter Enable

CNTRST

Counter Reset

- BE

Byte Enables (9-bit bytes)

DDQL

DDQR

Power (I/O Bus)

(3.3V or 2.5V)

(1)

OPT

Option for selection V

DDQX

(1,2)

Power

(3.3V)

(1)

Ground

(0V)

4831 tbl 01

CLK

Byte 3

I/O

27-35

Byte 2

I/O

18-26

Byte 1
I/O

9-17

Byte 0

I/O

0-8

MODE

High-Z

DeselectedPower Down

High-Z

DeselectedPower Down

High-Z

All Bytes Deselected

High-Z

Write to Byte 0 Only

High-Z

Write to Byte 1 Only

High-Z

Write to Byte 2 Only

High-Z

Write to Byte 3 Only

High-Z

Write to Lower 2 Bytes Only

High-Z

Write to Upper 2 bytes Only

Write to All Bytes

High-Z

OUT

Read Byte 0 Only

High-Z

OUT

High-Z

Read Byte 1 Only

High-Z

OUT

High-Z

Read Byte 2 Only

OUT

High-Z

Read Byte 3 Only

High-Z

OUT

Read Lower 2 Bytes Only

OUT

High-Z

Read Upper 2 Bytes Only

OUT

Read All Bytes

High-Z

Outputs Disabled

4831 tbl 02

NOTES:
1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and controls will operate at 2.5V levels and V

DDQX

must be supplied

at 2.5V. The OPT pins are independent of one another--both ports can operate
at 3.3V levels, both can operate at 2.5V levels, or either can operate at 3.3V
with the other at 2.5V.

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

(1,2)

Recommended DC Operating

Conditions with V

DDQ

at 2.5V

Absolute Maximum Ratings

(1)

Truth Table IIAddress Counter Control

(1,2)

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/

W, CE

, CE

BEn and OE.

3. Outputs are in Pipelined mode: the data out will be delayed by one cycle.
4.

ADS and CNTRST are independent of all other memory control signals including CE

, CE

and

BEn

5. The address counter advances if

CNTEN = V

on the rising edge of CLK, regardless of all other memory control signals including

, CE

BEn.

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 150mV for more than 25% of the cycle time or

4ns maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 150mV.

NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

2. This is the parameter T

. This is the "instant on" case temperature.

Address

Previous

Address

Addr
Used

CLK

(6)

ADS

CNTEN

CNTRST

I/O

(3)

MODE

(4)

I/O

(0)

Counter Reset to Address 0

(4)

I/O

(n)

External Address Used

I/O

(p)

External Address Blocked--Counter disabled (Ap reused)

Ap + 1

(5)

I/O

(p+1)

Counter Enabled--Internal Address generation

4831 tbl 03

Grade

Ambient

Temperature

GND

Commercial

C to +70

3.3V

150mV

Industrial

-40

C to +85

3.3V

150mV

4831 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

3.15

3.3

3.45

DDQ

I/O Supply Voltage

(3)

2.375

2.5

2.625

Ground

Input High Voltage

(3)

(Address & Control Inputs)

1.7

____

DDQ

+ 125mV

(2)

Input High Voltage - I/O

(3)

1.7

____

DDQ

+ 125mV

(2)

Input Low Voltage

-0.3

(1)

____

0.7

4831 tbl 05a

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage
with Respect to

GND

-0.5 to +4.6

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-65 to +150

OUT

DC Output Current

4831 tbl 06

NOTES:
1. V

IL >

-1.5V for pulse width less than 10 ns.

2. V

TERM

must not exceed V

DDQ

+ 125mV.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V

(0V), and V

DDQX

for that port must be

supplied as indicated above.

NOTES:
1. V

IL >

-1.5V for pulse width less than 10 ns.

2. V

TERM

must not exceed V

DDQ

+ 150mV.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V

(3.3V), and V

DDQX

for that port must be

supplied as indicated above.

Recommended DC Operating

Conditions with V

DDQ

at 3.3V

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

3.15

3.3

3.45

DDQ

I/O Supply Voltage

(3)

3.15

3.3

3.45

Ground

Input High Voltage
(Address & Control Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

Input High Voltage - I/O

(3)

2.0

____

DDQ

+ 150mV

(2)

Input Low Voltage

-0.3

(1)

____

0.8

4831 tbl 05b

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V ± 150mV)

NOTE:
1. At V

< - 2.0V input leakages are undefined.

2. V

DDQ

is selectable (3.3V/2.5V) via OPT pins. Refer to p.4 for details.

Symbol

Parameter

Test Conditions

70V3569S

Unit

Min.

Max.

Input Leakage Current

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

µ A

Output Leakage Current

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

µ A

(3.3V)

Output Low Voltage

(2)

= +4mA, V

DDQ

= Min.

___

0.4

(3.3V)

Output High Voltage

(2)

= -4mA, V

DDQ

= Min.

2.4

___

(2.5V)

Output Low Voltage

(2)

= +2mA, V

DDQ

= Min.

___

0.4

(2.5V)

Output High Voltage

(2)

= -2mA, V

DDQ

= Min.

2.0

___

4831 tbl 08

NOTES:
1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

(1)

= +25°C, F = 1.0MH

) PQFP ONLY

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

10.5

4831 tbl 07

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(3)

= 3.3V ± 150mV)

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V

= 3.3V, T

= 25°C for Typ, and are not production tested. I

DD DC

(f=0)

= 120mA (Typ).

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

- 0.2V

"X" represents "L" for left port or "R" for right port.

70V3569S4

Com 'l Only

70V3569S5

Com 'l

& Ind

70V3569S6

Com 'l

& Ind

Sym bol

Param eter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dynam ic Op e rating
Curre nt (Bo th
P o rts A ctive )

and

= V

Outp uts Disab le d ,

f = f

MAX

(1)

COM 'L

375

460

285

360

245

310

m A

IND

____

285

415

245

360

SB1

S tand b y Curre nt
(Bo th P o rts - TTL
Le ve l Inp uts )

= V

f = f

MAX

(1)

COM 'L

145

190

105

145

125

m A

IND

____

105

175

150

SB2

S tand b y Curre nt
(One Po rt - TTL
Le ve l Inp uts )

"A"

= V

and

"B"

= V

(5)

A ctiv e P o rt Outp uts Dis ab le d ,
f= f

MAX

(1)

COM 'L

265

325

190

260

175

225

m A

IND

____

190

300

175

260

SB3

Full S tand b y Curre nt
(B o th P o rts - CM OS
Le ve l Inp uts )

B o th P o rts CE

and

> V

- 0.2V, V

> V

- 0.2V

o r V

< 0.2V , f = 0

(2)

COM 'L

m A

IND

____

SB4

Full S tand b y Curre nt
(One Po rt - CM OS
Le ve l Inp uts )

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

> V

- 0.2V o r V

< 0.2V, Ac tive

P o rt, Ou tp uts Disab le d , f = f

MAX

(1)

COM 'L

265

325

180

260

170

225

m A

IND

____

180

300

170

260

4831 tbl 09

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For t

CKLZ

, t

CKHZ

, t

OLZ

, and t

OHZ

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Input Pulse Levels (Address & Controls)

Input Pulse Levels (I/Os)

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V/GND to 2.35V

3ns

1.5V/1.25V

Figures 1, 2, and 3

4831 tbl 10

1.5V/1.25

4831 drw 03

10pF
(Tester)

DATA

OUT

4831 drw 04

590

5pF*

435

3.3V

DATA

OUT

833

5pF*

770

2.5V

DATA

OUT

-1

20.5

100

200

10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.

Capacitance (pF)

tCD

(Typical, ns)

4831 drw 05

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating

Temperature Range (Read and Write Cycle Timing)

(1,2)

= 3.3V ± 150mV, T

= 0°C to +70°C)

NOTES:
1. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (

OE).

2. These values are valid for either level of V

DDQ

(3.3V/2.5V). See page 4 for details on selecting the desired I/O voltage levels for each port.

70V3569S4

Com'l Only

70V3569S5

Com'l

& Ind

70V3569S6

Com'l

& Ind

Unit

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

CYC2

Clock Cycle Time (Pipelined)

7.5

____

CH2

Clock High Time (Pipelined)

____

CL2

Clock Low Time (Pipelined)

____

Clock Rise Time

____

Clock Fall Time

____

Address Setup Time

1.8

____

2.0

____

2.0

____

Address Hold Time

0.7

____

0.7

____

1.0

____

Chip Enable Setup Time

1.8

____

2.0

____

2.0

____

Chip Enable Hold Time

0.7

____

0.7

____

1.0

____

Byte Enable Setup Time

1.8

____

2.0

____

2.0

____

Byte Enable Hold Time

0.7

____

0.7

____

1.0

____

W Setup Time

1.8

____

2.0

____

2.0

____

W Hold Time

0.7

____

0.7

____

1.0

____

Input Data Setup Time

1.8

____

2.0

____

2.0

____

Input Data Hold Time

0.7

____

0.7

____

1.0

____

SAD

ADS Setup Time

1.8

____

2.0

____

2.0

____

HAD

ADS Hold Time

0.7

____

0.7

____

1.0

____

SCN

CNTEN Setup Time

1.8

____

2.0

____

2.0

____

HCN

CNTEN Hold Time

0.7

____

0.7

____

1.0

____

SRST

CNTRST Setup Time

1.8

____

2.0

____

2.0

____

HRST

CNTRST Hold Time

0.7

____

0.7

____

1.0

____

(1)

Output Enable to Data Valid

____

OLZ

Output Enable to Output Low-Z

____

OHZ

Output Enable to Output High-Z

4.5

CD2

Clock to Data Valid (Pipelined)

____

4.2

____

Data Output Hold After Clock High

____

CKHZ

Clock High to Output High-Z

4.5

1.5

CKLZ

Clock High to Output Low-Z

____

Port-to-Port Delay

Clock-to-Clock Offset

____

4831 tbl 11

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

0(B1)

ADDRESS

(B1)

CLK

4831 drw 07

DATA

OUT(B1)

CH2

CL2

CYC2

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CKHZ

CKLZ

CD2

An + 1

An + 2

An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(0-3)

(3)

DATA

OUT

CD2

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

4831 drw 06

(1)

(4)

(1 Latency)

(5)

Timing Waveform of a Multi-Device Pipelined Read

(1,2)

Timing Waveform of Read Cycle for Pipelined Operation

(2)

NOTES:
1.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

ADS = V

CNTEN and CNTRST = V

3. The output is disabled (High-Impedance state) by

= V

, CE

= V

following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If

was HIGH, then the appropriate Byte of DATA

OUT

for Qn + 2 would be disabled (High-Impedance state).

NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V3569 for this waveform,
and are setup for depth expansion in this example. ADDRESS

(B1)

= ADDRESS

(B2)

in this situation.

OE, and ADS = V

; CE

1(B1)

, CE

1(B2)

, R/

W, CNTEN, and CNTRST = V

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

CLK

ADDRESS

DATA

INL

CLK

ADDRESS

DATA

OUTR

(3)

CD2

MATCH

VALID

MATCH

VALID

4831 drw 08

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

4831 drw 09

Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ

NOP

READ

(3)

(1)

WRITE

(4)

Timing Waveform of Left Port Write to Pipelined

Right Port Read

(1,2)

NOTES:
1.

, and

ADS = V

; CE

CNTEN, and CNTRST = V

OE = V

for the Right Port, which is being read from.

OE = V

for the Left Port, which is being written to.

3. If t

< minimum specified, then data from right port read is not valid until following right port clock cycle (ie, time from write to valid read on opposite port will

be t

+ 2 t

CYC2

+ t

CD2

). If t

> minimum, then data from right port read is available on first right port clock cycle (ie, time from write to valid read on opposite

port will be t

+ t

CYC

+ t

CD2

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = V

)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.

, and

ADS = V

; CE

CNTEN, and CNTRST = V

. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

CLK

DATA

OUT

Qx - 1

(2)

Qn + 2

(2)

Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

4831 drw 11

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

DATA

Dn + 3

Dn + 2

CLK

4831 drw 10

DATA

OUT

Qn + 4

CH2

CL2

CYC2

CKLZ

CD2

OHZ

CD2

READ

WRITE

READ

(3)

(1)

(4)

Timing Waveform of Pipelined Read with Address Counter Advance

(1)

NOTES:
1.

OE, BE

= V

; CE

, R/

W, and CNTRST = V

2. If there is no address change via

ADS = V

(loading a new address) or

CNTEN = V

(advancing the address), i.e.

ADS = V

and

CNTEN = V

, then

the data output remains constant for subsequent clocks.

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.

, and

ADS = V

; CE

CNTEN, and CNTRST = V

3. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use

only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

CH2

CL2

CYC2

CLK

DATA

CNTRST

4831 drw 13

INTERNAL

(3)

ADDRESS

ADS

CNTEN

SRST

HRST

COUNTER

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

An + 1

An + 2

READ

ADDRESS n+1

DATA

OUT

An + 1

(4)

(5)

(6)

SAD

HAD

SCN

HCN

Timing Waveform of Write with Address Counter Advance

(1)

Timing Waveform of Counter Reset

(2)

NOTES:
1.

, and R/

W = V

; CE

and

CNTRST = V

2. CE

= V

; CE

= V

3. The "Internal Address" is equal to the "External Address" when

ADS = V

and equals the counter output when

ADS = V

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle: A

DDR

0 will be accessed. Extra cycles

are shown here simply for clarification.

CNTEN = V

advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1'Address is

written to during this cycle.

ADDRESS

CLK

DATA

Dn + 1

Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

4831 drw 12

INTERNAL

(3)

ADDRESS

(7)

An + 1

An + 2

An + 3

An + 4

Dn + 3

Dn + 4

SAD

HAD

WRITE

COUNTER HOLD

WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

SCN

HCN

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V3569 provides a true synchronous Dual-Port Static RAM

interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.

An asynchronous output enable is provided to ease asyn-

chronous bus interfacing. Counter enable inputs are also provided to stall
the operation of the address counters for fast interleaved
memory applications.

A HIGH on

or a LOW on CE

for one clock cycle will power down

the internal circuitry to reduce static power consumption. Multiple chip
enables allow easier banking of multiple IDT70V3569s for depth expan-
sion configurations. Two cycles are required with

LOW and CE

HIGH to re-activate the outputs.

4831 drw 14

IDT70V3569

Control Inputs

CLK,

ADS

CNTRST

CNTEN

Depth and Width Expansion

The IDT70V3569 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.

The IDT70V3569 can also be used in applications requiring expanded

width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 72-bits or wider.

Figure 4. Depth and Width Expansion with IDT70V3569

6.42

IDT70V3569S
High-Speed 16K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Power

Speed

Package

Process/

Temperature

Range

Blank
I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

208-pin fpBGA (BF-208)

208-pin PQFP (DR-208)

256-pin BGA (BC-256)

XXXXX

Device

Type

IDT

Speed in nanoseconds

4831 drw 15A

Standard Power

70V3569 576Kbit (16K x 36-Bit) Synchronous Dual-Port RAM

Commercial Only

Commercial & Industrial
Commercial & Industrial

Datasheet Document History

1/8/99:

Initial Public Release

3/12/99:

Added fpBGA package

4/28/99:

Fixed typo on page 10

6/8/99:

Changed drawing format
Page 2

Changed package body dimensions

Page 3

Fixed typo

6/15/99:

Page 5

Deleted note 6 for Table II

8/4/99:

Page 2

Fixed typographical error

Page 6

Improved power number

10/14/99:

Upgraded speed to 133MHz, added 2.5V I/O capability

10/19/99:

Page 4

Corrected I/O numbers in Truth Table I

11/12/99:

Replaced IDT logo

4/10/00:

Added new BGA packages, added full 2.5V interface capability

1/12/01:

Page 6

Updated Truth Table II

Increated storage temperature parameter
Clarified T

Parameter

Page 8

DC Electrical parameterschanged wording from "open" to "disabled"
Removed note 7 on DC Electrical Characteristics table

Removed Preliminary status

4/10/01:

Added Industrial Temperature Ranges and removed related notes

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-5166

831-754-4613

Santa Clara, CA 95054

fax: 408-492-8674

DualPortHelp@idt.com

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

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