JULY 2001

DSC 4830/13

Functional Block Diagram

Features:

True Dual-Port memory cells which allow simultaneous
access of the same memory location

High-speed clock to data access
Commercial: 4.2/5/6ns (max.)
Industrial: 5/6ns (max)

Pipelined output mode

Counter enable and reset features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
7.5ns cycle time, 133MHz operation (9.6 Gbps bandwidth)
Fast 4.2ns clock to data out
1.8ns setup to clock and 0.7ns hold on all control, data, and

address inputs @ 133MHz

Data input, address, byte enable and control registers
Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus
matching compatibility

LVTTL- compatible, single 3.3V (±150mV) power supply for
core

LVTTL compatible, selectable 3.3V (±150mV)/2.5V (±125mV)
power supply for I/Os and control signals on each port

Industrial temperature range (-40°C to +85°C) is
available for selected speeds

Available in a 208-pin Plastic Quad Flatpack (PQFP) and
208-pin fine pitch Ball Grid Array, and 256-pin Ball Grid
Array

HIGH-SPEED 3.3V 32K x 36
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

IDT70V3579S

CNTRST

Counter/

Address

Reg.

14R

Counter/

Address

Reg.

CNTEN

ADS

CNTEN

ADS

CNTRST

Dout0-8_L
Dout9-17_L
Dout18-26_L
Dout27-35_L

Dout0-8_R

Dout9-17_R

Dout18-26_R
Dout27-35_R

B
W
0
L

B
W
1
L

B
W
2
L

B
W
3
L

B
W
3
R

B
W
2
R

B
W
1
R

B
W
0
R

I/O

- I/O

35L

14L

I/O

- I/O

35R

Din_L

ADDR_L

Din_R

ADDR_R

4830 tbl 01

32K x 36

MEMORY

ARRAY

CLK

6.42

IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V3579 is a high-speed 32K x 36 bit synchronous Dual-

Port RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold
times. The timing latitude provided by this approach allows systems
to be designed with very short cycle times. With an input data register, the
IDT70V3579 has been optimized for applications having unidirectional or

bidirectional data flow in bursts. An automatic power down feature,
controlled by

and CE

permits the on-chip circuitry of each port to

enter a very low standby power mode.

The 70V3579 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for
the core of the device (V

) remains at 3.3V.

Pin Configuration

(1,2,3,4)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm, with 0.8mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

A17

B17

I/O

15R

C17

D17

I/O

14R

E16

E17

I/O

13L

D16

I/O

14L

C16

I/O

15L

B16

I/O

16L

A16

I/O

17L

A15

OPT

B15

DDQR

C15

I/O

16R

D15

DDQL

E15

I/O

13R

E14

I/O

12L

D14

I/O

17R

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

D12

D11

CNTRST

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

12L

13L

14L

11L

I/O

20L

I/O

18R

DDQR

I/O

21L

I/O

19R

18L

19L

I/O

20R

DDQL

I/O

22L

I/O

23L

I/O

22R

DDQR

I/O

21R

DDQL

I/O

23R

I/O

24L

I/O

26L

I/O

25L

I/O

24R

I/O

26R

DDQR

I/O

25R

DDQL

I/O

28R

I/O

27R

I/O

29R

I/O

28L

DDQR

I/O

27L

DDQL

I/O

29L

I/O

30R

I/O

31L

I/O

31R

I/O

30L

I/O

32R

I/O

32L

DDQR

I/O

35R

I/O

33L

I/O

34R

I/O

33R

I/O

34L

DDQL

I/O

35L

11R

P12

CNTEN

U10

P10

T11

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

13R

U14

T14

R14

P14

I/O

P15

I/O

R15

DDQL

T15

I/O

U15

OPT

U16

I/O

U17

I/O

T16

T17

I/O

R17

DDQR

R16

I/O

P17

I/O

P16

N17

I/O

N16

I/O

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

I/O

M14

L17

I/O

L16

L15

I/O

L14

I/O

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

10R

H16

H15

H14

G17

I/O

11R

G16

I/O

10L

G15

DDQL

G14

I/O

F17

DDQR

F16

I/O

11L

F14

70V3579BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

F15

I/O

12R

R11

ADS

14R

B10

C13

R10

T10

10R

4830 drw 02c

6.42

IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

70V3579BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

14R

D16

I/O

16R

C16

I/O

16L

B16

A16

A15

B15

I/O

17L

C15

I/O

17R

D15

I/O

15L

E15

I/O

14L

E14

I/O

13L

D14

I/O

15R

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

CNTRST

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

14L

13L

DDQL

I/O

20L

I/O

19R

I/O

19L

I/O

18L

I/O

18R

I/O

20R

I/O

21R

I/O

21L

I/O

22L

DDQL

I/O

23L

I/O

22R

I/O

23R

DDQL

I/O

24R

I/O

24L

I/O

25L

DDQR

I/O

26L

I/O

25R

I/O

26R

DDQR

I/O

27L

I/O

28R

I/O

27R

DDQL

I/O

29R

I/O

29L

I/O

28L

DDQL

I/O

30L

I/O

31R

I/O

30R

DDQR

I/O

32R

I/O

32L

I/O

31L

DDQR

I/O

33L

I/O

34R

I/O

33R

I/O

35R

I/O

34L

I/O

35L

13R

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

14R

T14

R14

OPT

P14

I/O

P15

I/O

R15

T15

T16

R16

P16

I/O

N16

I/O

N15

I/O

N14

I/O

M16

I/O

M15

I/O

M14

I/O

L16

I/O

L15

I/O

L14

I/O

K16

I/O

K15

I/O

K14

I/O

J16

I/O

J15

I/O

J14

I/O

H16

I/O

10R

H15

H14

I/O

G16

I/O

11R

G15

I/O

11L

G14

I/O

10L

F16

I/O

12L

F14

I/O

12R

F15

I/O

13R

R11

CNTRST

11R

11L

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

4830 drw 02d

6.42

IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 28mm x 28mm x 3.5mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52

156
155
154
153
152
151
150
149
148
147
146
145
144
143
142
141
140
139
138
137
136
135
134
133
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105

70V3579DR

DR-208

(5)

208-Pin PQFP

Top View

(6)

I/O

19L

I/O

19R

I/O

20L

I/O

20R

DDQL

I/O

21L

I/O

21R

I/O

22L

I/O

22R

DDQR

I/O

23L

I/O

23R

I/O

24L

I/O

24R

DDQL

I/O

25L

I/O

25R

I/O

26L

I/O

26R

DDQR

DDQL

I/O

27R

I/O

27L

I/O

28R

I/O

28L

DDQR

I/O

29R

I/O

29L

I/O

30R

I/O

30L

DDQL

I/O

31R

I/O

31L

I/O

32R

I/O

32L

DDQR

I/O

33R

I/O

33L

I/O

34R

I/O

34L

I
/
O

I/O

16L

I/O

16R

I/O

15L

I/O

15R

DDQL

I/O

14L

I/O

14R

I/O

13L

I/O

13R

DDQR

I/O

12L

I/O

12R

I/O

11L

I/O

11R

DDQL

I/O

10L

I/O

10R

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

I/O

DDQR

I/O

I
/
O

4830 drw 02a

6.42

IDT70V3579S
High-Speed 32K x 36 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST = V

OE is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table IRead/Write and Enable Control

(1,2,3,4)

Pin Names

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

- A

14L

- A

14R

Address

I/O

- I/O

35L

I/O

- I/O

35R

Data Input/Output

CLK

Clock

ADS

Address Strobe Enable

CNTEN

Counter Enable

CNTRST

Counter Reset

Byte Enables (9-bit bytes)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(1)

OPT

Option for selecting V

DDQX

(1,2)

Power (3.3V)

(1)

Ground (0V)

4830 tbl 01

CLK

Byte 3

I/O

27-35

Byte 2

I/O

18-26

Byte 1
I/O

9-17

Byte 0

I/O

0-8

MODE

High-Z

DeselectedPower Down

High-Z

DeselectedPower Down

High-Z

All Bytes Deselected

High-Z

Write to Byte 0 Only

High-Z

Write to Byte 1 Only

High-Z

Write to Byte 2 Only

High-Z

Write to Byte 3 Only

High-Z

Write to Lower 2 Bytes Only

High-Z

Write to Upper 2 bytes Only

Write to All Bytes

High-Z

OUT

Read Byte 0 Only

High-Z

OUT

High-Z

Read Byte 1 Only

High-Z

OUT

High-Z

Read Byte 2 Only

OUT

High-Z

Read Byte 3 Only

High-Z

OUT

Read Lower 2 Bytes Only

OUT

High-Z

Read Upper 2 Bytes Only

OUT

Read All Bytes

High-Z

Outputs Disabled

4830 tbl 02

NOTES:
1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels on that port. If OPT

is set to VIH (3.3V),

then that port's I/Os and controls will operate at 3.3V levels and V

DDQX

must be

supplied at 3.3V. If OPT

is set to VIL (0V), then that port's I/Os and controls will

operate at 2.5V levels and V

DDQX

must be supplied at 2.5V. The OPT pins are

independent of one another--both ports can operate at 3.3V levels, both can
operate at 2.5V levels, or either can operate at 3.3V with the other at 2.5V.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70V3579

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 70V3579