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Электронный компонент: 70V7278

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2000 Integrated Device Technology, Inc.
JUNE 2000
DSC-4078/7
1
8Kx16
MEMORY
ARRAY
(BANK 3)
MUX
MUX
R/
W
L
CE
0L
CE
1L
UB
L
LB
L
OE
L
I/O
8L-15L
I/O
0L-7L
A
12L
A
0L(1)
A
5L(1)
A
0L(1)
LB
L
/
UB
L
OE
L
R/
W
L
CE
L
MAILBOX
INTERRUPT
LOGIC
8Kx16
MEMORY
ARRAY
(BANK 1)
MUX
MUX
8Kx16
MEMORY
ARRAY
(BANK 0)
MUX
MUX
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
R/
W
R
CE
0R
CE
1R
UB
R
LB
R
OE
R
I/O
8R-15R
I/O
0R-7R
A
12R
A
0R(1)
CONTROL
LOGIC
I/O
CONTROL
BANK
DECODE
ADDRESS
DECODE
A
5R(1)
A
0R(1)
LB
R
/
UB
R
OE
R
R/
W
R
CE
R
4078 drw 01
MBSEL
R
INT
R
MBSEL
L
INT
L
BKSEL
3(2)
BKSEL
0(2)
BANK
SELECT
BA
1R
BA
0R
BA
1L
BA
0L
HIGH-SPEED 3.3V
32K x 16 BANK-SWITCHABLE
DUAL-PORTED SRAM WITH
EXTERNAL BANK SELECTS
Features
x
x
x
x
x
32K x 16 Bank-Switchable Dual-Ported SRAM Architecture
Four independent 8K x 16 banks
512 kilobit of memory on chip
x
x
x
x
x
Fast asynchronous address-to-data access time: 15ns
x
x
x
x
x
User-controlled input pins included for bank selects
x
x
x
x
x
Independent port controls with asynchronous address &
data busses
x
x
x
x
x
Four 16-bit mailboxes available to each port for inter-
processor communications; interrupt option
IDT70V7278S/L
NOTES:
1. The first six address pins for each port serve dual functions. When
MBSEL = V
IH
, the pins serve as memory address inputs. When
MBSEL = V
IL
, the pins serve as mailbox
address inputs.
2. Each bank has an input pin assigned that allows the user to toggle the assignment of that bank between the two ports. Refer to Truth Table I for more details.
Functional Block Diagram
x
x
x
x
x
Interrupt flags with programmable masking
x
x
x
x
x
Dual Chip Enables allow for depth expansion without
external logic
x
x
x
x
x
UB and LB are available for x8 or x16 bus matching
x
x
x
x
x
LVTTL-compatible, single 3.3V (5%) power supply
x
x
x
x
x
Available in a 100-pin Thin Quad Flatpack
x
x
x
x
x
Industrial temperature range (-40 to +85C) is available
for selected speeds
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
2
Description
The IDT70V7278 is a high-speed 32K x 16 (512K bit) Bank-
Switchable Dual-Ported SRAM organized into four independent 8K x
16 banks. The device has two independent ports with separate
controls, addresses, and I/O pins for each port, allowing each port to
asynchronously access any 8K x 16 memory block not already
accessed by the other port. Accesses by the ports into specific banks
are controlled via bank select pin inputs under the user's control.
Mailboxes are provided to allow inter-processor communications.
Interrupts are provided to indicate mailbox writes have occurred. An
automatic power down feature controlled by the chip enables (
CE
0
and
CE
1
) permits the on-chip circuitry of each port to enter a very low
standby power mode and allows fast depth expansion.
The IDT70V7278 offers a maximum address-to-data access time
as fast as 15ns, and is packaged in a 100-pin Thin Quad Flatpack
(TQFP).
Functionality
The IDT70V7278 is a high-speed asynchronous 32K x 16 Bank-
Switchable Dual-Ported SRAM, organized in four 8K x 16 banks. The
two ports are permitted independent, simultaneous access into sepa-
rate banks within the shared array. There are four user-controlled
Bank Select input pins, and each of these pins is associated with a
specific bank within the memory array. Access to a specific bank is
gained by placing the associated Bank Select pin in the appropriate
state: V
IH
assigns the bank to the left port, and V
IL
assigns the bank to
the right port (See Truth Table IV). Once a bank is assigned to a
particular port, the port has full access to read and write within that
bank. Each port can be assigned as many banks within the array as
needed, up to and including all four banks.
The IDT70V7278 provides mailboxes to allow inter-processor
communications. Each port has four 16-bit mailbox registers available
to which it can write and read and which the opposite port can read
only. These mailboxes are external to the common SRAM array, and
are accessed by setting
MBSEL = V
IL
while setting
CE = V
IH
. Each
mailbox has an associated interrupt: a port can generate an interrupt
to the opposite port by writing to the upper byte of any one of its four
16-bit mailboxes. The interrupted port can clear the interrupt by
reading the upper byte. This read will not alter the contents of the
mailbox.
If desired, any source of interrupt can be independently masked via
software. Two registers are provided to permit interpretation of inter-
rupts: the Interrupt Cause Register and the Interrupt Status Register.
The Interrupt Cause Register gives the user a snapshot of what has
caused the interrupt to be generated - the specific mailbox written to.
The information in this register provides post-mask signals: Interrupt
sources that have been masked will not be updated. The Interrupt
Status Register gives the user the status of all bits that could potentially
cause an interrupt regardless of whether they have been masked.
Truth Table V gives a detailed explanation of the use of these registers.
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
3
INDEX
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V7278PF
PN100-1(4)
100-Pin TQFP
Top View(5)
GND
OE
R
R/
W
R
MBSEL
R
CE
1R
CE
0R
BKSEL
3
NC
GND
A
9R
A
10R
A
8R
A
7R
A
6R
A
11R
I/O
10R
I/O
11R
I/O
12R
I/O
13R
I/O
14R
I/O
15R
GND
UB
R
LB
R
4078 drw 02
I/O
15L
GND
OE
L
R/
W
L
MBSEL
L
CE
1L
CE
0L
Vcc
BKSEL
0
A
11L
A
10L
NC
A
9L
A
8L
A
7L
A
6L
I/O
10L
I/O
11L
I/O
12L
I/O
13L
I/O
14L
UB
L
LB
L
GND
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
G
N
D
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
I
/
O
8
R
I
/
O
9
R
I
/
O
8
L
I
/
O
9
L
I
/
O
6
R
A
4
R
A
5
L
A
4
L
A
3
R
A
0
R
A
1
2
R
I
N
T
R
I
N
T
L
B
K
S
E
L
1
A
3
L
A
5
R
G
N
D
V
c
c
I
/
O
1
L
V
c
c
G
N
D
NC
N
C
B
A
0
R
B
A
1
R
A
1
R
A
2
R
B
K
S
E
L
2
G
N
D
N
C
A
0
L
A
1
2
L
B
A
0
L
B
A
1
L
A
1
L
A
2
L
NC
,
Pin Names
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
NOTES:
1. Duplicated per port.
2. Each bank has an input pin assigned that allows the user to toggle the assign-
ment of that bank between the two ports. Refer to Truth Table IV for more details.
When changing the bank assignment, accesses of the affected banks must be
suspended. Accesses may continue uninterrupted in banks that are not being
reallocated.
3. Generated upon mailbox access.
4. All Vcc pins must be connected to power supply.
5. All GND pins must be connected to ground supply.
6. The first six address pins (A
0
-A
5
) for each port serve dual functions. When MBSEL
= V
IH
, the pins serve as memory address inputs. When MBSEL = V
IL
, the pins serve
as mailbox address inputs (A
6
-A
12
ignored).
Pin Configurations
(1,2,3)
A
0
- A
12
(1,6)
Address Inputs
BA
0
- BA
1
(1)
Bank Address Inputs
MBSEL
(1)
Mailbox Access Control Gate
BKSEL
0-3
(2)
Bank Select Inputs
R/
W
(1)
Read/Write Enable
OE
(1)
Output Enable
CE
0
,
CE
1
(1)
Chip Enables
UB, LB
(1)
I/O Byte Enables
I/O
0
- I/O
15
(1)
Bidirectional Data Input/Output
INT
(1)
Interrupt Flag (Output)
(3)
V
CC
(4)
3.3VPower
GND
(5)
Ground
4078 tbl 01
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
4
Truth Table III Mailbox Read/Write Control
(1)
NOTES:
1.
Chip Enable references are shown above with the actual
CE
0
and CE
1
levels,
CE is a reference only.
2.
Port "A" and "B" references are located where
CE is used.
3.
"H" = V
IH
and "L" = V
IL
.
4.
CE and MBSEL cannot both be active at the same time.
Truth Table I Chip Enable
(1,2,3,4)
Truth Table II Non-Contention Read/Write Control
NOTES:
1.
BA
0L
- BA
1L
BA
0R
- BA
1R
: cannot access same bank simultaneously from both ports.
2.
Refer to Truth Table I.
3.
CE and MBSEL cannot both be active at the same time.
NOTES:
1. There are four mailbox locations per port written to and read from all the I/O's (I/O
0
-I/O
15
). These four mailboxes are addressed by A
0
-A
5.
Refer to Truth Table V.
2. Refer to Truth Table I.
3. Each mailbox location contains a 16-bit word, controllable in bytes by setting input levels to
UB and LB appropriately.
CE
CE
0
CE
1
Mode
L
V
IL
V
IH
Port Selected (TTL Active)
< 0.2V
>V
CC
-0.2V
Port Selected (CMOS Active)
H
V
IH
X
Port Deselected (TTL Inactive)
X
V
IL
Port Deselected (TTL Inactive)
>V
CC
-0.2V
X
Port Deselected (CMOS Inactive)
X
<0.2V
Port Deselected (CMOS Inactive)
4078 tbl 02
Inputs
(1)
Outputs
Mode
CE
(2)
R/
W
OE
UB
LB
MBSEL
I/O
8-15
I/O
0-7
H
X
X
X
X
H
High-Z
High-Z
Deselected: Power-Down
X
(3)
X
X
H
H
X
(3)
High-Z
High-Z
Both Bytes Deselected
L
L
X
L
H
H
DATA
IN
High-Z
Write to Upper Byte Only
L
L
X
H
L
H
High-Z
DATA
IN
Write to Lower Byte Only
L
L
X
L
L
H
DATA
IN
DATA
IN
Write to Both Bytes
L
H
L
L
H
H
DATA
OUT
High-Z
Read Upper Byte Only
L
H
L
H
L
H
High-Z
DATA
OUT
Read Lower Byte Only
L
H
L
L
L
H
DATA
OUT
DATA
OUT
Read Both Bytes
X
(3)
X
H
X
X
X
(3)
High-Z
High-Z
Outputs Disabled
4078 tbl 03
Inputs
Outputs
Mode
CE
(2)
R/
W
OE
UB
LB
MBSEL
I/O
8-15
I/O
0-7
H
H
L
X
(3)
X
(3)
L
DATA
OUT
DATA
OUT
Read Data from Mailbox,
clears interrupt
H
H
L
L
L
L
DATA
OUT
DATA
OUT
Read Data from Mailbox,
clears interrupt
H
L
X
L
(3)
L
(3)
L
DATA
IN
DATA
IN
Write Data into Mailbox
L
X
X
X
X
L
____
____
Not Allowed
4078 tbl 04
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
5
Absolute Maximum Ratings
(1)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 5%)
Capacitance
(1)
(T
A
= +25C, f = 1.0MHz) TQFP Package
Recommended DC Operating
Conditions
Maximum Operating Temperature
and Supply Voltage
(1)
NOTES:
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.
V
TERM
must not exceed Vcc + 5% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 5%.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
NOTES:
1.
V
IL
> -1.5V for pulse width less than 10ns.
2.
V
TERM
must not exceed Vcc + 5%.
NOTES:
1.
This parameter is determined by device characterization but is not production
tested.
2.
3dV represents the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
3.
C
OUT
represents C
I/O
as well.
NOTE:
1. At Vcc
<
2.0V, input leakages are undefined.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50
mA
4078 tbl 05
Grade
Ambient Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
5%
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
5%
4078 tbl 06
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.135
3.3
3.465
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
CC
+5%
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
4078 tbl 07
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
4078 tbl 08
Symbol
Parameter
Test Conditions
70V7278S
70V7278L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.465V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
CE = V
IH
,
MBSEL = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
4078 tbl 09
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
6
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,6)
(V
CC
= 3.3V 5%)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. V
CC
= 3.3V, T
A
= +25C, and are not production tested. I
CCDC
= 120mA (Typ.)
3. At f = f
MAX
,
address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC,
and using "AC Test Conditions" of input levels of
GND to 3V.
4. f = 0 means no address or control lines change.
5. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
6. Refer to Truth Table I.
70V7278X15
Com'l Only
70V7278X20
Com'l Only
70V7278X25
Com'l & Ind
Symbol
Parameter
Test Condition
Version
Typ.
(2)
Max.
Typ.
(2)
Max.
Typ.
(2)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
MBSEL = V
IH
f = f
MAX
(3)
COM'L
S
L
200
200
280
230
170
170
260
210
160
160
250
200
mA
IND
S
L
____
____
____
____
____
____
____
____
160
160
280
230
I
SB1
Standby Current
(Bo th Ports - TTL Level
Inputs)
CE
L
=
CE
R
= V
IH
MBSEL
R
=
MBSEL
L
= V
IH
f = f
MAX
(3)
COM'L
S
L
50
50
85
60
40
40
75
50
35
35
70
45
mA
IND
S
L
____
____
____
____
____
____
____
____
35
35
80
55
I
SB2
Standby Current
(One Port - TTL Level
Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
MBSEL
R
=
MBSEL
L
= V
IH
COM'L
S
L
120
120
160
140
100
100
140
120
90
90
130
110
mA
IND
S
L
____
____
____
____
____
____
____
____
90
90
150
130
I
SB3
Full Standby Current
(Both Ports - All CMOS
Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
MBSEL
R
=
MBSEL
L
> V
CC
- 0.2V
COM'L
S
L
1.5
1.5
6
3
1.5
1.5
6
3
1.5
1.5
6
3
mA
IND
S
L
____
____
____
____
____
____
____
____
1.5
1.5
10
6
I
SB4
Full Standby Current
(One Port - All CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
MBSEL
R
=
MBSEL
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L
S
L
115
115
140
125
95
95
130
110
85
85
120
100
mA
IND
S
L
____
____
____
____
____
____
____
____
85
85
140
120
4078 tbl 10
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
7
AC Test Conditions
Figure 3. Lumped Capacitance Load Typical Derating Curve
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2.
This parameter is guaranteed by device characterization, but is not production tested.
3.
To access RAM,
CE = V
IL
and
MBSEL = V
IH
. To access mailbox,
CE= V
IH
and
MBSEL = V
IL
.
4.
'X' in part numbers indicates power rating (S or L).
5.
Refer to Truth Table I.
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(4)
Figure 1. AC Output Test Load Figure 2. Output Test Load
(for t
LZ
, t
HZ
, t
WZ
, t
OW
)
*Including scope and jig.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
3ns Max.
1.5V
1.5V
Figures 1,2 and 3
4078 tbl 11
4078 drw 04
590
30pF
435
3.3V
DATA
OUT
INT
590
5pF*
435
3.3V
DATA
OUT
4078 drw 03
t
ACE
/t
AA
(Typical, ns)
4078 drw 05
1
2
3
4
5
6
7
8
20 40
100
60 80
120 140 160 180 200
Capacitance (pF)
-1
0
- 10pF is the I/O capacitance
of this device, and 30pF is the
AC Test Load Capacitance
,
70V7278X15
Com'l Only
70V7278X20
Com'l Only
70V7278X25
Com'l & Ind
Unit
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
15
____
20
____
25
____
ns
t
AA
Address Access Time
____
15
____
20
____
25
ns
t
ACE
Chip Enable Access Time
(3)
____
15
____
20
____
25
ns
t
ABE
Byte Enable Access Time
(3)
____
15
____
20
____
25
ns
t
AOE
Output Enable Access Time
____
9
____
10
____
11
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
8
____
9
____
10
ns
t
PU
Chip Enab le to Power Up Time
(2,5)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2,5)
____
15
____
20
____
25
ns
t
MOP
Mailbox Flag Update Pulse (
OE or MBSEL)
10
____
10
____
10
____
ns
t
MAA
Mailbox Address Access Time
____
15
____
20
____
25
ns
4078 tbl 12
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
8
NOTES:
1. Bank 0 refers to the first 8Kx16 memory spaces, Bank 1 to the second 8Kx16
memory spaces, Bank 2 to the third 8Kx16 memory spaces, and Bank 3 to the
fourth 8Kx16 memory spaces. 'LEFT' indicates the bank is assigned to the left port;
'RIGHT' indicates the bank is assigned to the right port. 0-4 banks may be
assigned to either port.
2. The bank select pin inputs must be set at either V
IH
or V
IL
- these inputs are not tri-
statable. When changing the bank assignments, accesses of the affected banks
must be suspended. Accesses may continued uninterrupted in banks that are not
being reallocated.
3. 'H' = V
IH
, 'L' = V
IL
, 'X' = Don't Care.
Assigning the Banks via the
External Bank Selects
There are four bank select pins available on the IDT70V7278, and
each of these pins is associated with a specific bank within the memory
array. The pins are user-controlled inputs: access to a specific bank is
assigned to a particular port by setting the input to the appropriate
level. The process of assigning the banks is detailed in Truth Table IV.
Once a bank is assigned to a port, the owning port has full access to
read and write within that bank. The opposite port is unable to access
that bank until the user reassigns the port. Access by a port to a bank
Truth Table IV Memory Bank
Assignment (CE = V
IH
)
(2,3)
Mailbox Interrupts and Interrupt
Control Registers
If the user chooses the mailbox interrupt function, four mailbox
locations are assigned to each port. These mailbox locations are
external to the memory array. The mailboxes are accessed by taking
MBSEL LOW while holding CE HIGH.
The mailboxes are 16 bits wide and controllable by byte:
the message is user-defined since these are addressable SRAM
locations. An interrupt is generated to the opposite port upon writing to
the upper byte of any mailbox location. A port can read the message
it has just written in order to verify it: this read will not alter the status
of the interrupt sent to the opposite port. The interrupted port can clear
the interrupt by reading the upper byte of the applicable mailbox. This
read will not alter the contents of the mailbox. The use of mailboxes to
generate interrupts to the opposite port and the reading of mailboxes
to clear interrupts is detailed in Truth Table V.
If desired, any of the mailbox interrupts can be independently
masked via software. Masking of the interrupt sources is done in the
Mask Register. The masks are individual and independent: a port can
mask any combination of interrupt sources with no effect on the other
sources. Each port can modify only its own Mask Register. The use of
this register is detailed in Truth Table V.
Two registers are provided to permit interpretation of interrupts:
these are the Interrupt Cause Register and the Interrupt Status
Register. The Interrupt Cause Register gives the user a snapshot of
what has caused the interrupt to be generated - the specific mailbox
written to by the opposite port. The information in this register provides
post-mask signals: interrupt sources that have been masked will not
be updated. The Interrupt Status Register gives the user the status of
all bits that could potentially cause an interrupt regardless of whether
they have been masked. The use of the Interrupt Cause Register and
the Interrupt Status Register is detailed in Truth Table V.
which it does not control will have no effect if written, and if read
unknown values on D
0
-D
15
will be returned. Each port can be assigned
as many banks within the array as needed, up to and including all four
banks.
The bank select pin inputs must be set at either V
IH
or V
IL
- these
inputs are not tri-statable. When changing the bank assignments,
accesses of the affected banks must be suspended. Accesses may
continue uninterrupted in banks that are not being reallocated.
BKSEL0
BKSEL1
BKSEL2
BKSEL3
BANK AND
DIRECTION
(1)
H
X
X
X
BANK 0 LEFT
X
H
X
X
BANK 1 LEFT
X
X
H
X
BANK 2 LEFT
X
X
X
H
BANK 3 LEFT
L
X
X
X
BANK 0 RIGHT
X
L
X
X
BANK 1 RIGHT
X
X
L
X
BANK 2 RIGHT
X
X
X
L
BANK 3 RIGHT
4078 tbl 13
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
9
Truth Table V Mailbox Interrupts (CE = V
IH
)
(8,9)
NOTES:
1. There are four independent mailbox locations available to each side, external to the standard memory array. The mailboxes can be written to in either 8-bit or 16-bit
widths. The upper byte of each mailbox has an associated interrupt to the opposite port. The mailbox interrupts can be individually masked if desired, and the status of
the interrupt determined by polling the Interrupt Status Register (see Note 6 for this table). A port can read its own mailboxes to verify the data written, without affecting
the interrupt which is sent to the opposite port.
2. These registers allow a port to read the data written to a specific mailbox location by the opposite port. Reading the upper byte of the data in a particular mailbox clears
the interrupt associated with that mailbox without modifying the data written. Once the address and R/
W are stable, the actual clearing of the interrupt is triggered by the
transition of
MBSEL from V
IH
to V
IL
.
3. This register contains the Mask Register (bits D
0
-D
3
), the Interrupt Cause Register (bits D
4
-D
7
), and the Interrupt Status Register (bits D
8
-D
11
). The controls for R/
W, UB,
and
LB are manipulated in accordance with the appropriate function. See Notes 4, 5, and 6 for this table. Bits D
12
-D
15
are "Don't Care".
4. This register, the Mask Register, allows the user to independently mask the various interrupt sources. Writing V
IH
to the appropriate bit (D
0
= Mailbox 0, D
1
= Mailbox 1,
D
2
= Mailbox 2, and D
3
= Mailbox 3) disables the interrupt, while writing V
IL
enables the interrupt. All four bits in this register must be written at the same time. This
register can be read at any time to verify the mask settings. The masks are individual and independent: any single interrupt source can be masked with no effect on the
other sources. Each port can modify only its own mask settings.
5. This register, the Interrupt Cause Register, gives the user a snapshot of what has caused the interrupt to be generated. Reading V
OL
for a specific bit (D
4
= Mailbox 0, D
5
= Mailbox 1, D
6
= Mailbox 2, and D
7
= Mailbox 3) indicates that the associated interrupt source has generated an interrupt. Acknowledging the interrupt clears the bit in
this register (see Note 2 for this table). This register provides post-mask information: if the interrupt source has been masked, the associated bit in this register will not
update.
6. This register, the Interrupt Status Register, gives the user the status of all interrupt sources that could potentially cause an interrupt regardless of whether they have
been masked. Reading V
OL
for a specific bit (D
8
= Mailbox 0, D
9
= Mailbox 1, D
10
= Mailbox 2, and D
11
= Mailbox 3) indicates that the associated interrupt source has
generated an interrupt. Acknowledging the interrupt clears the associated bit in this register (see Note 2 for this table). This register provides pre-mask information:
regardless of whether an interrupt source has been masked, the associated bit in this register will update.
7. Access to registers defined as "RESERVED" will have no effect, if written, and if read unknown values on D
0
-D
15
will be returned.
8. These registers are not guaranteed to initialize in any known state. At power-up, the initialization sequence should include the set-up of these registers.
9. 'L' = V
IL
or V
OL
, 'H' = V
IH
or V
OH
, 'X' = Don't Care.
MB
SEL R/W UB LB A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 D10 D11 D12 D13 D14 D15 DESCRIPTION
L
X
X
X
L
L
L
L
L
L
RESERVED (7)
RESERVED (7)
L
X
X
X
RESERVED (7)
RESERVED (7)
L
(1)
(1)
(1)
H
L
L
L
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 0 - SET INTERRUPT ON OPPOSITE PORT
L
(1)
(1)
(1)
H
L
L
L
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 1 - SET INTERRUPT ON OPPOSITE PORT
L
(1)
(1)
(1)
H
L
L
L
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 2 - SET INTERRUPT ON OPPOSITE PORT
L
(1)
(1)
(1)
H
L
L
L
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 3 - SET INTERRUPT ON OPPOSITE PORT
H
(2)
(2)
H
L
L
H
L
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 0 - CLEAR OPPOSITE PORT INTERRUPT
H
(2)
(2)
H
L
L
H
L
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 1 - CLEAR OPPOSITE PORT INTERRUPT
H
(2)
(2)
H
L
L
H
H
L
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 2 - CLEAR OPPOSITE PORT INTERRUPT
H
(2)
(2)
H
L
L
H
H
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
X
MAILBOX 3 - CLEAR OPPOSITE PORT INTERRUPT
L
(3)
(3)
(3)
H
L
H
L
L
L
(4)
(4)
(4)
(4)
(5)
(5)
(5)
(5)
(6)
(6)
(6)
(6)
X
X
X
X
MAILBOX INTERRUPT CONTROLS
L
X
X
X
RESERVED (7)
RESERVED (7)
L
X
X
X
H
H
H
H
H
H
RESERVED (7)
RESERVED (7)
4078 tbl 14
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
10
Waveform of Read Cycles
(4)
Timing of Power-Up Power-Down
CE
4078 drw 07
t
PU
I
CC
I
SB
t
PD
50%
50%
(5)
,
NOTES:
1. Timing depends on which signal is asserted last,
CE, OE, LB, or UB.
2. Timing depends on which signal is de-asserted first
CE, OE, LB, or UB.
3. Start of valid data depends on which timing becomes effective last: t
AOE
, t
ACE
, t
AA
, or t
ABE
.
4.
MBSEL = V
IH
.
5. Refer to Truth Table I.
t
RC
R/
W
CE
ADDR
t
AA
OE
UB
,
LB
4078 drw 06
(3)
t
ACE
(3)
t
AOE
(3)
t
ABE
(3)
(1)
t
LZ
t
OH
(2)
t
HZ
DATA
OUT
VALID DATA
(3)
(5)
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
11
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2.
This parameter is guaranteed by device characterization, but is not production tested.
3.
To access RAM,
CE = V
IL
and
MBSEL = V
IH
. To access mailbox,
CE = V
IH
and
MBSEL = V
IL
. Either condition must be valid for the entire t
EW
time.
Refer to Truth Tables I and III.
4.
The specification for t
DH
must be met by the device supplying write data to the RAM under all operating conditions. Although t
DH
and t
OW
values will vary over voltage and
temperature, the actual t
DH
will always be smaller than the actual t
OW
.
5.
'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage
(5)
Symbol
Parameter
70V7278X15
Com'l Only
70V7278X20
Com'l Only
70V7278X25
Com'l & Ind
Unit
Min.
Max.
Min.
Max.
Min.
Max.
WRITE CYCLE
t
WC
Write Cycle Time
15
____
20
____
25
____
ns
t
EW
Chip Enable to End-of-Write
(3)
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write
12
____
15
____
20
____
ns
t
AS
Address Set-up Time
(3)
0
____
0
____
0
____
ns
t
BS
Bank Set-up Time
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
12
____
15
____
20
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
15
____
15
____
20
____
ns
t
HZ
Output High-Z Time
(1,2)
____
8
____
9
____
10
ns
t
DH
Data Hold Time
(4)
0
____
0
____
0
____
ns
t
WZ
Write Enab le to Output in High-Z
(1,2)
____
8
____
9
____
10
ns
t
OW
Output Active from End-of-Write
(1,2,4)
3
____
3
____
3
____
ns
t
MWRD
Mailbo x Write to Read Time
5
____
5
____
5
____
ns
4078 tbl 15
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
12
Timing Waveform of Write Cycle No. 1, R/W Controlled Timing
(1,5,8)
NOTES:
1. R/
W or CE or UB and LB must be HIGH during all address transitions.
2. A write occurs during the overlap (t
EW
or t
WP
) of a LOW
CE and a LOW R/W for memory array writing cycle.
3. t
WR
is measured from the earlier of
CE or R/W (or MBSEL or R/W) going HIGH to the end of write cycle.
4. During this period, the I/O pins are in the output state and input signals must not be applied.
5. If the
CE or MBSEL LOW transition occurs simultaneously with or after the R/W LOW transition, the outputs remain in the High-impedance state.
6. Timing depends on which enable signal is asserted last,
CE or R/W.
7. This parameter is guaranteed by device characterization, but is not production tested. Transition is measured 0mV from steady state with the Output Test Load
(Figure 2).
8. If
OE is LOW during R/W controlled write cycle, the write pulse width must be the larger of t
WP
or (t
WZ
+ t
DW
) to allow the I/O drivers to turn off and data to be placed on the
bus for the required t
DW
. If
OE is HIGH during an R/W controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t
WP
.
9. To access RAM,
CE = V
IL
and
MBSEL = V
IH
. To access mailboxes,
CE = V
IH
and
MBSEL = V
IL
. t
EW
must be met for either condition.
10. Refer to Truth Table I.
Timing Waveform of Write Cycle No. 2, CE, UB, LB Controlled Timing
(1,5)
R/
W
t
WC
t
HZ
t
AW
t
WR
t
AS
t
WP
DATA
OUT
(2)
t
WZ
t
DW
t
DH
t
OW
OE
ADDRESS
DATA
IN
(6)
(4)
(7)
UB
or
LB
4078 drw 08
(9)
CE
or
MBSEL
(9,10)
(7)
(3)
t
LZ
VALID
(4)
4078 drw 09
t
WC
t
AS
t
WR
t
DW
t
DH
ADDRESS
DATA
IN
R/
W
t
AW
t
EW
UB
or
LB
(3)
(2)
(6)
CE
or
MBSEL
(9,10)
(9)
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
13
Timing Waveform of Mailbox Read after Write Timing, Either Side
(1,2)
NOTES:
1.
CE
= V
IH
for the duration of the above timing (both write and read cycle), refer to Truth Table I.
2.
UB and LB are controlled as necessary to enable the desired byte accesses.
MBSEL
4078 drw 11
t
AW
t
EW
t
MOP
I/O
0-15
VALID ADDRESS
t
MAA
R/
W
t
WR
t
OH
t
ACE
VALID ADDRESS
DATA
IN
VALID
DATA
OUT
VALID
t
DW
t
WP
t
DH
t
AS
t
MWRD
t
AOE
Read Cycle
Write Cycle
A
0
-A
5
OE
Timing Waveform of Left Port Write to Right Port Read of Same Data
(1,2,3)
NOTES:
1.
UB and LB are controlled as necessary to enable the desired byte accesses.
2. Timing for Right Port Write to Left Port Read is identical.
3. Refer to Truth Table I and IV.
BKSEL
0-3
4078 drw 10
t
WC
I/O
0L-15L
ADDRESSES MATCH
DATA
IN
VALID
DATA
OUT
VALID
Read Cycle
Write Cycle
CE
L
A
0L-12L
and A
0R-12R
CE
R
I/O
0R-15R
R/
W
R
OE
R
t
AS
t
WP
t
AW
t
EW
t
DW
t
DH
t
WR
t
BS
t
LZ
t
ACE
t
HZ
t
OH
R/
W
L
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
14
Waveform of Interrupt Timing
(1,5)
NOTES:
1. All timing is the same for left and right ports. Port "A" may be either the left or right port. Port "B" is the port opposite from port "A".
2. See Interrupt Truth Table V.
3. Timing depends on which enable signal (
CE
or R/
W) is asserted last.
4. Timing depends on which enable signal (
CE or R/W) is de-asserted first.
5. Refer to Truth Table I.
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
AC Electrical Characteristics Over the
Operating Temperature and Supply Voltage Range
(1)
4078 drw 12
ADDR
"A"
MAILBOX SET ADDRESS
MBSEL
"A"
R/
W
"A"
t
AS
t
WC
t
WR
(3)
(4)
t
INS
(3)
INT
"B"
(2)
4078 drw 13
ADDR
"B"
MAILBOX CLEAR ADDRESS
MBSEL
"B"
OE
"B"
t
AS
t
RC
(3)
t
INR
(3)
INT
"B"
(2)
70V7278X15
Com'l Only
70V7278X20
Com'l Only
70V7278X25
Com'l & Ind
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Unit
INTERRUPT TIMING
t
AS
Address Set-up Time
0
____
0
____
0
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
ns
t
INS
Interrupt Set Time
____
15
____
20
____
25
ns
t
INR
Interrupt Reset Time
____
15
____
20
____
25
ns
4078 tbl 16
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
15
Depth and Width Expansion
The IDT70V7278 features dual chip enables (refer to Truth Table
I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.
The IDT70V7278 can also be used in applications requiring
4078 drw 14
IDT70V7278
Bank-Switchable
SRAM
CE
0
CE
1
CE
1
CE
0
CE
0
CE
1
A
13
CE
1
CE
0
V
CC
V
CC
IDT70V7278
Bank-Switchable
SRAM
IDT70V7278
Bank-Switchable
SRAM
IDT70V7278
Bank-Switchable
SRAM
Control Inputs
Control Inputs
Control Inputs
Control Inputs
BKSEL
0-3
R/
W
LB
,
UB
OE
Figure 4. Depth and Width Expansion with IDT70V7278
expanded width, as indicated in Figure 4. Since the banks are allocated
at the discretion of the user, the external controller can be set up to drive
the input signals for the various devices as required to allow for 32-bit or
wider applications.
6.42
IDT70V7278S/L
32K x 16 3.3V Bank-Switchable Dual-Ported SRAM with External Bank Selects Industrial and Commercial Temperature Ranges
16
Ordering Information
A
Power
999
Speed
A
Package
A
Process/
Temperature
Range
Blank
I
Commercial (0
C to +70
C)
Industrial (-40
C to +85
C)
PF
100-pin TQFP (PN100-1)
15
20
25
S
L
Standard Power
Low Power
XXXXX
Device
Type
512Kbit (4 x 8K x 16) 3.3V
Bank-Switchable Dual-Ported SRAM
with External Bank Selects
70V7278
IDT
4078 drw 15
Commercial Only
Commercial & Industrial
Commercial & Industrial
Speed in nanoseconds
,
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
Datasheet Document History
3/5/99:
Initiated datasheet document history
Converted to new format
Cosmetic typographical corrections
Page 3 Added additional notes to pin configurations
Added 15ns speed grade
6/10/99:
Changed drawing format
9/1/99:
Removed Preliminary
3/10/00:
Added Industrial Temperature Ranges and removed corresponding notes
Replaced IDT logo
Page 1 Added industrial temperature note
Changed 200mV to 0mV in notes
6/8/00:
Page 5
Increated storage temperature parameter
Clarified T
A
Parameter
Page 6
DC Electrical parameterschanged wording from "open" to "disabled"
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
831-754-4613
Santa Clara, CA 95054
fax: 408-492-8674
DualPortHelp@idt.com
www.idt.com