DECEMBER 2002

DSC 5628/6

Functional Block Diagram

Features:

512K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
64 independent 8K x 18 banks
9 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access
 Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

 Industrial: 3.6ns (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
5ns cycle time, 200MHz operation (14Gbps bandwidth)
Fast 3.4ns clock to data out

 1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

Data input, address, byte enable and control registers
Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus
matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply
for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port

Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz

Available in a 144-pin Thin Quad Flatpack (TQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1
 Due to limited pin count, JTAG is not supported on the

144-pin TQFP package.

HIGH-SPEED 3.3V 512K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

IDT70V7339S

8Kx18

MEMORY

ARRAY

(BANK 63)

MUX

PL/

OPT

CLK

ADS

CNTEN

REPEAT

I/O

0L-17L

12L

JTAG

8Kx18

MEMORY

ARRAY

(BANK 1)

MUX

8Kx18

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

I/O

0R-17R

12R

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

5628 drw 01

PL/

OPT

CLK

ADS

CNTEN

REPEAT

TMS
TCK

TRST

TDI

TDO

NOTE:
1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.

6.42

IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V7339 is a high-speed 512Kx18 (9Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent
8Kx18 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 8Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data

Pin Configuration

(1,2,3,4)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

A17

B17

C17

D17

I/O

E16

E17

D16

I/O

C16

B16

I/O

A16

A15

OPT

B15

DDQR

C15

I/O

D15

DDQL

E15

E14

I/O

D14

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

D12

D11

REPEAT

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

12L

11L

TDO

TDI

PL/

DDQR

I/O

10L

I/O

DDQL

I/O

11L

DDQR

I/O

10R

DDQL

I/O

11R

I/O

12L

DDQR

I/O

12R

DDQL

I/O

14R

I/O

13R

I/O

14L

DDQR

I/O

13L

DDQL

I/O

15R

I/O

15L

I/O

16R

I/O

16L

DDQR

I/O

17R

TCK

I/O

17L

DDQL

TMS

PL/

TRST

11R

P12

CNTEN

U10

P10

T11

P11

CLK

R12

T12

U12

P13

12R

R13

T13

U13

U14

T14

R14

P14

P15

I/O

R15

DDQL

T15

U15

OPT

U16

U17

I/O

T16

T17

R17

DDQR

R16

I/O

P17

P16

N17

I/O

N16

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

M14

L17

I/O

L16

L15

I/O

L14

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

H16

H15

H14

G17

G16

I/O

G15

DDQL

G14

F17

DDQR

F16

F14

70V7339BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

F15

I/O

R11

ADS

B10

C13

R10

T10

10R

5628 drw 02c

1 1 /2 0 /0 1

register, the IDT70V7339 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE

and CE

, permits the on-chip circuitry of each

port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.

The 70V7339 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(V

) remains at 3.3V. Please refer also to the

functional description on page 19.

6.42

IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

70V7339BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

D16

I/O

C16

I/O

B16

A16

A15

B15

C15

D15

E15

I/O

E14

D14

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

12L

10L

DDQL

BA1

DDQL

PL/

TDO

I/O

TDI

I/O

10R

I/O

10L

DDQL

I/O

11L

I/O

11R

DDQL

I/O

12L

DDQR

I/O

12R

DDQR

I/O

13L

I/O

14R

I/O

13R

DDQL

I/O

14L

DDQL

I/O

15L

I/O

15R

DDQR

I/O

16R

I/O

16L

DDQR

I/O

17R

PL/

I/O

17L

TMS

TRST

TCK

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

12R

T14

R14

OPT

P14

P15

R15

T15

T16

R16

P16

I/O

N16

N15

I/O

N14

M16

M15

I/O

M14

I/O

L16

I/O

L15

L14

I/O

K16

I/O

K15

K14

J16

I/O

J15

I/O

J14

I/O

H16

I/O

H15

H14

G16

G15

G14

I/O

F16

I/O

F14

I/O

F15

R11

REPEAT

11R

11L

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5628 drw 02d

11/20/01

6.42

IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4,7)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 20mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. Due to the limited pin count, JTAG is not supported in the DD-144 package.

DDQR

I/O

10L

I/O

10R

I/O

11L

I/O

11R

DDQL

I/O

12L

I/O

12R

DDQR

DDQL

I/O

13R

I/O

13L

I/O

14R

I/O

14L

DDQR

I/O

15R

I/O

15L

I/O

16R

I/O

16L

I/O

17R

I/O

17L

DDQL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15

16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36

108

107
106
105
104
103
102
101
100

99
98

97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82

81
80
79
78
77
76
75
74
73

12R

11R

10R

OPT

DDQR

I/O

DDQL

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

OPT

70V7339DD

DD-144

(5)

144-Pin TQFP

Top View

(6)

5628 drw 02a

11/20/01

6.42

IDT70V7339S
High-Speed 512K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

- BA

Bank Address

(4)

- A

12L

- A

12R

Address

I/O

- I/O

17L

I/O

- I/O

17R

Data Input/Output

CLK

Clock

PL/

Pipeline/Flow-Through

ADS

Address Strobe Enable

CNTEN

Counter Enable

REPEAT

Counter Repeat

(3)

Byte Enables (9-bit bytes)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(1)

OPT

Option for selecting V

DDQX

(1,2)

Power (3.3V)

(1)

Ground (0V)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz)

TMS

Test Mode Select

TRST

Reset (Initialize TAP Controller)

5628 tbl 01

NOTES:
1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another--both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.

3. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA

- BA

). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).

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