DECEMBER 2002

DSC 5630/6

Functional Block Diagram

Features:

128K x 18 Synchronous Bank-Switchable Dual-ported
SRAM Architecture
64 independent 2K x 18 banks
2 megabits of memory on chip

Bank access controlled via bank address pins

High-speed data access
 Commercial: 3.4ns (200MHz)/3.6ns (166MHz)/

4.2ns (133MHz) (max.)

 Industrial: 3.6 (166MHz)/4.2ns (133MHz) (max.)

Selectable Pipelined or Flow-Through output mode

Counter enable and repeat features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
5ns cycle time, 200MHz operation (14Gbps bandwidth)
Fast 3.4ns clock to data out
1.5ns setup to clock and 0.5ns hold on all control, data, and

address inputs @ 200MHz

Data input, address, byte enable and control registers
Self-timed write allows fast cycle time

Separate byte controls for multiplexed bus and bus
matching compatibility

LVTTL- compatible, 3.3V (±150mV) power supply
for core

LVTTL compatible, selectable 3.3V (±150mV) or 2.5V
(±100mV) power supply for I/Os and control signals on
each port

Industrial temperature range (-40°C to +85°C) is
available at 166MHz and 133MHz

Available in a 144-pin Thin Quad Flatpack (TQFP),
208-pin fine pitch Ball Grid Array (fpBGA), and 256-pin Ball
Grid Array (BGA)

Supports JTAG features compliant with IEEE 1149.1
 Due to limited pin count, JTAG is not supported on the

144-pin TQFP package.

HIGH-SPEED 3.3V 128K x 18
SYNCHRONOUS
BANK-SWITCHABLE
DUAL-PORT STATIC RAM
WITH 3.3V OR 2.5V INTERFACE

IDT70V7399S

2Kx18

MEMORY

ARRAY

(BANK 63)

MUX

PL/

OPT

CLK

ADS

CNTEN

REPEAT

I/O

0L-17L

10L

JTAG

2Kx18

MEMORY

ARRAY

(BANK 1)

MUX

2Kx18

MEMORY

ARRAY

(BANK 0)

MUX

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

I/O

0R-17R

10R

CONTROL

LOGIC

I/O

CONTROL

BANK

DECODE

ADDRESS

DECODE

5630 drw 01

PL/

OPT

CLK

ADS

CNTEN

REPEAT

TMS
TCK

TRST

TDI

TDO

NOTE:
1. The Bank-Switchable dual-port uses a true SRAM

core instead of the traditional dual-port SRAM core.
As a result, it has unique operating characteristics.
Please refer to the functional description on page 19
for details.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Description:

The IDT70V7399 is a high-speed 128Kx18 (2Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent
2Kx18 banks. The device has two independent ports with separate
control, address, and I/O pins for each port, allowing each port to access
any 2Kx18 memory block not already accessed by the other port.
Accesses by the ports into specific banks are controlled via the bank
address pins under the user's direct control.

Registers on control, data, and address inputs provide minimal setup

and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times. With an input data

Pin Configuration

(1,2,3,4)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 15mm x 15mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

A17

B17

C17

D17

I/O

E16

E17

D16

I/O

C16

B16

I/O

A16

A15

OPT

B15

DDQR

C15

I/O

D15

DDQL

E15

E14

I/O

D14

D13

C12

C14

B14

A14

A12

CNTEN

B12

C11

D12

D11

REPEAT

C10

B11

ADS

A11

CLK

D10

10L

B13

A13

A10

TDO

TDI

PL/

DDQR

I/O

10L

I/O

DDQL

I/O

11L

DDQR

I/O

10R

DDQL

I/O

11R

I/O

12L

DDQR

I/O

12R

DDQL

I/O

14R

I/O

13R

I/O

14L

DDQR

I/O

13L

DDQL

I/O

15R

I/O

15L

I/O

16R

I/O

16L

DDQR

I/O

17R

TCK

I/O

17L

DDQL

TMS

PL/

TRST

P12

CNTEN

U10

P10

T11

P11

CLK

R12

T12

U12

P13

R13

T13

U13

U14

T14

R14

P14

P15

I/O

R15

DDQL

T15

U15

OPT

U16

U17

I/O

T16

T17

R17

DDQR

R16

I/O

P17

P16

N17

I/O

N16

N15

DDQL

N14

I/O

M17

DDQR

M16

I/O

M15

M14

L17

I/O

L16

L15

I/O

L14

K17

K16

I/O

K15

DDQL

K14

I/O

J17

DDQR

J16

J15

J14

H17

I/O

H16

H15

H14

G17

G16

I/O

G15

DDQL

G14

F17

DDQR

F16

F14

70V7399BF

BF-208

(5)

208-Pin fpBGA

Top View

(6)

F15

I/O

R11

ADS

B10

C13

R10

T10

10R

5630 drw 02c

11/20/01

register, the IDT70V7399 has been optimized for applications having
unidirectional or bidirectional data flow in bursts. An automatic power down
feature, controlled by CE

and CE

, permits the on-chip circuitry of each

port to enter a very low standby power mode. The dual chip enables also
facilitate depth expansion.

The 70V7399 can support an operating voltage of either 3.3V or 2.5V

on one or both ports, controllable by the OPT pins. The power supply for
the core of the device(V

) remains at 3.3V. Please refer also to the

functional description on page 19.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is

set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 17mm x 17mm x 1.4mm, with 1.0mm ball-pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.

70V7399BC

BC-256

(5)

256-Pin BGA

Top View

(6)

E16

I/O

D16

I/O

C16

I/O

B16

A16

A15

B15

C15

D15

E15

I/O

E14

D14

D13

C12

C14

OPT

B14

A14

A12

B12

C11

ADS

D12

DDQR

D11

DDQR

C10

CLK

B11

REPEAT

A11

CNTEN

DDQR

DDQL

D10

DDQL

B13

A13

A10

DDQR

10L

DDQL

PL/

TDO

I/O

TDI

I/O

10R

I/O

10L

DDQL

I/O

11L

I/O

11R

DDQL

I/O

12L

DDQR

I/O

12R

DDQR

I/O

13L

I/O

14R

I/O

13R

DDQL

I/O

14L

DDQL

I/O

15L

I/O

15R

DDQR

I/O

16R

I/O

16L

DDQR

I/O

17R

PL/

I/O

17L

TMS

TRST

TCK

P12

P10

CLK

T11

CNTEN

P11

ADS

R12

T12

P13

R13

T13

T14

R14

OPT

P14

P15

R15

T15

T16

R16

P16

I/O

N16

N15

I/O

N14

M16

M15

I/O

M14

I/O

L16

I/O

L15

L14

I/O

K16

I/O

K15

K14

J16

I/O

J15

I/O

J14

I/O

H16

I/O

H15

H14

G16

G15

G14

I/O

F16

I/O

F14

I/O

F15

R11

REPEAT

B10

C13

10R

R10

T10

E10

E11

E12

E13

DDQR

F10

F12

F13

DDQR

G10

G11

G12

G13

DDQL

H10

H11

H12

H13

DDQL

J10

J11

J12

J13

DDQR

DDQL

K10

K11

K12

L10

L11

L12

M10

M11

M12

DDQR

N10

DDQR

N11

DDQL

N12

DDQL

K13

DDQR

L13

DDQL

M13

DDQL

N13

F11

5630 drw 02d

11/20/01

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Configuration

(1,2,3,4,7)

(con't.)

NOTES:
1. All V

pins must be connected to 3.3V power supply.

2. All V

DDQ

pins must be connected to appropriate power supply: 3.3V if OPT pin for that port is set to V

(3.3V), and 2.5V if OPT pin for that port is set to V

(0V).

3. All V

pins must be connected to ground supply.

4. Package body is approximately 20mm x 20mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
7. Due to the limited pin count, JTAG is not supported in the DD-144 package.

DDQR

I/O

10L

I/O

10R

I/O

11L

I/O

11R

DDQL

I/O

12L

I/O

12R

DDQR

DDQL

I/O

13R

I/O

13L

I/O

14R

I/O

14L

DDQR

I/O

15R

I/O

15L

I/O

16R

I/O

16L

I/O

17R

I/O

17L

DDQL

1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26

27
28
29
30
31
32
33
34
35
36

108
107
106
105
104
103
102
101
100

99
98
97
96
95
94

93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77

76
75
74
73

10R

OPT

DDQR

I/O

DDQL

I/O

DDQR

DDQL

I/O

DDQR

I/O

DDQL

OPT

70V7399DD

DD-144

(5)

144-Pin TQFP

Top View

(6)

5630 drw 02a

11/20/01

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Pin Names

Left Port

Right Port

Names

Chip Enables

Read/Write Enable

Output Enable

- BA

Bank Address

(4)

- A

101L

- A

10R

Address

I/O

- I/O

17L

I/O

- I/O

17R

Data Input/Output

CLK

Clock

PL/

Pipeline/Flow-Through

ADS

Address Strobe Enable

CNTEN

Counter Enable

REPEAT

Counter Repeat

(3)

Byte Enables (9-bit bytes)

DDQL

DDQR

Power (I/O Bus) (3.3V or 2.5V)

(1)

OPT

Option for selecting V

DDQX

(1,2)

Power (3.3V)

(1)

Ground (0V)

TDI

Test Data Input

TDO

Test Data Output

TCK

Test Logic Clock (10MHz)

TMS

Test Mode Select

TRST

Reset (Initialize TAP Controller)

5630 tbl 01

NOTES:
1. V

, OPT

, and V

DDQX

must be set to appropriate operating levels prior to

applying inputs on the I/Os and controls for that port.

2. OPT

selects the operating voltage levels for the I/Os and controls on that port.

If OPT

is set to VIH (3.3V), then that port's I/Os and controls will operate at 3.3V

levels and V

DDQX

must be supplied at 3.3V. If OPT

is set to VIL (0V), then that

port's I/Os and address controls will operate at 2.5V levels and V

DDQX

must be

supplied at 2.5V. The OPT pins are independent of one another--both ports can
operate at 3.3V levels, both can operate at 2.5V levels, or either can operate
at 3.3V with the other at 2.5V.

3. When

REPEAT

is asserted, the counter will reset to the last valid address loaded

via

ADS

4. Accesses by the ports into specific banks are controlled by the bank address

pins under the user's direct control: each port can access any bank of memory
with the shared array that is not currently being accessed by the opposite port
(i.e., BA

- BA

). In the event that both ports try to access the

same bank at the same time, neither access will be valid, and data at the two
specific addresses targeted by the ports within that bank may be corrupted (in
the case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, REPEAT are set as appropriate for address access. Refer to Truth Table II for details.

OE is an asynchronous input signal.

4. It is possible to read or write any combination of bytes during a given access. A few representative samples have been illustrated here.

Truth Table IRead/Write and Enable Control

(1,2,3,4)

CLK

R/W

Upper Byte

I/O

9-17

Lower Byte

I/O

0-8

MODE

High-Z

DeselectedPower Down

High-Z

DeselectedPower Down

High-Z

All Bytes Deselected

High-Z

Write to Lower Byte Only

High-Z

Write to Upper Byte Only

Write to both Bytes

High-Z

OUT

Read Lower Byte Only

OUT

High-Z

Read Upper Byte Only

OUT

Read both Bytes

High-Z

Outputs Disabled

5630 tbl 02

Truth Table IIAddress and Address Counter Control

(1,2,7)

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

2. Read and write operations are controlled by the appropriate setting of R/

W, CE

, CE

UB/LB and OE.

3. Outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle.
4.

ADS and REPEAT are independent of all other memory control signals including CE

, CE

and

UB/LB.

5. The address counter advances if

CNTEN = V

on the rising edge of CLK, regardless of all other memory control signals including

, CE

UB/LB.

6. When

REPEAT is asserted, the counter will reset to the last valid address loaded via ADS. This value is not set at power-up: a known location should be loaded

via

ADS during initialization if desired. Any subsequent ADS access during operations will update the REPEAT address location.

7. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0. Refer
to Timing Waveform of Counter Repeat, page 18. Care should be taken during operation to avoid having both counters point to the same bank (i.e., ensure BA

- BA

), as this condition will invalidate the access for both ports. Please refer to the functional description on page 19 for details.

Address

Previous

Address

Addr
Used

CLK

ADS

CNTEN REPEAT

(6)

I/O

(3)

MODE

(4)

I/O

(n)

External Address Used

An + 1

(5)

I/O

(n+1)

Counter Enabled--Internal Address generation

An + 1

I/O

(n+1)

External Addre ss Blocked--Counter disab led (An + 1 reused)

(4)

I/O

(0)

Counter Set to last valid

ADS load

5630 tbl 03

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Recommended Operating

Temperature and Supply Voltage

(1)

Recommended DC Operating

Conditions with V

DDQ

at 2.5V

Absolute Maximum Ratings

(1)

NOTES:
1. Undershoot of V

IL >

-1.5V for pulse width less than 10ns is allowed.

2. V

TERM

must not exceed V

DDQ

+ 100mV.

3. To select operation at 2.5V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V

(0V), and V

DDQX

for that port must be supplied

as indicated above.

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+ 150mV for more than 25% of the cycle time or

4ns maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 150mV.

NOTE:
1. This is the parameter T

. This is the "instant on" case temperature.

Grade

Ambient

Temperature

GND

Commercial

C to +70

3.3V

150mV

Industrial

-40

C to +85

3.3V

150mV

5630 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

3.15

3.3

3.45

DDQ

I/O Supply Voltage

(3)

2.4

2.5

2.6

Ground

Input High Voltage
(Address & Control Inputs)

1.7

____

DDQ

+ 100mV

(2)

Input High Voltage - I/O

(3)

1.7

____

DDQ

+ 100mV

(2)

Input Low Voltage

-0.3

(1)

____

0.7

5630 tbl 05a

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage
with Respect to

GND

-0.5 to +4.6

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-65 to +150

OUT

DC Output Current

5630 tbl 06

Recommended DC Operating

Conditions with V

DDQ

at 3.3V

NOTES:
1. Undershoot of V

IL >

-1.5V for pulse width less than 10ns is allowed.

2. V

TERM

must not exceed V

DDQ

+ 150mV.

3. To select operation at 3.3V levels on the I/Os and controls of a given port, the

OPT pin for that port must be set to V

(3.3V), and V

DDQX

for that port must be

supplied as indicated above.

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

3.15

3.3

3.45

DDQ

I/O Supply Voltage

(3)

3.15

3.3

3.45

Ground

Input High Voltage
(Address & Control Inputs)

(3)

2.0

____

DDQ

+ 150mV

(2)

Input High Voltage - I/O

(3)

2.0

____

DDQ

+ 150mV

(2)

Input Low Voltage

-0.3

(1)

____

0.8

5630 tbl 05b

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V ± 150mV)

NOTES:
1. At V

< 2.0V leakages are undefined.

2. V

DDQ

is selectable (3.3V/2.5V) via OPT pins. Refer to p.5 for details.

Symbol

Parameter

Test Conditions

70V7399S

Unit

Min.

Max.

Input Leakage Current

(1)

DDQ

= Max., V

= 0V to V

DDQ

___

µ A

Output Leakage Current

(1)

= V

or CE

= V

, V

OUT

= 0V to V

DDQ

___

µ A

(3.3V)

Output Low Voltage

(2)

= +4mA, V

DDQ

= Min.

___

0.4

(3.3V)

Output High Voltage

(2)

= -4mA, V

DDQ

= Min.

2.4

___

(2.5V)

Output Low Voltage

(2)

= +2mA, V

DDQ

= Min.

___

0.4

(2.5V)

Output High Voltage

(2)

= -2mA, V

DDQ

= Min.

2.0

___

5630 tbl 08

NOTES:
1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

(1)

= +25°C, F = 1.0MH

) PQFP ONLY

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

10.5

5630 tbl 07

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(5)

= 3.3V ± 150mV)

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V

= 3.3V, T

= 25°C for Typ, and are not production tested. I

DD DC

(f=0)

= 120mA (Typ).

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

< 0.2V

"X" represents "L" for left port or "R" for right port.

70V 7399S200

(7)

Com 'l O nly

70V 7399S166

(6)

Com 'l

& Ind

70V 7399S133

Com 'l

& Ind

Sym bol

P aram eter

Test Condition

Version

Typ.

(4)

M ax.

Typ.

(4)

M ax.

Typ.

(4)

M ax.

Unit

Dy nam ic O p e rating
C urre nt (B o th
P o rts A c tiv e )

and

= V

O utp uts Dis ab le d ,

f = f

M A X

(1 )

C OM 'L

815

950

675

790

550

645

m A

IND

____

675

830

550

675

S B1

S tand b y C urre nt
(B o th P o rts - TTL
Le v e l Inp uts )

= V

f = f

M A X

(1 )

C OM 'L

340

410

275

340

250

295

m A

IND

____

275

355

250

310

S B2

S tand b y C urre nt
(One P o rt - TTL
Le v e l Inp uts )

"A "

= V

and

"B "

= V

(3 )

A c tiv e P o rt Outp uts D isab le d ,
f= f

M A X

(1 )

C OM 'L

690

770

515

640

460

520

m A

IND

____

515

660

460

545

S B3

F ull S tand b y C urre nt
(B o th P o rts - C M O S
Le v e l Inp uts )

B o th P o rts

and

> V

- 0.2V, V

> V

- 0.2V

o r V

< 0.2 V, f = 0

(2 )

C OM 'L

m A

IND

____

S B4

F ull S tand b y C urre nt
(One P o rt - CM OS
Le v e l Inp uts )

"A "

< 0.2V and

"B "

> V

- 0.2V

(3 )

> V

- 0.2V o r V

< 0.2V

A c tiv e P o rt, O utp uts D isab le d , f = f

M A X

(1 )

C OM 'L

690

770

515

640

460

520

m A

IND

____

515

660

460

545

5630 tb l 0 9

6. 166MHz Industrial Temperature not available in BF-208 package.
7. This speed grade available when V

DDQ

= 3.3.V for a specific port (i.e., OPTx = V

). This speed grade available in BC-256 package only.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

DDQ

- 3.3V/2.5V)

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For t

CKLZ

, t

CKHZ

, t

OLZ

, and t

OHZ

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

Input Pulse Levels (Address & Controls)

Input Pulse Levels (I/Os)

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3

0V/GND to 2.4V

GND to 3.0V/GND to 2.4V

2ns

1.5V/1.25V

Figures 1 and 2

5630 tbl 10

1.5V/1.25

5630 drw 03

10pF
(Tester)

DATA

OUT

5630 drw 04

590

5pF*

435

3.3V

DATA

OUT

833

5pF*

770

2.5V

DATA

OUT

-1

20.5

100

200

10.5pF is the I/O capacitance of this
device, and 10pF is the AC Test Load
Capacitance.

Capacitance (pF)

tCD

(Typical, ns)

5630 drw 05

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)

(2,3)

= 3.3V ± 150mV, T

= 0°C to +70°C)

NOTES:
1. The Pipelined output parameters (t

CYC2

, t

CD2

) apply to either or both left and right ports when PL/

= V

. Flow-through parameters (t

CYC1

, t

CD1

) apply when

PL/

= V

for that port.

2. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (

OE) and PL/FT

PL/

should be treated as a

DC signal, i.e. steady state during operation.

3. These values are valid for either level of V

DDQ

(3.3V/2.5V). See page 5 for details on selecting the desired operating voltage levels for each port.

70V7399S200

(5)

Com'l Only

70V7399S166

(3,4)

Com'l

& Ind

70V7399S133

(3)

Com'l

& Ind

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

C Y C 1

Clo ck Cycle Time (Flo w-Thro ug h)

(1)

____

C Y C 2

Clo ck Cycle Time (P ip e line d)

(1)

____

7.5

____

C H 1

Clo ck Hig h Time (Flo w-Thro ug h)

(1)

____

CL 1

Clo ck Lo w Tim e (Flow-Thro ugh)

(1)

____

C H 2

Clo ck Hig h Time (P ip e line d)

(2)

2.0

____

2.1

____

2.6

____

CL 2

Clo ck Lo w Tim e (P ipe line d )

(1)

2.0

____

2.1

____

2.6

____

Clo ck Rise Time

____

1.5

____

1.5

____

1.5

Clo ck Fall Time

____

1.5

____

1.5

____

1.5

S A

A d dre ss Se tup Tim e

1.5

____

1.7

____

1.8

____

H A

A d dre ss Ho ld Tim e

0.5

____

0.5

____

0.5

____

S C

Chip E nab le S e tup Time

1.5

____

1.7

____

1.8

____

H C

Chip E nab le Ho ld Time

0.5

____

0.5

____

0.5

____

S W

R/W S e tup Time

1.5

____

1.7

____

1.8

____

H W

R/W Ho ld Time

0.5

____

0.5

____

0.5

____

S D

Inp ut Data S e tup Time

1.5

____

1.7

____

1.8

____

H D

Input Data Ho ld Tim e

0.5

____

0.5

____

0.5

____

SA D

ADS Setup Time

1.5

____

1.7

____

1.8

____

HA D

ADS Hold Time

0.5

____

0.5

____

0.5

____

SC N

CNTEN Setup Time

1.5

____

1.7

____

1.8

____

HC N

CNTEN Hold Time

0.5

____

0.5

____

0.5

____

S R P T

REPEAT Setup Time

1.5

____

1.7

____

1.8

____

H R P T

REPEAT Hold Time

0.5

____

0.5

____

0.5

____

Outp ut Enab le to Data Valid

____

4.0

____

4.0

____

4.2

OL Z

Outp ut Enab le to Outp ut Lo w-Z

0.5

____

0.5

____

0.5

____

O H Z

Outp ut Enab le to Outp ut Hig h-Z

3.4

3.6

4.2

C D 1

Clo ck to Data Valid (Flo w-Thro ug h)

(1)

____

C D 2

Clo ck to Data Valid (Pip e lined )

(1)

____

3.4

____

3.6

____

4.2

D C

Data Output Ho ld A fte r Clo ck Hig h

____

C K H Z

Clo ck Hig h to Outp ut Hig h-Z

3.4

3.6

4.2

C KL Z

Clo ck Hig h to Outp ut Lo w-Z

0.5

____

0.5

____

0.5

____

Port-to-Port Delay

Clo ck-to -Clo ck Offse t

5.0

____

6.0

____

7.5

____

5 630 tb l 11

4. 166MHz Industrial Temperature not available in BF-208 package.
5. This speed grade available when V

DDQ

= 3.3.V for a specific port (i.e., OPTx = V

). This speed grade available in BC-256 package only.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

An + 1

An + 2

An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(3)

DATA

OUT

CD2

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

5630 drw 06

(1)

(4)

(1 Latency)

(5)

Timing Waveform of Read Cycle for Pipelined Operation

(ADS Operation) (FT/PIPE

'X'

= V

)

(2)

NOTES:
1.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

ADS = V

CNTEN and REPEAT = V

3. The output is disabled (High-Impedance state) by

= V

, CE

= V

UB/LB = V

following the next rising edge of the clock. Refer to

Truth Table 1.

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

5. If

UB/LB was HIGH, then the appropriate Byte of DATA

OUT

for Qn + 2 would be disabled (High-Impedance state).

6. "x" denotes Left or Right port. The diagram is with respect to that port.

Timing Waveform of Read Cycle for Flow-through Output

(FT/PIPE

"X"

= V

)

(2,6)

An + 1

An + 2

An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

CKHZ

5630 drw 07

(5)

(1)

(3)

(4)

(5)

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

0(B1)

ADDRESS

(B1)

CLK

DATA

OUT(B1)

CH2

CL2

CYC2

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

CKHZ

CKLZ

CD2

5630 drw 08

Timing Waveform of a Multi-Device Pipelined Read

(1,2)

NOTES:
1. B1 Represents Device #1; B2 Represents Device #2. Each Device consists of one IDT70V7399 for this waveform,
and are setup for depth expansion in this example. ADDRESS

(B1)

= ADDRESS

(B2)

in this situation.

UB/LB, OE, and ADS = V

; CE

1(B1)

, CE

1(B2)

, R/

W, CNTEN, and REPEAT = V

Timing Waveform of a Multi-Device Flow-Through Read

(1,2)

0(B1)

ADDRESS

(B1)

CLK

5630 drw 09

CD1

CKLZ

CKHZ

(1)

DATA

OUT(B1)

CH1

CL1

CYC1

(1)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD1

CKHZ

CD1

CKLZ

(1)

CKHZ

(1)

CKLZ

(1)

CD1

CKLZ

(1)

CKHZ

(1)

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

CLK

"A"

BANK ADDRESS

AND ADDRESS

"A"

DATA

IN"A"

CLK

"B"

BANK ADDRESS

AND ADDRESS

"B"

DATA

OUT"B"

CD2

5630 drw 10

(3)

Timing Waveform of Port A Write to Pipelined Port B Read

(1,2,4)

Timing Waveform with Port-to-Port Flow-Through Read

(1,2,4)

DATA

IN "A"

CLK

"B"

BANK ADDRESS

AND ADDRESS

"A"

CLK

"A"

BANK ADDRESS

AND ADDRESS

"B"

DATA

OUT "B"

5630 drw 11

CD1

(3)

NOTES:
1.

, and

ADS = V

; CE

CNTEN, and REPEAT = V

OE = V

for Port "B", which is being read from.

OE = V

for Port "A", which is being written to.

3. If t

< minimum specified, then operations from both ports are INVALID. If t

minimum, then data from Port "B" read is available on first Port "B" clock cycle

(ie, time from write to valid read on opposite port will be t

+ t

CYC2

+ t

CD2

4. All timing is the same for Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite of Port "A"

NOTES:
1.

BEn, and ADS = V

; CE

CNTEN, and REPEAT = V

OE = V

for the Right Port, which is being read from.

OE = V

for the Left Port, which is being written to.

3. If t

< minimum specified, then operations from both ports are INVALID. If t

minimum, then data from Port "B" read is available on first Port "B" clock cycle

(i.e., time from write to valid read on opposite port will be t

+ t

CD1

4. All timing is the same for both left and right ports. Port "A" may be either left or right port. Port "B" is the opposite of Port "A".

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

5630 drw 12

Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ

NOP

READ

(3)

(1)

WRITE

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read

(OE = V

)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.

UB/LB, and ADS = V

; CE

CNTEN, and REPEAT = V

. "NOP" is "No Operation".

3. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.
4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

DATA

Dn + 3

Dn + 2

CLK

5630 drw 13

DATA

OUT

Qn + 4

CH2

CL2

CYC2

CKLZ

CD2

OHZ

CD2

READ

WRITE

READ

(3)

(1)

(4)

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.

UB/LB, and ADS = V

; CE

CNTEN, and REPEAT = V

3. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference

use only.

4. This timing does not meet requirements for fastest speed grade. This waveform indicates how logically it could be done if timing so allows.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = V

)

(2)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)

(2)

NOTES:
1. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
2.

UB/LB, and ADS = V

; CE

CNTEN, and REPEAT = V

3. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

4. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

5630 drw 14

DATA

OUT

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ

NOP

READ

CKLZ

(3)

(1)

WRITE

(4)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

(3)

DATA

Dn + 2

CLK

5630 drw 15

DATA

OUT

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ

WRITE

READ

CKLZ

(1)

Dn + 3

OHZ

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

CLK

DATA

OUT

Qx - 1

(2)

Qn + 2

(2)

Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

5630 drw 16

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1

Timing Waveform of Pipelined Read with Address Counter Advance

(1)

NOTES:
1.

OE, UB/LB = V

; CE

, R/

W, and REPEAT = V

2. If there is no address change via

ADS = V

(loading a new address) or

CNTEN = V

(advancing the address), i.e.

ADS = V

and

CNTEN = V

, then

the data output remains constant for subsequent clocks.

Timing Waveform of Flow-Through Read with Address Counter Advance

(1)

ADDRESS

CLK

DATA

OUT

(2)

Qn + 1

Qn + 2

Qn + 3

(2)

Qn + 4

ADS

CNTEN

CYC1

CH1

CL1

5630 drw 17

SAD

HAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

CD1

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Write with Address Counter Advance

(Flow-through or Pipelined Inputs)

(1,6)

NOTES:
1.

UB/LB, and R/W = V

; CE

and

REPEAT = V

2. CE

UB/LB = V

; CE

= V

3. The "Internal Address" is equal to the "External Address" when

ADS = V

and equals the counter output when

ADS = V

4. No dead cycle exists during

REPEAT operation. A READ or WRITE cycle may be coincidental with the counter REPEAT cycle: Address loaded by last valid

ADS load will be accessed. For more information on REPEAT function refer to Truth Table II.

CNTEN = V

advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance. The `An +1'Address is

written to during this cycle.

6. The counter includes bank address and internal address. The counter will advance across bank boundaries. For example, if the counter is in Bank 0, at address

FFFh, and is advanced one location, it will move to address 0h in Bank 1. By the same token, the counter at FFFh in Bank 63 will advance to 0h in Bank 0.

7. For Pipelined Mode user should add 1 cycle latency for outputs as per timing waveform of read cycle for pipelined operations.

ADDRESS

CLK

DATA

Dn + 1

Dn + 2

ADS

CNTEN

CH2

CL2

CYC2

5630 drw 18

INTERNAL

(3)

ADDRESS

(5)

An + 1

An + 2

An + 3

An + 4

Dn + 3

Dn + 4

SAD

HAD

WRITE

COUNTER HOLD

WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

SCN

HCN

Timing Waveform of Counter Repeat for Flow Through Mode

(2,6,7)

ADDRESS

CYC2

CLK

DATA

REPEAT

5630 drw 19

INTERNAL

(3)

ADDRESS

ADS

CNTEN

WRITE TO

ADS

ADDRESS

ADVANCE
COUNTER
WRITE TO

An+1

ADVANCE
COUNTER
WRITE TO

An+2

HOLD

COUNTER
WRITE TO

An+2

REPEAT

READ LAST

ADS

ADDRESS

DATA

OUT

SAD

HAD

SCN

HCN

SRPT

HRPT

CD1

An+1

An+2

An+1

An+2

An+1

An+2

ADVANCE
COUNTER

READ

An+1

ADVANCE
COUNTER

READ

An+2

HOLD

COUNTER

READ

An+2

(4)

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Functional Description

The IDT70V7399 is a high-speed 128Kx18 (2 Mbit) synchronous

Bank-Switchable Dual-Ported SRAM organized into 64 independent
2Kx18 banks. Based on a standard SRAM core instead of a traditional true
dual-port memory core, this bank-switchable device offers the benefits of
increased density and lower cost-per-bit while retaining many of the
features of true dual-ports. These features include simultaneous, random
access to the shared array, separate clocks per port, 166 MHz operating
speed, full-boundary counters, and pinouts compatible with the IDT70V3319
(256Kx18) dual-port family.

The two ports are permitted independent, simultaneous access into

separate banks within the shared array. Access by the ports into specific
banks are controlled by the bank address pins under the user's direct
control: each port can access any bank of memory with the shared array
that is not currently being accessed by the opposite port (i.e., BA

- BA

). In the event that both ports try to access the same bank

at the same time, neither access will be valid, and data at the two specific
addresses targeted by the ports within that bank may be corrupted (in the
case that either or both ports are writing) or may result in invalid output (in
the case that both ports are trying to read).

The IDT70V7399 provides a true synchronous Dual-Port Static RAM

5630 drw 20

IDT70V7399

(1)

IDT70V7399

Control Inputs

CLK,

ADS

REPEAT

CNTEN

Figure 4. Depth and Width Expansion with IDT70V7399

interface. Registered inputs provide minimal setup and hold times on
address, data and all critical control inputs.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to stall the
operation of the address counters for fast interleaved memory applications.

A HIGH on

or a LOW on CE

for one clock cycle will power down

the internal circuitry on each port (individually controlled) to reduce static
power consumption. Dual chip enables allow easier banking of multiple
IDT70V7399s for depth expansion configurations. Two cycles are
required with

LOW and CE

HIGH to read valid data on the outputs.

Depth and Width Expansion

The IDT70V7399 features dual chip enables (refer to Truth

Table I) in order to facilitate rapid and simple depth expansion with no
requirements for external logic. Figure 4 illustrates how to control the
various chip enables in order to expand two devices in depth.

The IDT70V7399 can also be used in applications requiring expanded

width, as indicated in Figure 4. Through combining the control signals, the
devices can be grouped as necessary to accommodate applications
needing 36-bits or wider.

NOTE:
1. In the case of depth expansion, the additional address pin logically serves as an extension of the bank address. Accesses by the ports into specific banks are

controlled by the bank address pins under the user's direct control: each port can access any bank of memory within the shared array that is not currently
being accessed by the opposite port (i.e., BA

- BA

). In the event that both ports try to access the same bank at the same time, neither

access will be valid, and data at the two specific addresses targeted by the parts within that bank may be corrupted (in the case that either or both parts are
writing) or may result in invalid output (in the case that both ports are trying to read).

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

JTAG AC Electrical

Characteristics

(1,2,3,4)

70V7399

Symbol

Parameter

Min.

Max.

Units

JCYC

JTAG Clock Input Period

100

____

JCH

JTAG Clock HIGH

____

JCL

JTAG Clock Low

____

JTAG Clock Rise Time

____

(1)

JTAG Clock Fall Time

____

(1)

JRST

JTAG Reset

____

JRSR

JTAG Reset Recovery

____

JCD

JTAG Data Output

____

JDC

JTAG Data Output Hold

____

JTAG Setup

____

JTAG Hold

____

5630 tbl 12

NOTES:
1. Guaranteed by design.
2. 30pF loading on external output signals.
3. Refer to AC Electrical Test Conditions stated earlier in this document.
4. JTAG operations occur at one speed (10MHz). The base device may run at

any speed specified in this datasheet.

JTAG Timing Specifications

TCK

Device Inputs

(1)

TDI/TMS

Device Outputs

(2)

TDO

TRST

JCD

JDC

JRST

JCYC

JRSR

JCL

JCH

5630 drw 21

Figure 5. Standard JTAG Timing

NOTES:
1. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.
2. Device outputs = All device outputs except TDO.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Identification Register Definitions

Instruction Field

Value

Description

Revision Number (31:28)

0x0

Reserved for version number

IDT Device ID (27:12)

0x321

Defines IDT part number

IDT JEDEC ID (11:1)

0x33

Allows unique identification of device vendor as IDT

ID Register Indicator Bit (Bit 0)

Indicates the presence of an ID register

5630 tbl 13

Scan Register Sizes

Register Name

Bit Size

Instruction (IR)

Bypass (BYR)

Identification (IDR)

Boundary Scan (BSR)

Note (3)

5630 tbl 14

System Interface Parameters

Instruction

Code

Description

EXTEST

0000

Forces contents of the bound ary scan cells onto the device outputs

(1)

Places the boundary scan registe r (BSR) between TDI and TDO.

BYPASS

1111

Places the bypass registe r (BYR) between TDI and TDO.

IDCODE

0010

Loads the ID register (IDR) with the vendor ID code and places the
register between TDI and TDO.

HIGHZ

0100

Places the bypass register (BYR) between TDI and TDO. Forces all
device output drivers to a High-Z state.

CLAMP

0011

Uses BYR. Forces contents of the bound ary scan cells onto the device
outputs. Places the bypass registe r (BYR) between TDI and TDO.

SAMPLE/PRELOAD

0001

Places the boundary scan registe r (BSR) between TDI and TDO.
SAMPLE allows data from device inputs

(2)

and outputs

(1)

to be captured

in the boundary scan cells and shifted serially through TDO. PRELOAD
allows data to be input serially into the b oundary scan cells via the TDI.

RESERVED

All other codes

Several combinations are reserved. Do not use codes other than those
identified above.

5630 tbl 15

NOTES:
1. Device outputs = All device outputs except TDO.
2. Device inputs = All device inputs except TDI, TMS, TRST, and TCK.
3. The Boundary Scan Descriptive Language (BSDL) file for this device is available on the IDT website (www.idt.com), or by contacting your local

IDT sales representative.

6.42

IDT70V7399S
High-Speed 128K x 18 Synchronous Bank-Switchable Dual-Port Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

Power

999

Speed

Package

Process/

Temperature

Range

Blank
I

Commercial (0°C to +70°C)

Industrial (-40°C to +85°C)

DD
BC

208-pin fpBGA (BF-208)

144-pin TQFP (DD-144)

256-pin BGA (BC-256)

200

166

133

XXXXX

Device

Type

IDT

Speed in Megahertz

5630 drw 22

Standard Power

70V7399 2Mbit (128K x 18-Bit) Synchronous Bank-Switchable Dual-Port RAM

Commercial Only

(1)

Commercial & Industrial

(2)

Commercial & Industrial

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-5166

831-754-4613

Santa Clara, CA 95054

fax: 408-492-8674

DualPortHelp@idt.com

www.idt.com

Datasheet Document History:

1/5/00:

Initial Public Offering

6/20/01:

Page 1 Added JTAG information for TQFP package

Pages 4 & 22 Changed TQFP package from DA to DD
Corrected Pin number on TQFP package from 100 to 110
Page 20 Increased t

JCD

from 20ns to 25ns

8/6/01:

Page 4 Changed body size for DD package from 22mm x 22mm x1.6mm to 20mm x 20mm x 1.4mm

Page 9 Changed I

values for commercial and industrial DC Electrical Characteristics

11/20/01:

Page 2, 3 & 4 Added date revision for pin configurations

Page 11 Changed t

value in AC Electrical Characteristics, please refer to Errata #SMEN-01-05

Page 1 & 22 Replaced

logo with ® logo

3/18/02:

Page 1, 9, 11 & 22 Added 200MHz specification

Page 9 Tightened power numbers in DC Electrical Characteristics
Page 14 Changed waveforms to show INVALID operation if t

< minimum specified

Page 1 - 22 Removed "Preliminary" status

12/4/02:

Page 9 , 11& 22 Designated 200Mhz speed grade in BC-256 package only.

NOTES:
1. Available in BC-256 package only.
2. Industrial Temperature at 166Mhz not available in BF-208 package.

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