1999 Integrated Device Technology, Inc.
JUNE 1999
DSC 3753/4
1
Functional Block Diagram
Features:
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
High-speed clock to data access
Commercial: 9/12/15ns (max.)
x
Low-power operation
IDT70V9079S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
IDT70V9079L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
x
Flow-Through or Pipelined output mode on Right Port via
the FT/PIPE
R
pin
x
Counter enable and reset features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
4ns setup to clock and 1ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 9ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
15ns cycle time, 66MHz operation in the Pipelined output mode
x
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x
LVTTL- compatible, single 3.3V (0.3V) power supply
x
Industrial temperature range (40C to +85C) is
available for selected speeds
x
Available in a 100 pin Thin Quad Flatpack (TQFP)
HIGH-SPEED 3.3V 32K x 8
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
IDT70V9079S/L
R/
W
R
OE
R
CE
0R
CE
1R
FT
/PIPE
R
0
1
0/1
I/O
Control
MEMORY
ARRAY
Counter/
Address
Reg.
I/O
Control
3753 drw 01
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
A
0L
CLK
L
ADS
L
A
14L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
R/
W
L
CE
0L
OE
L
CE
1L
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
1
0/1
0
6.42
IDT70V9079S/L Preliminary
High Speed 3.3V 32K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
2
Description:
The IDT70V9079 is a high-speed 32K x 8 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
Pin Configurations
(1,2,3)
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
IDT70V9079PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
GND
FT
/PIPE
R
OE
R
R/
W
R
CNTRST
R
CE
1R
CE
0R
NC
NC
GND
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
NC
3753 drw 02
NC
NC
V
CC
OE
L
R/
W
L
CNTRST
L
CE
1L
CE
0L
NC
NC
NC
V
CC
NC
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
I
/
O
I
L
G
N
D
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
N
C
N
C
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
C
N
T
E
N
R
C
L
K
R
A
D
S
R
A
D
S
L
C
L
K
L
C
N
T
E
N
L
A
0
L
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
NC
NC
N
C
N
C
V
C
C
G
N
D
V
C
C
G
N
D
N
C
N
C
G
N
D
N
C
N
C
With an input data register, the IDT70V9079 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very LOW standby power mode.
Fabricated using IDTs CMOS high-performance technology, these
devices typically operate on only 429mW of power.
IDT70V9079S/L Preliminary
High Speed 3.3V 32K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
3
Pin Names
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. CE
0
and OE = V
IL
; CE
1
and R/W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4. ADS is independent of all other signals including CE
0
and CE
1
.
5. The address counter advances if CNTEN = V
IL
on the rising edge of CLK, regardless of all other signals including CE
0
and CE
1
.
Truth Table IIAddress Counter Control
(1,2)
Truth Table IRead/Write and
Enable Control
(1,2,3)
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2. ADS, CNTEN, CNTRST = X.
3. OE is an asynchronous input signal.
Left Port
Right Port
Names
CE
0L
, CE
1L
CE
0R
, CE
1R
Chip Enables
R/W
L
R/W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/O
7L
I/O
0R
- I/O
7R
Data Input/Output
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
____
FT
/PIPE
R
Flow-Through/Pipeline
V
CC
Power
GND
Ground
3753 tbl 01
OE
CLK
CE
0
CE
1
R/W
I/O
0-7
Mode
X
H
X
X
High-Z
Deselected
X
X
L
X
High-Z
Deselected
X
L
H
L
DATA
IN
Write
L
L
H
H
DATA
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
3753 tbl 02
Address
Previous
Address
CLK
ADS
CNTEN
CNTRST
I/O
(3)
Mode
X
X
H
H
L
DATA
I/O
(0)
Counter Reset to Address 0
An
X
L
(4)
H
H
DATA
I/O
(n)
External Address Utilized
X
An
H
H
H
DATA
I/O
(n)
External Address BlockedCounter Disabled
X
An
H
L
(5)
H
DATA
I/O
(n+1)
Counter EnableInternal Address Generation
3753 tbl 03
6.42
IDT70V9079S/L Preliminary
High Speed 3.3V 32K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
4
Recommend DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage
(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
cc
+ 0.3V.
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
Capacitance
(T
A
= +25C, f = 1.0MH
Z
)
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact
your sales office.
NOTES:
1. V
TERM
must not exceed V
CC
+0.3V.
2. V
IL
> -1.5V for pulse width less than 10ns.
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
3753 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
V
CC
+ 0.3V
(2)
V
V
IL
Input Low Voltage
-0.3
(2)
____
0.8
V
3753 tbl 05
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
I
OUT
DC Output
Current
50
mA
3753 tbl 06
Symbol
Parameter
(1)
Conditions
(2)
Max. Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
3753 tbl 07
IDT70V9079S/L Preliminary
High Speed 3.3V 32K x 8 Synchronous Pipelined Dual-Port Static RAM Industrial and Commercial Temperature Ranges
5
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, TA = 25C for Typ, and are not production tested. I
CC DC
(f=0)
= 90mA (Typ).
5. CE
X
= V
IL
means CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
CC
- 0.2V means CE
0X
> V
CC
- 0.2V or CE
1X
< 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part number indicates power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(6,7)
(V
CC
= 3.3V 0.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
Symbol
Parameter
Test Conditions
70V9079S
70V9079L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.3V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
CE
0
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
3753 tbl 08
70V9079X9
Com'l Only
70V9079X12
Com'l Only
70V9079X15
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
(4)
Max.
Typ.
(4)
Max.
Typ.
(4)
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE
L
and CE
R
= V
IL
Outputs Open
f = f
MAX
(1)
COM'L
S
L
180
180
260
225
150
150
240
205
130
130
220
185
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
and CE
R
= V
IH
f = f
MAX
(1)
COM'L
S
L
50
50
75
65
40
40
65
50
30
30
55
35
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(3)
Active Port Outputs Open,
f=f
MAX
(1)
COM'L
S
L
110
110
170
150
100
100
160
140
90
90
150
130
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB3
Full Standby Current
(Both Ports -
CMOS Level Inputs)
Both Ports CE
R
and
CE
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
COM'L
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB4
Full Standby Current
(One Port -
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port
Outputs Open, f = f
MAX
(1)
COM'L
S
L
100
100
160
140
90
90
150
130
80
80
140
120
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
3753 tbl 09
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