2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-5645/1
1
.unctional Block Diagram
.eatures:
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
High-speed clock to data access
Commercial: 7.5/9/12ns (max.)
Industrial: 9ns (max)
x
Low-power operation
IDT70V9179L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE pins
x
Counter enable and reset features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
4ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode
x
LVTTL- compatible, single 3.3V (0.3V) power supply
x
Industrial temperature range (40C to +85C) is
available for selected speeds
x
Available in a 100-pin Thin Quad Flatpack (TQFP)
IDT70V9179L
R/
W
R
OE
R
CE
0R
CE
1R
FT
/PIPE
R
0
1
0/1
I/O
Control
MEMORY
ARRAY
Counter/
Address
Reg.
I/O
Control
5645 drw 01
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
A
0L
CLK
L
ADS
L
A
14L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
R/
W
L
CE
0L
OE
L
CE
1L
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
1
0/1
0
1
0/1
0
0/1
1
0
FT
/PIPE
L
HIGH-SPEED 3.3V 32K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
6.42
IDT70V9179L
High-Speed 3.3V 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Preliminary
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
V
s
s
Vss
FT
/PIPE
R
OE
R
R/
W
R
CNTRST
R
CE
1R
CE
0R
NC
NC
Vss
A
12R
A
13R
A
11R
A
10R
A
9R
A
8R
A
7R
NC
NC
A
14R
NC
NC
5645 drw 02
NC
NC
FT
/PIPE
L
OE
L
R/
W
L
CNTRST
L
CE
1L
CE
0L
NC
NC
NC
V
DD
A
14L
A
13L
A
8L
A
7L
NC
NC
NC
A
12L
A
11L
A
10L
A
9L
I
/
O
6
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
0
R
I
/
O
0
L
I
/
O
1
L
V
s
s
I
/
O
2
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
3
L
I
/
O
1
R
I
/
O
7
R
I
/
O
8
L
I
/
O
8
R
A
6
R
A
5
R
A
4
R
A
3
R
A
2
R
A
1
R
A
0
R
C
N
T
E
N
R
C
L
K
R
A
D
S
R
A
D
S
L
C
L
K
L
C
N
T
E
N
L
A
0
L
A
2
L
A
3
L
A
5
L
A
6
L
A
1
L
A
4
L
N
C
N
C
V
D
D
V
s
s
V
D
D
V
s
s
V
s
s
N
C
N
C
N
C
70V9179PF
PN100-1
(4)
100-Pin TQFP
Top View
(5)
NC
NC
NC
NC
NC
Description:
The IDT70V9179 is a high-speed 32K x 9 bit synchronous Dual-
Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.
Pin Configuration
(1,2,3)
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
With an input data register, the IDT70V9179 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 500mW of power.
6.42
IDT70V9179L
High-Speed 3.3V 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
Preliminary
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST = X.
3.
OE is an asynchronous input signal.
Truth Table IRead/Write and Enable Control
(1,2,3)
Pin Names
Left Port
Right Port
Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip Enables
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/O
8L
I/O
0R
- I/O
8R
Data Input/Output
CLK
L
CLK
R
Clock
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
DD
Power (3.3V)
V
SS
Ground (0V)
5645 tbl 01
OE
CLK
CE
0
CE
1
R/
W
I/O
0-8
MODE
X
H
X
X
High-Z
DeselectedPower Down
X
X
L
X
High-Z
DeselectedPower Down
X
L
H
L
DATA
IN
Write
L
L
H
H
DATA
OUT
Read
H
X
L
H
X
High-Z
Outputs Disabled
5645 tbl 02
Truth Table IIAddress Counter Control
(1,2,6)
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
and
OE = V
IL
; CE
1
and R/
W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS and CNTRST are independent of all other signals including CE
0
and CE
1
.
5. The address counter advances if
CNTEN = V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
and CE
1
.
6. While an external address is being loaded (
ADS = V
IL
), R/
W = V
IH
is recommended to ensure data is not written arbitrarily.
Address
Previous
Address
Addr
Used
CLK
(6
)
ADS
CNTEN
CNTRST
I/O
(3)
MODE
An
X
An
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled--Internal Address generation
X
An + 1
An + 1
H
H
H
D
I/O
(n+1)
External Addre ss Blocked--Counter disabled (An + 1 reused)
X
X
Ao
X
X
L
(4)
D
I/O
(0)
Counter Reset to Address 0
5645 tbl 03
6.42
IDT70V9179L
High-Speed 3.3V 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Preliminary
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V 0.3V)
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
Capacitance
(1)
(T
A
= +25C, f = 1.0MH
Z
)
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
Grade
Ambient
Temperature
(1)
GND
V
DD
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
5645 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
2.0V
____
V
DD
+0.3V
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5645 tbl 05
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current
50
mA
5645 tbl 06
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
5645 tbl 07
Symbol
Parameter
Test Conditions
70V9179L
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
DD
= 3.6V, V
IN
= 0V t
o
V
DD
___
5
A
|I
LO
|
Output Leakage Current
CE = V
IH
or CE
1
= V
IL
, V
OUT
= 0V t
o
V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
V
5645 tbl 08
6.42
IDT70V9179L
High-Speed 3.3V 32K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
Preliminary
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(3)
(V
DD
= 3.3V 0.3V)
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
DD
= 3.3V, T
A
= 25C for Typ, and are not production tested. I
DD
DC
(f=0)
= 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
DD
- 0.2V
CE
X
> V
DD
- 0.2V means
CE
0X
> V
DD
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
70V9179L7
Com'l Only
70V9179L9
Com'l
& Ind
70V9179L12
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
(4)
Max.
Typ.
(4)
Max.
Typ.
(4)
Max.
Unit
I
DD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
COM'L
L
200
310
180
260
150
230
mA
IND
L
____
____
180
280
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
COM'L
L
65
130
50
100
40
80
mA
IND
L
____
____
50
120
____
____
I
SB2
Standby
Current (One
Port - TTL
Level Inputs)
CE
"A "
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs
Disabled, f=f
MAX
(1)
COM'L
L
140
245
110
190
100
175
mA
IND
L
____
____
110
205
____
____
I
SB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports
CE
L
and
CE
R
> V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
COM'L
L
0.4
3
0.4
3.0
0.4
3
mA
IND
L
____
____
0.4
6.0
____
____
I
SB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE
"A "
< 0.2V and
CE
"B "
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, Active Port,
Outputs Disabled, f = f
MAX
(1)
COM'L
L
130
235
100
180
90
165
mA
IND
L
____
____
100
195
____
____
5645 tbl 09
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