JANUARY 2001

DSC-4860/2

Functional Block Diagram

Features:

True Dual-Ported memory cells which allow simultaneous
access of the same memory location

High-speed clock to data access
 Commercial: 7.5/9/12ns (max.)

Low-power operation
 IDT70V9189L

Active: 500mW (typ.)
Standby: 1.5mW (typ.)

Flow-Through or Pipelined output mode on either port via
the

FT/PIPE pins

Counter enable and reset features

Dual chip enables allow for depth expansion without
additional logic

Full synchronous operation on both ports
 4ns setup to clock and 0ns hold on all control, data, and

address inputs

Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode

LVTTL- compatible, single 3.3V (±0.3V) power supply

Industrial temperature range (40°C to +85°C) is
available for selected speeds

Available in a 100-pin Thin Quad Flatpack (TQFP)

IDT70V9189L

/PIPE

0/1

I/O

Control

MEMORY

ARRAY

Counter/

Address

Reg.

I/O

Control

4860 drw 01

15R

CLK

ADS

CNTEN

CNTRST

CLK

ADS

15L

CNTEN

CNTRST

Counter/

Address

Reg.

I/O

- I/O

I/O

- I/O

0/1

/PIPE

HIGH-SPEED 3.3V 64K x 9
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Index

75
74

26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76

GND

/PIPE

CNTRST

GND

12R

13R

11R

10R

14R

4860 drw 02

/PIPE

CNTRST

14L

13L

12L

11L

10L

I
/
O

70V9189PF

PN100-1

(4)

100-Pin TQFP

Top View

(5)

15R

15L

Description:

The IDT70V9189 is a high-speed 64K x 9 bit synchronous Dual-

Port RAM. The memory array utilizes Dual-Port memory cells to
allow simultaneous access of any address from both ports. Registers on
control, data, and address inputs provide minimal setup and hold times.
The timing latitude provided by this approach allows systems to be
designed with very short cycle times.

Pin Configuration

(1,2,3)

NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.

With an input data register, the IDT70V9189 has been optimized for

applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by

and CE

permits the

on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 500mW of power.

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

ADS, CNTEN, CNTRST = X.

OE is an asynchronous input signal.

Truth Table IRead/Write and Enable Control

(1,2,3)

Pin Names

Left Port

Right Port

Names

0L,

0R,

Chip Enables

Read/Write Enable

Output Enable

- A

15L

- A

15R

Address

I/O

- I/O

I/O

- I/O

Data Input/Output

CLK

Clock

ADS

Address Strobe Enable

CNTEN

Counter Enable

CNTRST

Counter Reset

FT/PIPE

Flow-Through / Pipeline

Power

GND

Ground

4860 tbl 01

CLK

I/O

0-8

MODE

High-Z

DeselectedPower Down

High-Z

DeselectedPower Down

DATA

Write

DATA

OUT

Read

High-Z

Outputs Disabled

4860 tbl 02

Truth Table IIAddress Counter Control

(1,2,6)

NOTES:
1. "H" = V

IH,

"L" = V

IL,

"X" = Don't Care.

and

OE = V

; CE

and R/

W = V

3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.

ADS is independent of all other signals including CE

and CE

5. The address counter advances if

CNTEN = V

on the rising edge of CLK, regardless of all other signals including

and CE

6. While an external address is being loaded (

ADS = V

), R/

W = V

is recommended to ensure data is not written arbitrarily.

Address

Previous

Address

Addr
Used

CLK

(6)

ADS

CNTEN

CNTRST

I/O

(3)

MODE

(4)

I/O

(0)

Counter Reset to Address 0

(4)

I/O

(n)

External Address Used

I/O

(p)

External Address Blocked--Counter disabled (Ap reused)

Ap + 1

(5)

I/O

(p+1)

Counter Enabled--Internal Address generation

4860 tbl 03

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V ± 0.3V)

NOTE:
1. At Vcc < 2.0V input leakages are undefined.

Recommended Operating

Temperature and Supply Voltage

(1)

Recommended DC Operating

Conditions

Absolute Maximum Ratings

(1)

NOTES:
1. These parameters are determined by device characterization, but are not

production tested.

2. 3dV references the interpolated capacitance when the input and output switch

from 0V to 3V or from 3V to 0V.

3. C

OUT

also references C

I/O

Capacitance

(1)

= +25°C, f = 1.0MH

)

NOTES:
1. V

> -1.5V for pulse width less than 10 ns.

2. V

TERM

must not exceed V

+0.3V.

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

TERM

must not exceed V

+0.3V for more than 25% of the cycle time or 10ns

maximum, and is limited to < 20mA for the period of V

TERM

> V

+ 0.3V.

NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your

sales office.

2. This is the parameter T

. This is the "instant on" case temperature.

Grade

Ambient

Temperature

(2)

GND

Vcc

Commercial

C to +70

3.3V

0.3V

Industrial

-40

C to +85

3.3V

0.3V

4860 tbl 04

Symbol

Parameter

Min.

Typ.

Max.

Unit

Supply Voltage

3.0

3.3

3.6

GND

Ground

Input High Voltage

2.0V

____

+0.3V

(2)

Input Low Voltage

-0.3

(1)

____

0.8

4860 tbl 05

Symbol

Rating

Commercial

& Industrial

Unit

TERM

(2)

Terminal Voltage

with Respect to

GND

-0.5 to +4.6

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-65 to +150

OUT

DC Output Current

4860 tbl 06

Symbol

Parameter

Conditions

(2)

Max.

Unit

Input Capacitance

= 3dV

OUT

(3)

Output Capacitance

OUT

= 3dV

4860 tbl 07

Symbol

Parameter

Test Conditions

70V9189L

Unit

Min.

Max.

Input Leakage Current

(1)

= 3.6V, V

= 0V to V

___

µ A

Output Leakage Current

CE = V

or CE

= V

, V

OUT

= 0V to V

___

µ A

Output Low Voltage

= +4mA

___

0.4

Output High Voltage

= -4mA

2.4

___

4860 tbl 08

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

DC Electrical Characteristics Over the Operating

Temperature Supply Voltage Range

(3,6)

= 3.3V ± 0.3V)

NOTES:
1. At f = f

MAX

, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t

CYC

, using "AC TEST CONDITIONS" at input

levels of GND to 3V.

2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, T

= 25°C for Typ, and are not production tested. I

CC DC

(f=0)

= 90mA (Typ).

= V

means

= V

and CE

= V

means

= V

or CE

= V

< 0.2V means

< 0.2V and CE

> V

- 0.2V

> V

- 0.2V means

> V

- 0.2V or CE

< 0.2V

"X" represents "L" for left port or "R" for right port.

6. Industrial temperature: for specific speeds, packages and powers contact your sales office.

70V9189L7

Com'l Only

70V9189L9

Com'l Only

70V9189L12

Com'l Only

Symbol

Parameter

Test Condition

Version

Typ.

(4)

Max.

Typ.

(4)

Max.

Typ.

(4)

Max.

Unit

Dynamic Operating
Current (Both
Ports Active)

and

= V

Outputs Disabled,

f = f

MAX

(1)

COM'L

200

310

180

260

150

230

IND

____

SB1

Standby Current
(Both Ports - TTL
Level Inputs)

= V

f = f

MAX

(1)

COM'L

130

100

IND

____

SB2

Standby
Current (One
Port - TTL
Level Inputs)

"A"

= V

and

"B"

= V

(5)

Active Port Outputs

Disabled, f=f

MAX

(1)

COM'L

140

245

110

190

100

175

IND

____

SB3

Full Standby
Current (Both
Ports - CMOS
Level Inputs)

Both Ports

and

> V

- 0.2V,

> V

- 0.2V or

< 0.2V, f = 0

(2)

COM'L

0.4

IND

____

SB4

Full Standby
Current (One
Port - CMOS
Level Inputs)

"A"

< 0.2V and

"B"

> V

- 0.2V

(5)

> V

- 0.2V or

< 0.2V, Active Port,

Outputs Disabled, f = f

MAX

(1)

COM'L

130

235

100

180

165

IND

____

4860 tbl 09

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

AC Test Conditions

Figure 1. AC Output Test load.

Figure 2. Output Test Load

(For t

CKLZ

, t

CKHZ

, t

OLZ

, and t

OHZ

*Including scope and jig.

Figure 3. Typical Output Derating (Lumped Capacitive Load).

4860 drw 04

590

30pF

435

3.3V

DATA

OUT

590

5pF*

435

3.3V

DATA

OUT

4860 drw 03

20 40

100

60 80

120 140 160 180 200

tCD

(Typical, ns)

Capacitance (pF)

4860 drw 05

-1

- 10pF is the I/O capacitance

of this device, and 30pF is the

AC Test Load Capacitance

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

3ns Max.

1.5V

Figures 1, 2, and 3

4860 tbl 10

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

AC Electrical Characteristics Over the Operating Temperature Range

(Read and Write Cycle Timing)

(3,4)

= 3.3V ± 0.3V, T

= 0°C to +70°C)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2). This parameter is guaranteed

by device

characterization, but is not production tested.

2. The Pipelined output parameters (t

CYC2

, t

CD2

) apply to either or both the Left and Right ports when

FT/PIPE = V

. Flow-through parameters (t

CYC1

, t

CD1

) apply

when

FT/PIPE = V

for that port.

3. All input signals are synchronous with respect to the clock except for the asynchronous Output Enable (

OE), FT/PIPE

, and

FT/PIPE

4. Industrial temperature: for specific speeds, packages and powers contact your sales office.

70V9189L7

Com'l Only

70V9189L9

Com'l Only

70V9189L12

Com'l Only

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC1

Clock Cycle Time (Flow-Through)

(2)

____

CYC2

Clock Cycle Time (Pipelined)

(2)

____

CH1

Clock High Time (Flow-Through)

(2)

7.5

____

CL1

Clock Low Time (Flow-Through)

(2)

7.5

____

CH2

Clock High Time (Pipelined)

(2)

____

CL2

Clock Low Time (Pipelined)

(2)

____

Clock Rise Time

____

Clock Fall Time

____

Address Setup Time

____

Address Hold Time

____

Chip Enable Setup Time

____

Chip Enable Hold Time

____

R/W Setup Time

____

R/W Hold Time

____

Input Data Setup Time

____

Input Data Hold Time

____

SAD

ADS Setup Time

____

HAD

ADS Hold Time

____

SCN

CNTEN Setup Time

____

HCN

CNTEN Hold Time

____

SRST

CNTRST Setup Time

____

HRST

CNTRST Hold Time

____

Output Enable to Data Valid

____

OLZ

Output Enable to Output Low-Z

(1)

____

OHZ

Output Enable to Output High-Z

(1)

CD1

Clock to Data Valid (Flow-Through)

(2)

____

CD2

Clock to Data Valid (Pipelined)

(2)

____

7.5

____

Data Output Hold After Clock High

____

CKHZ

Clock High to Output High-Z

(1)

CKLZ

Clock High to Output Low-Z

(1)

____

Port-to-Port Delay

CWDD

Write Port Clock High to Read Data Delay

____

CCS

Clock-to-Clock Setup Time

____

4860 tbl 11

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Read Cycle for

Flow-Through Output (FT/PIPE

"X"

= V

)

(3,6)

Timing Waveform of Read Cycle for Pipelined Operation

(FT/PIPE

"X"

= V

)

(3,6)

An + 1

An + 2

An + 3

CYC1

CH1

CL1

ADDRESS

DATA

OUT

CLK

CD1

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

CKHZ

4860 drw 06

(1)

(2)

(4)

(5)

An + 1

An + 2

An + 3

CYC2

CH2

CL2

ADDRESS

CLK

(4)

DATA

OUT

CD2

CKLZ

Qn + 1

Qn + 2

OHZ

OLZ

4860 drw 07

(1)

(2)

(5)

(1 Latency)

(6)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2.

OE is asynchronously controlled; all other inputs are synchronous to the rising clock edge.

ADS = V

CNTEN and CNTRST = V

4. The output is disabled (High-Impedance state) by

= V

or CE

= V

following the next rising edge of the clock. Refer to Truth Table 1.

5. Addresses do not have to be accessed sequentially since ADS = V

constantly loads the address on the rising edge of the CLK; numbers

are for reference use only.

6. "X' here denotes Left or Right port. The diagram is with respect to that port.

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform with Port-to-Port Flow-Through Read

(4,5,7)

Timing Waveform of a Bank Select Pipelined Read

(1,2)

0(B1)

ADDRESS

(B1)

CLK

4860 drw 08

DATA

OUT(B1)

CH2

CL2

CYC2

(3)

ADDRESS

(B2)

0(B2)

DATA

OUT(B2)

CD2

CKHZ

CD2

CKLZ

CKHZ

CD2

CKLZ

(3)

CKHZ

(3)

CKLZ

(3)

CD2

DATA

IN "A"

CLK

"B"

ADDRESS

"A"

CLK

"A"

ADDRESS

"B"

MATCH

VALID

CWDD

CD1

DATA

OUT "B"

4860 drw 09

VALID

CD1

CCS

(6)

NOTES:
1. B1 Represents Bank #1; B2 Represents Bank #2. Each Bank consists of one IDT70V9189 for this waveform, and are setup for depth expansion in this

example. ADDRESS

(B1)

= ADDRESS

(B2)

in this situation.

OE, and ADS = V

; CE

1(B1)

, CE

1(B2)

, R/

W, CNTEN, and CNTRST = V

3. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
4.

and

ADS = V

; CE

CNTEN, and CNTRST = V

OE = V

for the Right Port, which is being read from.

OE = V

for the Left Port, which is being written to.

6. If t

CCS

< maximum specified, then data from right port READ is not valid until the maximum specified for t

CWDD

If t

CCS

> maximum specified, then data from right port READ is not valid until t

CCS

+ t

CD1

. t

CWDD

does not apply in this case.

7. All timing is the same for both Left and Right ports. Port "A" may be either Left or Right port. Port "B" is the opposite from Port "A".

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read-to-Write-to-Read (OE = V

)

(3)

Timing Waveform of Pipelined Read-to-Write-to-Read (OE Controlled)

(3)

NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with the Output Test Load (Figure 2).
2. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
3.

and

ADS = V

; CE

CNTEN, and CNTRST = V

. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

4860 drw 10

Qn + 3

DATA

OUT

CD2

CKHZ

CKLZ

CD2

CH2

CL2

CYC2

READ

NOP

READ

(4)

(2)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

DATA

Dn + 3

Dn + 2

CLK

4860 drw 11

DATA

OUT

Qn + 4

CH2

CL2

CYC2

CKLZ

(1)

CD2

OHZ

(1)

CD2

READ

WRITE

READ

(4)

(2)

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE = V

)

(3)

Timing Waveform of Flow-Through Read-to-Write-to-Read (OE Controlled)

(3)

and

ADS = V

; CE

CNTEN, and CNTRST = V

. "NOP" is "No Operation".

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for

reference use only.

5. "NOP" is "No Operation." Data in memory at the selected address may be corrupted and should be re-written to guarantee data integrity.

ADDRESS

An +1

An + 2

An + 3

An + 4

DATA

Dn + 2

CLK

4860 drw 12

DATA

OUT

CD1

Qn + 1

CH1

CL1

CYC1

CD1

CKHZ

Qn + 3

CD1

READ

NOP

READ

CKLZ

(4)

(2)

(1)

WRITE

(5)

ADDRESS

An +1

An + 2

An + 3

An + 4

An + 5

(4)

DATA

Dn + 2

CLK

4860 drw 13

DATA

OUT

CD1

CH1

CL1

CYC1

CD1

Qn + 4

CD1

READ

WRITE

READ

CKLZ

(2)

Dn + 3

OHZ

(1)

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Timing Waveform of Pipelined Read with Address Counter Advance

(1)

Timing Waveform of Flow-Through Read with Address Counter Advance

(1)

NOTES:
1.

and

OE = V

; CE

, R/

W, and CNTRST = V

2. If there is no address change via

ADS = V

(loading a new address) or

CNTEN = V

(advancing the address), i.e.

ADS = V

and

CNTEN = V

, then the data

output remains constant for subsequent clocks.

ADDRESS

CLK

DATA

OUT

Qx - 1

(2)

Qn + 2

(2)

Qn + 3

ADS

CNTEN

CYC2

CH2

CL2

4860 drw 14

SAD

HAD

CD2

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

Qn + 1

ADDRESS

CLK

DATA

OUT

(2)

Qn + 1

Qn + 2

Qn + 3

(2)

Qn + 4

ADS

CNTEN

CYC1

CH1

CL1

4860 drw 15

SAD

HAD

READ

EXTERNAL

ADDRESS

READ WITH COUNTER

COUNTER

HOLD

CD1

SAD

HAD

SCN

HCN

READ

WITH

COUNTER

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

ADDRESS

(4)

CH2

CL2

CYC2

CLK

DATA

CNTRST

4860 drw 17

INTERNAL

(3)

ADDRESS

ADS

CNTEN

SRST

HRST

COUNTER

RESET

WRITE

ADDRESS 0

READ

ADDRESS 0

READ

ADDRESS 1

READ

ADDRESS n

An + 1

An + 2

READ

ADDRESS n+1

DATA

OUT

(5)

An + 1

(6)

SAD

HAD

SCN

HCN

(6)

Timing Waveform of Write with Address Counter Advance

(Flow-Through or Pipelined Outputs)

(1)

Timing Waveform of Counter Reset (Pipelined Outputs)

(2)

ADDRESS

CLK

DATA

Dn + 1

Dn + 2

ADS

CNTEN

(7)

CH2

CL2

CYC2

4860 drw 16

INTERNAL

(3)

ADDRESS

(7)

An + 1

An + 2

An + 3

An + 4

Dn + 3

Dn + 4

SAD

HAD

WRITE

COUNTER HOLD

WRITE WITH COUNTER

WRITE

EXTERNAL

ADDRESS

WRITE

WITH COUNTER

NOTES:
1.

and R/

W = V

; CE

and

CNTRST = V

2. CE

= V

; CE

= V

3. The "Internal Address" is equal to the "External Address" when

ADS = V

and equals the counter output when

ADS = V

4. Addresses do not have to be accessed sequentially since

ADS = V

constantly loads the address on the rising edge of the CLK; numbers are for reference use only.

5. Output state (High, Low, or High-impedance) is determined by the previous cycle control signals.
6. No dead cycle exists during counter reset. A READ or WRITE cycle may be coincidental with the counter reset cycle. ADDR

will be accessed. Extra cycles

are shown here simply for clarification.

CNTEN = V

advances Internal Address from `An' to `An +1'. The transition shown indicates the time required for the counter to advance.

The `An +1' Address is written to during this cycle.

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Depth and Width Expansion

The IDT70V9189 features dual chip enables (refer to Truth Table I)

in order to facilitate rapid and simple depth expansion with no requirements
for external logic. Figure 4 illustrates how to control the varioius chip
enables in order to expand two devices in depth.

The IDT70V9189 can also be used in applications requiring expanded

width, as indicated in Figure 4. Since the banks are allocated at the
discretion of the user, the external controller can be set up to drive the input
signals for the various devices as required to allow for 18-bit or wider
applications.

4860 drw 18

IDT70V9189

Control Inputs

CNTRST

CLK

ADS
CNTEN

Figure 4. Depth and Width Expansion with IDT70V9189

Functional Description

The IDT70V9189 provides a true synchronous Dual-Port Static RAM

interface. Registered inputs provide minimal set-up and hold times on
address, data, and all critical control inputs. All internal registers are clocked
on the rising edge of the clock signal, however, the self-timed internal write
pulse is independent of the LOW to HIGH transition of the clock signal.

An asynchronous output enable is provided to ease asynchronous

bus interfacing. Counter enable inputs are also provided to staff the
operation of the address counters for fast interleaved memory applications.

= V

or CE

= V

for one clock cycle will power down the internal

circuitry to reduce static power consumption. Multiple chip enables allow
easier banking of multiple IDT70V9189's for depth expansion configura-
tions. When the Pipelined output mode is enabled, two cycles are required
with

= V

and CE

= V

to re-activate the outputs.

6.42

IDT70V9189L
High-Speed 64K x 9 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges

Ordering Information

NOTE:
1. Industrial temperature range is available.

For specific speeds, packages and powers contact your sales office.

Power

Speed

Package

Process/

Temperature

Range

Blank
I

(1)

Commercial (0

C to +70

Industrial (-40

C to +85

100-pin TQFP (PN100-1)

7
9
12

XXXXX

Device

Type

IDT

Speed in nanoseconds

4860 drw 19

Low Power

70V9189 576K (64K x 9-Bit) Synchronous Dual-Port RAM

Commercial Only
Commercial Only
Commercial Only

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-6116

831-754-4613

Santa Clara, CA 95054

fax: 408-492-8674

DualPortHelp@idt.com

www.idt.com

Datasheet Document History

9/30/99:

Initial Public Release

11/12/99:

Replaced IDT logo

1/10/01:

Page 3

Changed information in Truth Table II

Page 4

Increased storage temperature parameters
Clarified T

parameter

Page 5

DC Electrical parameterschanged wording from "open" to "disabled"

Changed ±200mV to 0mV in notes
Removed Preliminary status

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