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Электронный компонент: 70V9279

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2000 Integrated Device Technology, Inc.
JANUARY 2001
DSC 3743/6
1
Functional Block Diagram
Features:
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
High-speed clock to data access
Commercial: 9/12/15ns (max.)
x
Low-power operation
IDT70V9279S
Active: 429mW (typ.)
Standby: 3.3mW (typ.)
IDT70V9279L
Active: 429mW (typ.)
Standby: 1.32mW (typ.)
x
Flow-through or Pipelined output mode on either port via
the
FT/PIPE pin
x
Counter enable and reset features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
4ns setup to clock and 1ns hold on all control, data,
and address inputs
Data input, address, and control registers
Fast 9ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
15ns cycle time, 66MHz operation in Pipelined output mode
x
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x
LVTTL- compatible, single 3.3V (0.3V) power supply
x
Industrial temperature range (40C to +85C) is
available for selected speeds
x
Available in a 128-pin Thin Quad Flatpack (TQFP) package
HIGH-SPEED 3.3V 32K x 16
SYNCHRONOUS
DUAL-PORT STATIC RAM
IDT70V9279S/L
1a 0a
1b 0b
0/1
b
a
1
0/1
0
0a 1a
0b 1b
0/1
a
b
1
0/1
0
FT
/PIPE
R
R/
W
R
UB
R
LB
R
CE
0R
OE
R
CE
1R
I/O
Control
MEMORY
ARRAY
I/O
Control
Counter/
Address
Reg.
3743 drw 01
A
14R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
I/O
8L
-I/O
15L
I/O
0L
-I/O
7L
I/O
8R
-I/O
15R
I/O
0R
-I/O
7R
A
0L
CLK
L
ADS
L
A
14L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
R/
W
L
UB
L
LB
L
CE
0L
OE
L
CE
1L
,
FT
/PIPE
L
6.42
IDT70V9279S/L
High-Speed 32K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
102
101
100
99
98
97
96
95
94
93
92
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
70
69
68
67
66
65
91
71
N/C
N/C
N/C
N/C
A
9R
A
8R
A
7R
A
6R
A
5R
A
4R
A
3R
A
2R
A
1R
A
0R
N/C
CNTEN
R
CLK
R
ADS
R
GND
V
CC
N/C
A
0L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
N/C
N/C
N/C
N/C
I/O
10L
I/O
9L
V
CC
N/C
I/O
8L
N/C
N/C
V
CC
I/O
7L
I/O
6L
I/O
5L
I/O
4L
GND
I/O
3L
I/O
2L
GND
I/O
1L
I/O
0L
V
CC
GND
I/O
0R
I/O
2R
I/O
1R
GND
I/O
4R
I/O
5R
I/O
6R
V
CC
I/O
7R
N/C
N/C
I/O
8R
N/C
GND
I/O
9R
I/O
10R
V
CC
I/O
3R
70V9279PRF
PK-128
(4)
128-Pin TQFP
Top View
(5)
3743 drw 02
A
1
0
R
A
1
1
R
A
1
2
R
A
1
3
R
A
1
4
R
N
/
C
N
/
C
N
/
C
L
B
R
U
B
R
C
E
0
R
C
E
1
R
C
N
T
R
S
T
R
V
C
C
G
N
D
R
/
W
R
O
E
R
F
T
/
P
I
P
E
R
G
N
D
I
/
O
1
5
R
I
/
O
1
4
R
I
/
O
1
3
R
I
/
O
1
2
R
V
C
C
V
C
C
I
/
O
1
1
R
A
1
0
L
A
1
1
L
A
1
2
L
A
1
3
L
A
1
4
L
N
/
C
N
/
C
N
/
C
L
B
L
U
B
L
C
E
0
L
C
E
1
L
C
N
T
R
S
T
L
V
C
C
G
N
D
R
/
W
L
O
E
L
F
T
/
P
I
P
E
L
G
N
D
I
/
O
1
5
L
I
/
O
1
4
L
I
/
O
1
3
L
I
/
O
1
2
L
V
C
C
G
N
D
I
/
O
1
1
L
3
9
4
0
4
1
4
2
4
3
4
4
4
5
4
6
4
7
4
8
4
9
5
0
5
1
5
2
5
3
5
4
5
5
5
6
5
7
5
8
5
9
6
0
6
1
6
2
6
3
6
4
1
2
8
1
2
7
1
2
6
1
2
5
1
2
4
1
2
3
1
2
2
1
2
1
1
2
0
1
1
9
1
1
8
1
1
7
1
1
6
1
1
5
1
1
4
1
1
3
1
1
2
1
1
1
1
1
0
1
0
9
1
0
8
1
0
7
1
0
6
1
0
5
1
0
4
1
0
3
CNTEN
L
CLK
L
ADS
L
Description:
The IDT70V9279 is a high-speed 32K x 16 bit synchronous Dual-Port
RAM. The memory array utilizes Dual-Port memory cells to allow
simultaneous access of any address from both ports. Registers on control,
data, and address inputs provide minimal setup and hold times. The timing
latitude provided by this approach allows systems to be designed with very
short cycle times.
Pin Configuration
(1,2,3)
NOTES:
1. All Vcc pins must be connected to power supply.
2. All GND pins must be connected to ground.
3. Package body is approximately 14mm x 20mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
With an input data register, the IDT70V9279 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 429mW of power.
6.42
IDT70V9279S/L
High-Speed 32K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
3
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST = X.
3.
OE is an asynchronous input signal.
Truth Table IRead/Write and Enable Control
(1,2,3)
Pin Names
Left Port
Right Port
Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip Enables
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
14L
A
0R
- A
14R
Address
I/O
0L
- I/O
15L
I/O
0R
- I/O
15R
Data Input/Output
CLK
L
CLK
R
Clock
UB
L
UB
R
Upper Byte Select
LB
L
LB
R
Lower Byte Select
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
CC
Power
GND
Ground
3743 tbl 01
OE
CLK
CE
0
CE
1
UB
LB
R/
W
Upper Byte
I/O
8-15
Lower Byte
I/O
0-7
MODE
X
H
X
X
X
X
High-Z
High-Z
DeselectedPower Down
X
X
L
X
X
X
High-Z
High-Z
DeselectedPower Down
X
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
L
H
L
H
L
D
IN
High-Z
Write to Upper Byte Only
X
L
H
H
L
L
High-Z
DATA
IN
Write to Lower Byte Only
X
L
H
L
L
L
DATA
IN
DATA
IN
Write to Both Bytes
L
L
H
L
H
H
DATA
OUT
High-Z
Read Upper Byte Only
L
L
H
H
L
H
High-Z
DATA
OUT
Read Lower Byte Only
L
L
H
L
L
H
DATA
OUT
DATA
OUT
Read Both Bytes
H
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
3743 tbl 02
6.42
IDT70V9279S/L
High-Speed 32K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
4
Recommended Operating
Temperature and Supply Voltage
(1,2)
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
Capacitance
(1)
(T
A
= +25C, f = 1.0MH
Z
)
Truth Table IIAddress Counter Control
(1,2)
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB, and OE = V
IL
; CE
1
and R/
W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS is independent of all other signals including CE
0
, CE
1
,
UB and LB.
5. The address counter advances if
CNTEN = V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB and LB.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
CC
+0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
CC
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 0.3V.
NOTES:
1. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
2. This is the parameter T
A
. This is the "instant on" case temperature.
Address
Previous
Address
Addr
Used
CLK
ADS
CNTEN
CNTRST
I/O
(3)
MODE
X
X
0
X
X
L
D
I/O
(0)
Counte r Reset to Address 0
An
X
An
L
(4)
X
H
D
I/O
(n)
External Address Loaded into Counter
An
Ap
Ap
H
H
H
D
I/O
(p)
External Address Blocked--Counter disabled (Ap reused)
X
Ap
Ap + 1
H
L
(5)
H
D
I/O
(p+1)
Counter Enabled--Internal Address generation
3743 tbl 03
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
3743 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
V
CC
+0.3V
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
3743 tbl 05
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current
50
mA
3743 tbl 06
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
3743 tbl 07
6.42
IDT70V9279S/L
High-Speed 32K x 16 Dual-Port Synchronous Static RAM Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(3,6,7)
(V
CC
= 3.3V 0.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
NOTE:
1. At Vcc < 2.0V input leakages are undefined.
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. Vcc = 3.3V, T
A
= 25C for Typ, and are not production tested. I
CC DC
(f=0)
= 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
CC
- 0.2V
CE
X
> V
CC
- 0.2V means
CE
0X
> V
CC
- 0.2V or CE
1X
< 0.2V
'X' represents "L" for left port or "R" for right port.
6. 'X' in part numbers indicate power rating (S or L).
7. Industrial temperature: for specific speeds, packages and powers contact your sales office.
Symbol
Parameter
Test Conditions
70V9279S
70V9279L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.6V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
CE = V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
3743 tbl 08
70V9279X9
Com'l Only
70V9279X12
Com'l Only
70V9279X15
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
(4)
Max.
Typ.
(4)
Max.
Typ.
(4)
Max.
Unit
I
CC
Dynamic
Operating
Current (Both
Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
COM'L
S
L
180
180
260
225
150
150
240
205
130
130
220
185
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB1
Standby
Current (Both
Ports - TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
COM'L
S
L
50
50
75
65
40
40
65
50
30
30
55
35
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB2
Standby
Current (One
Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(1)
COM'L
S
L
110
110
170
150
100
100
160
140
90
90
150
130
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
COM'L
S
L
1.0
0.4
5
3
1.0
0.4
5
3
1.0
0.4
5
3
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
I
SB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, Active Port,
Outputs Disabled , f = f
MAX
(1)
COM'L
S
L
100
100
160
140
90
90
150
130
80
80
140
120
mA
IND
S
L
____
____
____
____
____
____
____
____
____
____
____
____
3743 tbl 09