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Электронный компонент: 70V9349

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2002 Integrated Device Technology, Inc.
JULY 2002
DSC-5638/2
1
.unctional Block Diagram
.eatures:
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
High-speed clock to data access
Commercial: 6.5/7.5/9ns (max.)
Industrial: 7.5ns (max.)
x
Low-power operation
IDT70V9359/49L
Active: 450mW (typ.)
Standby: 1.5mW (typ.)
x
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE pins
x
Counter enable and reset features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
3.5ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 6.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
10ns cycle time, 100MHz operation in Pipelined output mode
x
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x
LVTTL- compatible, single 3.3V (0.3V) power supply
x
Industrial temperature range (40C to +85C) is
available for 83 MHz
x
Available in a 100-pin Thin Quad Flatpack (TQFP) and 100-
pin Fine Pitch Ball Grid Array (fpBGA) packages.
IDT70V9359/49L
0a 1a
0b 1b
0/1
a
b
I/O
Control
1
0/1
0
FT
/PIPE
R
R/
W
R
UB
R
LB
R
CE
0R
OE
R
CE
1R
MEMORY
ARRAY
Counter/
Address
Reg.
5638 drw 01
A
12R
(1)
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
9R
-I/O
17R
I/O
0R
-I/O
8R
A
0L
CLK
L
ADS
L
A
12L
(1)
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
R/
W
L
UB
L
LB
L
CE
0L
OE
L
CE
1L
1
0/1
0
1b 0b
1a 0a
0/1
b a
I/O
Control
FT
/PIPE
L
HIGH-SPEED 3.3V 8/4K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
NOTE:
1. A
12
is a NC for IDT70V9349.
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Preliminary
Description:
The IDT70V9359/49 is a high-speed 8/4K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
With an input data register, the IDT70V9359/49 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 450mW of power.
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
100-Pin TQFP
Top View
(6)
A
9L
A
10L
A
11L
A
12L
(1)
NC
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
R/
W
L
OE
L
V
DD
FT
/PIPE
L
I/O
16L
I/O
17L
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
5638 drw 02
A
8R
A
9R
A
10R
A
11R
A
12R
(1)
NC
NC
NC
LB
R
UB
R
CE
0R
CNTRST
R
R/
W
R
V
SS
OE
R
FT
/PIPE
R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
CE
1R
I/O
17R
V
SS
I/O
16R
I/O
15R
A
8
L
A
7
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
L
A
0
L
C
N
T
E
N
L
C
L
K
L
A
D
S
L
V
S
S
V
s
s
A
D
S
R
C
L
K
R
C
N
T
E
N
R
A
0
R
A
2
R
A
3
R
A
4
R
A
5
R
A
6
R
A
7
R
I
/
O
9
L
I
/
O
8
L
V
D
D
I
/
O
7
L
I
/
O
6
L
I
/
O
5
L
I
/
O
4
L
I
/
O
3
L
I
/
O
2
L
I
/
O
1
L
V
S
S
I
/
O
0
L
I
/
O
4
R
I
/
O
5
R
I
/
O
6
R
I
/
O
3
R
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
7
R
I
/
O
8
R
I
/
O
9
R
I
/
O
1
0
R
A
1
R
.
70V9359/49PF
PN100-1
(5)
V
SS
V
S
S
V
D
D
07/03/02
NOTES:
1. A
12
is a NC for IDT70V9349.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 14mm x 14mm x 1.4mm.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
Pin Configurations
(1,2,3,4)
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
Preliminary
70V9359/49BF
BF100
(5)
100-Pin fpBGA
Top View
(6)
C10
I/O
3R
D8
I/O
8R
C8
I/O
11R
A9
I/O
10R
D9
I/O
5R
C9
I/O
7R
B9
I/O
9R
D10
I/O
1R
C7
I/O
15R
B8
I/O
12R
A8
I/O
13R
A10
I/O
17R
D7
I/O
14R
B7
PL/
FT
R
A7
Vss
B6
OE
R
C6
I/O
16R
D6
CE
0R
A5
Vss
B5
R/
W
R
C5
CE
1R
D5
LB
R
A4
CNTRST
R
B4
C4
A
9R
D4
A
2R
A3
UB
R
B3
A
10R
C3
A
5R
D3
A
1R
D2
CLK
R
C2
A
4R
B2
A
7R
A2
A
11R
A1
A
8R
B1
A
6R
C1
A
3R
D1
A
0R
E1
Vss
E2
ADS
R
E3
CNTEN
R
E4
A
1L
F1
Vss
F2
CLK
L
F3
A
0L
F4
A
3L
G1
CNTEN
L
G2
A
4L
G3
A
7L
G4
UB
L
H1
A
2L
H2
A
6L
H3
A
11L
H4
CE
0L
J1
A
5L
J2
A
9L
J3
J4
R/
W
L
K1
A
8L
K2
A
10L
K3
LB
L
K4
CE
1L
A6
Vss
B10
I/O
6R
E5
ADS
L
E6
Vss
E7
I/O
4R
E8
I/O
2R
E9
I/O
0R
E10
V
DD
F5
V
DD
F6
Vss
F8
I/O
2L
F9
I/O
1L
F10
I/O
0L
G5
Vss
G6
I/O
13L
G7
NC
G8
I/O
4L
G9
Vss
G10
I/O
3L
H5
CNTRST
L
H6
I/O
15L
H7
I/O
9L
H8
I/O
7L
H9
I/O
6L
H10
I/O
5L
J5
OE
L
J6
PL/
FT
L
J7
I/O
12L
J8
I/O
10L
J9
Vss
J10
I/O
8L
K5
V
DD
K6
V
DD
K7
I/O
16L
K8
I/O
14L
K9
I/O
11L
K10
I/O
17L
F7
V
DD
5638 drw 03
,
A
12R
(1)
A
12L
(1)
07/03/02
NOTES:
1. A
12
is a NC for IDT70V9349.
2. All V
DD
pins must be connected to power supply.
3. All V
SS
pins must be connected to ground supply.
4. Package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch.
5. This package code is used to reference the package diagram.
6. This text does not indicate orientation of the actual part-marking.
Pin Configurations(cont'd)
(1,2,3,4)
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Preliminary
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST = X.
3.
OE is an asynchronous input signal.
Truth Table IRead/Write and Enable Control
(1,2,3)
Pin Names
Left Port
Right Port
Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip Enables
(3)
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
12L
(1)
A
0R
- A
12R
(1)
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
UB
L
UB
R
Upper Byte Select
(2)
LB
L
LB
R
Lower Byte Select
(2)
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
DD
Power (3.3V)
V
SS
Ground (0V)
5638 tbl 01
OE
CLK
CE
0
(5)
CE
1
(5)
UB
(4)
LB
(4)
R/
W
Upper Byte
I/O
9-17
Lower Byte
I/O
0-8
MODE
X
H
X
X
X
X
High-Z
High-Z
DeselectedPower Down
X
X
L
X
X
X
High-Z
High-Z
DeselectedPower Down
X
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
L
H
L
H
L
DATA
IN
High-Z
Write to Upper Byte Only
X
L
H
H
L
L
High-Z
DATA
IN
Write to Lower Byte Only
X
L
H
L
L
L
DATA
IN
DATA
IN
Write to Both Bytes
L
L
H
L
H
H
DATA
OUT
High-Z
Read Upper Byte Only
L
L
H
H
L
H
High-Z
DATA
OUT
Read Lower Byte Only
L
L
H
L
L
H
DATA
OUT
DATA
OUT
Read Both Bytes
H
X
L
H
X
X
X
High-Z
High-Z
Outputs Disabled
5638 tbl 02
NOTE:
1. A
12
is a NC for IDT70V9349.
2.
LB and UB are single buffered regardless of state of FT/PIPE.
3.
CEo and CE
1
are single buffered when
FT/PIPE = V
IL
,
CEo and CE
1
are double buffered when
FT/PIPE = V
IH
,
i.e. the signals take two cycles to deselect.
4
LB and UB are single buffered regardless of state of FT/PIPE.
5.
CEo and CE
1
are single buffered when
FT/PIPE = V
IL
.
CEo and CE
1
are double buffered when
FT/PIPE = V
IH
, i.e. the signals take two cycles to deselect.
6.42
IDT70V9359/49L
High-Speed 3.3V 8/4K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
Preliminary
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
Capacitance
(1)
(T
A
= +25C, f = 1.0MH
Z
)
Truth Table IIAddress Counter Control
(1,2)
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
External
Address
Previous
Internal
Address
Internal
Address
Used
CLK
ADS
CNTEN
CNTRST
I/O
(3)
MODE
An
X
An
L
(4)
X
H
D
I/O
(n)
Exte rnal Ad dress Used
X
An
An + 1
H
L
(5)
H
D
I/O
(n+1)
Counte r Enab le d--Internal Ad dre ss g eneration
X
An + 1
An + 1
H
H
H
D
I/O
(n+1)
E xte rnal Ad dre ss Blo cke d-- Counte r disab le d (An + 1 re used )
X
X
A
0
X
X
L
(4)
D
I/O
(0)
Counte r Re se t to Ad dress 0
5638 tbl 03
Grade
Ambient
Temperature
(1)
GND
V
DD
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
5638 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
DD
+0.3V
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5638 tbl 05
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current
50
mA
5638 tbl 06
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
5638 tbl 07
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB, and OE = V
IL
; CE
1
and R/
W = V
IH
.
3. Outputs configured in Flow-Through Output mode: if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS and CNTRST are independent of all other signals including CE
0
, CE
1
,
UB and LB.
5. The address counter advances if
CNTEN = V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB and LB.