2002 Integrated Device Technology, Inc.
JANUARY 2002
DSC-5648/1
1
.unctional Block Diagram
.eatures:
x
True Dual-Ported memory cells which allow simultaneous
access of the same memory location
x
High-speed clock to data access
Commercial: 7.5/9/12ns (max.)
Industrial: 9ns (max.)
x
Low-power operation
IDT70V9369L
Active: 500mW (typ.)
Standby: 1.5mW (typ.)
x
Flow-Through or Pipelined output mode on either port via
the
FT/PIPE pins
x
Counter enable and reset features
x
Dual chip enables allow for depth expansion without
additional logic
x
Full synchronous operation on both ports
4ns setup to clock and 0ns hold on all control, data, and
address inputs
Data input, address, and control registers
Fast 7.5ns clock to data out in the Pipelined output mode
Self-timed write allows fast cycle time
12ns cycle time, 83MHz operation in Pipelined output mode
x
Separate upper-byte and lower-byte controls for
multiplexed bus and bus matching compatibility
x
LVTTL- compatible, single 3.3V (0.3V) power supply
x
Industrial temperature range (40C to +85C) is
available for selected speeds
x
Available in a 100-pin Thin Quad Flatpack (TQFP)
IDT70V9369L
0a 1a
0b 1b
0/1
a
b
I/O
Control
1
0/1
0
FT
/PIPE
R
R/
W
R
UB
R
LB
R
CE
0R
OE
R
CE
1R
MEMORY
ARRAY
Counter/
Address
Reg.
5648 drw 01
A
13R
A
0R
CLK
R
ADS
R
CNTEN
R
CNTRST
R
I/O
9L
-I/O
17L
I/O
0L
-I/O
8L
I/O
9R
-I/O
17R
I/O
0R
-I/O
8R
A
0L
CLK
L
ADS
L
A
13L
CNTEN
L
CNTRST
L
Counter/
Address
Reg.
R/
W
L
UB
L
LB
L
CE
0L
OE
L
CE
1L
1
0/1
0
1b 0b
1a 0a
0/1
b a
I/O
Control
FT
/PIPE
L
HIGH-SPEED 3.3V 16K x 18
SYNCHRONOUS PIPELINED
DUAL-PORT STATIC RAM
PRELIMINARY
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
2
Preliminary
Index
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76
100-Pin TQFP
Top View
(5)
A
9L
A
10L
A
11L
A
12L
A
13L
NC
NC
LB
L
UB
L
CE
0L
CE
1L
CNTRST
L
R/
W
L
OE
L
V
DD
FT
/PIPE
L
I/O
16L
I/O
17L
I/O
15L
I/O
14L
I/O
13L
I/O
12L
I/O
11L
I/O
10L
5648 drw 02
A
8R
A
9R
A
10R
A
11R
A
12R
A
13R
NC
NC
LB
R
UB
R
CE
0R
CNTRST
R
R/
W
R
V
SS
OE
R
FT
/PIPE
R
I/O
14R
I/O
13R
I/O
12R
I/O
11R
CE
1R
I/O
17R
V
SS
I/O
16R
I/O
15R
A
8
L
A
7
L
A
6
L
A
5
L
A
4
L
A
3
L
A
2
L
A
1
L
A
0
L
C
N
T
E
N
L
C
L
K
L
A
D
S
L
V
S
S
V
s
s
A
D
S
R
C
L
K
R
C
N
T
E
N
R
A
0
R
A
2
R
A
3
R
A
4
R
A
5
R
A
6
R
A
7
R
I
/
O
9
L
I
/
O
8
L
V
D
D
I
/
O
7
L
I
/
O
6
L
I
/
O
5
L
I
/
O
4
L
I
/
O
3
L
I
/
O
2
L
I
/
O
1
L
V
S
S
I
/
O
0
L
I
/
O
4
R
I
/
O
5
R
I
/
O
6
R
I
/
O
3
R
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
7
R
I
/
O
8
R
I
/
O
9
R
I
/
O
1
0
R
A
1
R
.
70V9369PF
PN100-1
(4)
V
SS
V
S
S
V
D
D
01/09/02
Description:
The IDT70V9369 is a high-speed 16K x 18 bit synchronous
Dual-Port RAM. The memory array utilizes Dual-Port memory cells
to allow simultaneous access of any address from both ports.
Registers on control, data, and address inputs provide minimal setup
and hold times. The timing latitude provided by this approach allows
systems to be designed with very short cycle times.
Pin Configuration
(1,2,3)
NOTES:
1. All V
DD
pins must be connected to power supply.
2. All V
SS
pins must be connected to ground.
3. Package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
With an input data register, the IDT70V9369 has been optimized for
applications having unidirectional or bidirectional data flow in bursts. An
automatic power down feature, controlled by
CE
0
and CE
1,
permits the
on-chip circuitry of each port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 500mW of power.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
3
Preliminary
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
ADS, CNTEN, CNTRST = X.
3.
OE is an asynchronous input signal.
Truth Table IRead/Write and Enable Control
(1,2,3)
Pin Names
Left Port
Right Port
Names
CE
0L,
CE
1L
CE
0R,
CE
1R
Chip Enables
(2)
R/
W
L
R/
W
R
Read/Write Enable
OE
L
OE
R
Output Enable
A
0L
- A
13L
A
0R
- A
13R
Address
I/O
0L
- I/O
17L
I/O
0R
- I/O
17R
Data Input/Output
CLK
L
CLK
R
Clock
UB
L
UB
R
Upper Byte Select
(1)
LB
L
LB
R
Lower Byte Select
(1)
ADS
L
ADS
R
Address Strobe Enable
CNTEN
L
CNTEN
R
Counter Enable
CNTRST
L
CNTRST
R
Counter Reset
FT/PIPE
L
FT/PIPE
R
Flow-Through / Pipeline
V
DD
Power (3.3V)
V
SS
Ground (0V)
5648 tbl 01
OE
CLK
CE
0
CE
1
UB
LB
R/
W
Upper Byte
I/O
9-17
Lower Byte
I/O
0-8
MODE
X
H
X
X
X
X
High-Z
High-Z
DeselectedPower Down
X
X
L
X
X
X
High-Z
High-Z
DeselectedPower Down
X
L
H
H
H
X
High-Z
High-Z
Both Bytes Deselected
X
L
H
L
H
L
DATA
IN
High-Z
Write to Upper Byte Only
X
L
H
H
L
L
High-Z
DATA
IN
Write to Lower Byte Only
X
L
H
L
L
L
DATA
IN
DATA
IN
Write to Both Bytes
L
L
H
L
H
H
DATA
OUT
High-Z
Read Upper Byte Only
L
L
H
H
L
H
High-Z
DATA
OUT
Read Lower Byte Only
L
L
H
L
L
H
DATA
OUT
DATA
OUT
Read Both Bytes
H
X
L
H
L
L
X
High-Z
High-Z
Outputs Disabled
5648 tbl 02
NOTES:
1.
LB and UB are single buffered regardless of state of FT/PIPE.
2.
CE
0
and CE
1
are single buffered when
FT/PIPE = V
IL
,
CE
0
and CE
1
are double buffered when
FT/PIPE = V
IH,
i.e., the signals
take two cycles to deselect.
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
4
Preliminary
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
NOTES:
1. These parameters are determined by device characterization, but are not
production tested.
2. 3dV references the interpolated capacitance when the input and output switch
from 0V to 3V or from 3V to 0V.
3. C
OUT
also references C
I/O
.
Capacitance
(1)
(T
A
= +25C, f = 1.0MH
Z
)
Truth Table IIAddress Counter Control
(1,2,6)
NOTES:
1. "H" = V
IH,
"L" = V
IL,
"X" = Don't Care.
2.
CE
0
,
LB, UB, and OE = V
IL
; CE
1
and R/
W = V
IH
.
3. Outputs configured in Flow-Through Output mode; if outputs are in Pipelined mode the data out will be delayed by one cycle.
4.
ADS and CNTRST are independent of all other signals including CE
0
, CE
1
,
UB and LB.
5. The address counter advances if
CNTEN = V
IL
on the rising edge of CLK, regardless of all other signals including
CE
0
, CE
1
,
UB and LB.
6. While an external address is being loaded (
ADS = V
IL
), R/
W = V
IH
is recommended to ensure data is not written arbitrarily.
NOTES:
1. V
IL
> -1.5V for pulse width less than 10 ns.
2. V
TERM
must not exceed V
DD
+0.3V.
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
TERM
must not exceed V
DD
+0.3V for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
DD
+ 0.3V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
Address
Previous
Address
Addr
Used
CLK
(6
)
ADS
CNTEN
CNTRST
I/O
(3)
MODE
An
X
An
L
(4)
X
H
D
I/O
(n)
External Address Used
X
An
An + 1
H
L
(5)
H
D
I/O
(n+1)
Counter Enabled--Internal Address generation
X
An + 1
An + 1
H
H
H
D
I/O
(n+1)
External Address Blocked--Counter disabled (An + 1 reused)
X
X
A
0
X
X
L
(4)
D
I/O
(0)
Counter Reset to Address 0
5648 tbl 03
Grade
Ambient
Temperature
(1)
GND
V
DD
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
5648 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Supply Voltage
3.0
3.3
3.6
V
Vss
Ground
0
0
0
V
V
IH
Input High Voltage
2.0V
____
V
DD
+0.3V
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5648 tbl 05
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect to
GND
-0.5 to +4.6
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output Current
50
mA
5648 tbl 06
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
(3)
Output Capacitance
V
OUT
= 3dV
10
pF
5648 tbl 07
6.42
IDT70V9369L
High-Speed 3.3V 16K x 18 Dual-Port Synchronous Pipelined Static RAM Industrial and Commercial Temperature Ranges
5
Preliminary
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(3)
(V
DD
= 3.3V 0.3V)
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
DD
= 3.3V 0.3V)
NOTE:
1. At V
DD
< 2.0V input leakages are undefined.
NOTES:
1. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency clock cycle of 1/t
CYC
, using "AC TEST CONDITIONS" at input
levels of GND to 3V.
2. f = 0 means no address, clock, or control lines change. Applies only to input at CMOS level standby.
3. Port "A" may be either left or right port. Port "B" is the opposite from port "A".
4. V
DD
= 3.3V, T
A
= 25C for Typ, and are not production tested. I
DD DC
(f=0)
= 90mA (Typ).
5.
CE
X
= V
IL
means
CE
0X
= V
IL
and CE
1X
= V
IH
CE
X
= V
IH
means
CE
0X
= V
IH
or CE
1X
= V
IL
CE
X
< 0.2V means
CE
0X
< 0.2V and CE
1X
> V
DD
- 0.2V
CE
X
> V
DD
- 0.2V means
CE
0X
> V
DD
- 0.2V or CE
1X
< 0.2V
"X" represents "L" for left port or "R" for right port.
Symbol
Parameter
Test Conditions
70V9369L
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
DD
= 3.6V, V
IN
= 0V to V
DD
___
5
A
|I
LO
|
Output Leakage Current
CE
O
= V
IH
or CE
1
= V
IL
, V
OUT
= 0V to V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= +4mA
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
V
5648 tbl 08
70V9369L7
Com'l Only
70V9369L9
Com'l
& Ind
70V9369L12
Com'l Only
Symbol
Parameter
Test Condition
Version
Typ.
(4)
Max.
Typ.
(4)
Max.
Typ.
(4)
Max.
Unit
I
DD
Dynamic Operating
Current (Both
Ports Active)
CE
L
and
CE
R
= V
IL
,
Outputs Disabled,
f = f
MAX
(1)
COM'L
L
200
310
180
260
150
230
mA
IND
L
____
____
180
280
____
____
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
f = f
MAX
(1)
COM'L
L
65
130
50
100
40
80
mA
IND
L
____
____
50
120
____
____
I
SB2
Standby
Current (One
Port - TTL
Level Inputs)
CE
"A "
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs
Disabled, f=f
MAX
(1)
COM'L
L
140
245
110
190
100
175
mA
IND
L
____
____
110
205
____
____
I
SB3
Full Standby
Current (Both
Ports - CMOS
Level Inputs)
Both Ports
CE
L
and
CE
R
> V
DD
- 0.2V,
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, f = 0
(2)
COM'L
L
0.4
3
0.4
3.0
0.4
3
mA
IND
L
____
____
0.4
6.0
____
____
I
SB4
Full Standby
Current (One
Port - CMOS
Level Inputs)
CE
"A "
< 0.2V and
CE
"B "
> V
DD
- 0.2V
(5)
V
IN
> V
DD
- 0.2V or
V
IN
< 0.2V, Active Port,
Outputs Disabled , f = f
MAX
(1)
COM'L
L
130
235
100
180
90
165
mA
IND
L
____
____
100
195
____
____
5648 tbl 09
PDF 
ZIP