FEBRUARY 2001
DSC-2948/07
1
2000 Integrated Device Technology, Inc.
Features
x
x
x
x
x
32K x 8 advanced high-speed CMOS static RAM
x
x
x
x
x
Commercial (0 to 70C) and Industrial (-40 to 85C)
temperature options
x
x
x
x
x
Equal access and cycle times
Commercial and Industrial: 12/15/20/25ns
x
x
x
x
x
One Chip Select plus one Output Enable pin
x
x
x
x
x
Bidirectional data inputs and outputs directly
TTL-compatible
x
x
x
x
x
Low power consumption via chip deselect
x
x
x
x
x
Commercial product available in 28-pin 300- and 600-mil
Plastic DIP, 300 mil Plastic SOJ and TSOP packages
x
x
x
x
x
Industrial product available in 28-pin 300 mil Plastic SOJ
and TSOP packages
Description
The IDT71256SA is a 262,144-bit high-speed Static RAM organized
as 32K x 8. It is fabricated using IDT's high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with
innovative circuit design techniques, provides a cost-effective solution for
high-speed memory needs.
The IDT71256SA has an output enable pin which operates as fast as
6ns, with address access times as fast as 12ns. All bidirectional inputs and
outputs of the IDT71256SA are TTL-compatible and operation is from a
single 5V supply. Fully static asynchronous circuitry is used, requiring no
clocks or refresh for operation.
The IDT71256SA is packaged in 28-pin 300- and 600-mil Plastic DIP,
28-pin 300 mil Plastic SOJ and TSOP.
Functional Block Diagram
CMOS Static RAM
256K (32K x 8-Bit)
IDT71256SA
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
A
8
A
9
A
10
A
11
A
12
A
13
A
14
I/O
0 -
I/O
7
CS
WE
OE
8
8
CONTROL
LOGIC
I/O CONTROL
262,144-BIT
MEMORY
ARRAY
ADDRESS
DECODER
2948 drw 01
,
2
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Pin Configurations
DIP/SOJ
Top View
Recommended Operating
Temperature and Supply Voltage
Recommended DC Operating
Conditions
Truth Table
(1,2)
TSOP
Top View
2948 drw 02a
22
23
24
25
26
27
28
1
2
3
4
5
7
6
21
20
19
18
17
16
15
14
13
12
11
10
9
8
A
10
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
GND
I/O
2
I/O
1
I/O
0
A
0
A
1
A
2
SO28-8
OE
A
11
A
9
A
8
A
13
A
14
A
7
A
6
A
5
A
4
A
3
A
12
WE
V
CC
,
2948 drw 02
5
6
7
8
9
10
11
12
GND
1
2
3
4
24
23
22
21
20
19
18
17
SO28-5
P28-2
P28-1
13
14
28
27
26
25
A
7
A
6
A
5
A
4
A
3
A
2
A
1
A
0
I/O
0
I/O
1
I/O
2
V
CC
A
14
WE
A
13
A
8
A
10
A
11
OE
A
12
CS
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
A
9
16
15
,
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Rating
Value
Unit
V
CC
Supply Voltage
Relative to GND
-0.5 to +7.0
V
V
TERM
Terminal Voltage
Relative to GND
-0.5 to V
CC
+0.5
V
T
BIAS
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-55 to +125
o
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
2948 tbl 02
NOTES:
1. H = V
IH
, L = V
IL
, x = Don't care.
2. V
LC
= 0.2V, V
HC
= V
CC
0.2V.
3. Other inputs
V
HC
or
V
LC
.
CS
OE
WE
I/O
Function
L
L
H
DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Outputs Disabled
H
X
X
High-Z
Deselecte d - Standby (I
SB
)
V
HC
(3)
X
X
High-Z
Deselecte d - Standby (I
SB1
)
2948 tbl 03
Grade
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
4.5V 5.5V
Industrial
-40
O
C to +85
O
C
0V
4.5V 5.5V
2948 tbl 01
NOTE:
1. V
IL
(min.) = 1.5V for pulse width less than 10ns, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
V
CC
+0.5
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2948 tbl 04
6.42
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
3
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
Figure 1. AC Test Load
*Including jig and scope capacitance.
DC Electrical Characteristics
(1)
(V
CC
= 5.0V 10%, V
LC
= 0.2V, V
HC
= V
CC
0.2V)
AC Test Conditions
Capacitance
(T
A
= +25C, f = 1.0MHz, SOJ package)
DC Electrical Characteristics
(V
CC
= 5.0V 10%)
2948 drw 03
480
255
30pF*
DATA
OUT
5V
,
2948 drw 04
480
255
5pF*
DATA
OUT
5V
.
Symbol
Parameter
Test Conditions
IDT71256SA
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
=
GND to V
CC
___
5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS = V
IH
, V
OUT
= GND to V
CC
___
5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
CC
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
___
V
2948 tbl 05
NOTES:
1. All values are maximum guaranteed values.
2. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing.
Symbol
Parameter
71256SA12
71256SA15
71256SA20
71256SA25
Unit
I
CC
Dynamic Operating Current
CS < V
IL
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
160
150
145
145
mA
I
SB
Standby Power Supply Current (TTL Level)
CS > V
IH
, Outputs Open, V
CC
= Max., f = f
MAX
(2)
50
40
40
40
mA
I
SB1
Standby Power Supply Current (CMOS Level)
CS > V
HC
, Outputs Open, V
CC
= Max., f = 0
(2)
,
V
IN
< V
LC
or V
IN
> V
HC
15
15
15
15
mA
2948 tbl 06
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figures 1 and 2
2948 tbl 07
NOTE:
1. This parameter is guaranteed by device characterization, but not production
tested.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
2948 tbl 08
4
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
CC
= 5.0V 10%)
NOTE:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
Symbol
Parameter
71256SA12
71256SA15
71256SA20
71256SA25
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
12
____
15
____
20
____
25
____
ns
t
AA
Address Access Time
____
12
____
15
____
20
____
25
ns
t
ACS
Chip Select Access Time
____
12
____
15
____
20
____
25
ns
t
CLZ
(1)
Chip Select to Output in Low-Z
4
____
4
____
4
____
4
____
ns
t
CHZ
(1)
Chip Sele ct to Output in High-Z
0
6
0
7
0
10
0
11
ns
t
OE
Output Enable to Output Valid
____
6
____
7
____
10
____
11
ns
t
OLZ
(1)
Output Enab le to Output in Low-Z
0
____
0
____
0
____
0
____
ns
t
OHZ
(1)
Output Disab le to Output in High-Z
0
6
0
6
0
8
0
10
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
3
____
ns
t
PU
(1)
Chip Sele ct to Power Up Time
0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
12
____
15
____
20
____
25
ns
Write Cycle
t
WC
Write Cycle Time
12
____
15
____
20
____
25
____
ns
t
AW
Address Valid to End-of-Write
9
____
10
____
15
____
20
____
ns
t
CW
Chip Select to End-of-Write
9
____
10
____
15
____
20
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
8
____
10
____
15
____
20
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
6
____
7
____
11
____
13
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
0
____
ns
t
OW
(1)
Output Active from End-of-Write
4
____
4
____
4
____
4
____
ns
t
WHZ
(1)
Write Enab le to Output in High-Z
0
6
0
6
0
10
0
11
ns
2948 tbl 09
6.42
IDT71256SA
CMOS Static RAM 256K (32K x 8-Bit) Commercial and Industrial Temperature Ranges
5
Timing Waveform of Read Cycle No. 1
(1)
ADDRESS
OE
CS
DATA
OUT
V
CC
SUPPLY
CURRENT
2948 drw 05
(5)
(5)
(5)
(5)
DATA
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
OUT
t
PU
t
PD
I
CC
I
SB
,
Timing Waveform of Read Cycle No. 2
(1,2,4)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3. Address must be valid prior to or coincident with the later of
CS transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE is LOW.
5. Transition is measured 200mV from steady state.
DATA
OUT
ADDRESS
2948 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
,
PDF 
ZIP