1
2000 Integrated Device Technology, Inc.
JANUARY 2001
DSC-2692/15
HIGH SPEED
2K x 8 DUAL PORT
STATIC RAM
IDT7132SA/LA
IDT7142SA/LA
Functional Block Diagram
Features
x
x
x
x
x
High-speed access
Military: 25/35/55/100ns (max.)
Commercial: 20/25/35/55/100ns (max.)
x
x
x
x
x
Low-power operation
IDT7132/42SA
Active: 325mW (typ.)
Standby: 5mW (typ.)
IDT7132/42LA
Active: 325mW (typ.)
Standby: 1mW (typ.)
NOTES:
1. IDT7132 (MASTER):
BUSY is open drain output and requires pullup resistor of 270
.
IDT7142 (SLAVE):
BUSY is input.
2. Open drain output: requires pullup resistor of 270
.
x
x
x
x
x
MASTER IDT7132 easily expands data bus width to 16-or-more
bits using SLAVE IDT7142
x
x
x
x
x
On-chip port arbitration logic (IDT7132 only)
x
x
x
x
x
BUSY output flag on IDT7132; BUSY input on IDT7142
x
x
x
x
x
Battery backup operation --2V data retention (LA only)
x
x
x
x
x
TTL-compatible, single 5V 10% power supply
x
x
x
x
x
Available in 48-pin DIP, LCC and Flatpack, and 52-pin PLCC
packages
x
x
x
x
x
Military product compliant to MIL-PRF-38535 QML
x
x
x
x
x
Industrial temperature range (40C to +85C) is available for
selected speeds
OE
L
CE
L
R/W
L
I/O
OL-
I/O
7L
BUSY
L
(1,2)
A
10L
A
0L
CE
L
OE
L
R/
W
L
CE
R
OE
R
R/
W
R
OE
R
CE
R
R/
W
R
I/O
OR-
I/O
7R
BUSY
R
(1,2)
A
10R
A
0R
I/O
Control
I/O
Control
Address
Decoder
Address
Decoder
MEMORY
ARRAY
ARBITRATION
LOGIC
2692 drw 01
m
11
11
2
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
Pin Configurations
(1,2,3)
NOTES:
1. All V
CC
pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. P48-1 package body is approximately .55 in x 2.43 in x .18 in.
C48-2 package body is approximately .62 in x 2.43 in x .15 in.
L48-1 package body is approximately .57 in x .57 in x .68 in.
F48-1 package body is approximately .75 in x .75 in x .11 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Description
The IDT7132/IDT7142 are high-speed 2K x 8 Dual-Port Static RAMs.
The IDT7132 is designed to be used as a stand-alone 8-bit Dual-Port RAM
or as a "MASTER" Dual-Port RAM together with the IDT7142 "SLAVE"
Dual-Port in 16-bit-or-more word width systems. Using the IDT MASTER/
SLAVE Dual-Port RAM approach in 16-or-more-bit memory system
applications results in full-speed, error-free operation without the need for
additional discrete logic.
Both devices provide two independent ports with separate control,
address, and l/O pins that permit independent, asynchronous access for
reads or writes to any location in memory. An automatic power down
feature, controlled by
CE permits the on-chip circuitry of each port to enter
a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200W from a 2V battery.
The IDT7132/7142 devices are packaged in a 48-pin sidebraze or
plastic DIPs, 48-pin LCCs, 52-pin PLCCs, and 48-lead flatpacks.
Military grade product is manufactured in compliance with the latest
revision of MIL-PRF-38535 QML, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
IDT7132/
7142
P or C
P48-1
(4)
&
C48-2
(4)
48-Pin
DIP
Top
View
(5)
2692 drw 02
GND
I/O
6R
I/O
5R
I/O
4R
I/O
3R
I/O
2R
I/O
1R
I/O
0R
I/O
7L
I/O
6L
I/O
5L
I/O
4L
CE
R
CE
L
OE
L
A
0L
BUSY
L
R/
W
L
R/
W
R
BUSY
R
V
CC
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
A
10L
A
10R
,
IDT7132/42L48 or F
L48-1
(4)
&
F48-1
(4)
48-Pin LCC/ Flatpack
Top View
(5)
INDEX
6 5
4 3 2
1
48 47 46 45 44 43
19 20 21 22 23
25 26 27 28 29 30
24
42
41
40
39
38
37
36
35
34
33
32
31
7
8
9
10
11
12
13
14
15
16
17
18
2692 drw 03
G
N
D
C
E
R
C
E
L
O
E
L
A
0
L
O
E
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
I
/
O
3
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
B
U
S
Y
L
R
/
W
L
R
/
W
R
B
U
S
Y
R
V
C
C
I/O
6R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
1
R
I
/
O
0
R
I
/
O
7
L
I
/
O
6
L
I
/
O
5
L
I
/
O
4
L
A
1
0
L
A
1
0
R
,
Capacitance
(1)
(T
A
= +25C,f = 1.0MHz)
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dV represents the interpolated capacitance when the input and output signals
switch from 3V to 0V.
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
11
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
11
pF
2692 tbl 00
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
3
IDT7132/42J
J52-1
(4)
52-Pin PLCC
Top View
(5)
INDEX
N
/
C
G
N
D
OE
R
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
N/C
I/O
7R
46
45
44
43
42
41
40
39
38
37
36
35
34
I/O
3L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
I/O
2L
8
9
10
11
12
13
14
15
16
17
18
19
20
47
48
49
50
51
52
1
2
3
4
5
6
7
33
32
31
30
29
28
27
26
25
24
23
22
21
2692 drw 04
A
1
0
L
V
C
C
A
1
0
R
I
/
O
6
R
A
0
L
O
E
L
N
/
C
C
E
L
C
E
R
N
/
C
B
U
S
Y
L
R
/
W
L
R
/
W
R
B
U
S
Y
R
I
/
O
5
R
I
/
O
4
R
I
/
O
3
R
I
/
O
2
R
I
/
O
1
R
I
/
O
0
R
I
/
O
7
L
I
/
O
6
L
I
/
O
5
L
I
/
O
4
L
Absolute Maximum Ratings
(1)
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage
(1,2)
NOTES:
1.
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in
the operational sections of the specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2.
V
TERM
must not exceed Vcc + 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> Vcc + 10%.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2.
Industrial temperature: for specific speeds, packages and powers contact your
sales office.
NOTES:
1.
V
IL
(min.) = -1.5V for pulse width less than 10ns.
2.
V
TERM
must not exceed Vcc + 10%.
NOTES:
1. All V
CC
pins must be connected to the power supply.
2. All GND pins must be connected to the ground supply.
3. Package body is approximately .75 in x .75 in x .17 in.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
Pin Configurations
(1,2,3)
(con't.)
Symbol
Rating
Commercial
& Industrial
Military
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
-0.5 to +7.0
V
T
BIAS
Temperature
Under Bias
-55 to +125
-65 to +135
o
C
T
STG
Storage
Temperature
-65 to +150
-65 to +150
o
C
I
OUT
DC Output
Current
50
50
mA
2692 tbl 01
Grade
Ambient
Temperature
GND
Vcc
Military
-55
O
C to+125
O
C
0V
5.0V
+
10%
Commercial
0
O
C to +70
O
C
0V
5.0V
+
10%
Industrial
-40
O
C to +85
O
C
0V
5.0V
+
10%
2692 tbl 02
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
6.0
(2)
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2692 tbl 03
4
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,5,8)
(V
CC
= 5.0V 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. PLCC Package only
3. At f = f
Max
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using "AC TEST CONDITIONS" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Vcc = 5V, T
A
=+25C for Typ and is not production tested. Vcc
DC
= 100mA (Typ)
6. Port "A" may be either left or right port. Port "B" is opposite from port "A".
7. Not available in DIP packages.
8. Industrial temperature: for specific speeds, packages and powers contact your sales office.
7132X20
(2)
7142X20
(2)
Com'l Only
7132X25
(7)
7142X25
(7)
Com'l &
Military
7132X35
7142X35
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Operating Current
(Both Ports Active)
CE
L
=
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
COM'L
SA
LA
110
110
250
200
110
110
220
170
80
80
165
120
mA
MIL &
IND
SA
LA
____
____
____
____
110
110
280
220
80
80
230
170
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
,
f = f
MAX
(3)
COM'L
SA
LA
30
30
65
45
30
30
65
45
25
25
65
45
mA
MIL &
IND
SA
LA
____
____
____
____
30
30
80
60
25
25
80
60
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(6)
Active Port Outputs Disabled
f=f
MAX
(3)
COM'L
SA
LA
65
65
165
125
65
65
150
115
50
50
125
90
mA
MIL &
IND
SA
LA
____
____
____
____
65
65
160
125
50
50
150
115
I
SB3
Full Standby Current (Both
Ports - All
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
-0.2V
V
IN
> V
CC
-0.2V or V
IN
< 0.2V, f = 0
(4)
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
1.0
0.2
15
4
mA
MIL &
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
-0.2V
(6)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L
SA
LA
60
60
155
115
60
60
145
105
45
45
110
85
mA
MIL &
IND
SA
LA
____
____
____
____
60
60
155
115
45
45
145
105
2692 tbl 04a
7132X55
7142X55
Com'l &
Military
7132X100
7142X100
Com'l &
Military
Symbol
Parameter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE
L
=
CE
R
= V
IL
,
Outputs Disabled
f = f
MAX
(3)
COM'L
SA
LA
65
65
155
110
65
65
155
110
mA
MIL &
IND
SA
LA
65
65
190
140
65
65
190
140
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
L
=
CE
R
= V
IH
,
f = f
MAX
(3)
COM'L
SA
LA
20
20
65
35
20
20
55
35
mA
MIL &
IND
SA
LA
20
20
65
45
20
20
65
45
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(6)
Active Port Outputs Disabled
f=f
MAX
(3)
COM'L
SA
LA
40
40
110
75
40
40
110
75
mA
MIL &
IND
SA
LA
40
40
125
90
40
40
125
90
I
SB3
Full Standby Current
(Both Ports - All
CMOS Level Inputs)
CE
L
and
CE
R
> V
CC
-0.2V
V
IN
> V
CC
-0.2V or V
IN
< 0.2V, f = 0
(4)
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
mA
MIL &
IND
SA
LA
1.0
0.2
30
10
1.0
0.2
30
10
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
-0.2V
(6)
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L
SA
LA
40
40
100
70
40
40
95
70
mA
MIL &
IND
SA
LA
40
40
110
85
40
40
110
80
2692 tbl 04b
6.42
IDT7132SA/LA and IDT 7142SA/LA
High Speed 2K x 8 Dual Port Static RAM Military, Industrial and Commercial Temperature Ranges
5
Data Retention Characteristics
(LA Version Only)
NOTES:
1. V
CC
= 2V, T
A
= +25C, and is not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed but not production tested.
NOTE:
1. At Vcc
<
2.0V leakages are undefined.
DC Electrical Characteristics Over the Operating
Temperature Supply Voltage Range
(V
CC
= 5.0V 10%)
Data Retention Waveform
V
CC
CE
4.5V
4.5V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
2692 drw 05
,
Symbol
Parameter
Test Conditions
7132SA
7142SA
7132LA
7142LA
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 5.5V,
V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
V
CC
= 5.5V,
CE = V
IH
, V
OUT
= 0V to V
CC
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= 4mA
___
0.4
___
0.4
V
V
OL
Open Drain Output
Low Voltage (
BUSY, INT)
I
OL
= 16mA
___
0.5
___
0.5
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
2692 tbl 05
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
V
DR
V
CC
for Data Retention
V
CC
= 2.0V
2.0
___
___
V
I
CCDR
Data Retention Current
CE > V
CC
-0.2V
V
IN
> V
CC
-0.2V or
Mil. & Ind.
___
100
4000
A
Com'l.
___
100
1500
A
t
CDR
(3)
Chip Deselect to Data Retention Time
V
IN
<
0.2V
0
___
___
ns
t
R
(3)
Operation Recovery Time
t
RC
(2)
___
___
ns
2692 tbl 06
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