1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-2691/8
1
HIGH SPEED
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
IDT71321SA/LA
IDT71421SA/LA
Features
x
x
x
x
x
High-speed access
Commercial: 20/25/35/55ns (max.)
Industrial: 55ns (max.)
x
x
x
x
x
Low-power operation
IDT71321/IDT71421SA
--
Active: 325mW (typ.)
--
Standby: 5mW (typ.)
IDT71321/421LA
--
Active: 325mW (typ.)
--
Standby: 1mW (typ.)
x
x
x
x
x
Two
INT flags for port-to-port communications
Functional Block Diagram
NOTES:
1. IDT71321 (MASTER):
BUSY is open drain output and requires pullup resistor of 270
.
IDT71421 (SLAVE):
BUSY is input.
2. Open drain output: requires pullup resistor of 270
.
1
x
x
x
x
x
MASTER IDT71321 easily expands data bus width to 16-or-
more-bits using SLAVE IDT71421
x
x
x
x
x
On-chip port arbitration logic (IDT71321 only)
x
x
x
x
x
BUSY output flag on IDT71321; BUSY input on IDT71421
x
x
x
x
x
Fully asynchronous operation from either port
x
x
x
x
x
Battery backup operation 2V data retention (LA only)
x
x
x
x
x
TTL-compatible, single 5V 10% power supply
x
x
x
x
x
Available in 52-Pin PLCC, 64-Pin TQFP, and 64-Pin STQFP
x
x
x
x
x
Industrial temperature range (40C to +85C) is available
for selected speeds
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
2691 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/
W
L
INT
L
BUSY
R
I/O
0R
-I/O
7R
A
10R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
R/
W
R
11
11
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
IDT71321/421J
J52-1
(4)
PLCC
Top View
(5)
INDEX
I/O
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
3L
2L
OE
A
A
A
A
A
A
A
A
A
A
NC
I/O
R
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
4
L
5
L
6
L
7
L
N
C
G
N
D
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
0
R
1
R
2
R
3
R
4
R
6
R
5
R
A
0
L
O
E
A
I
N
T
B
U
S
Y
R
/
W
C
E
V
C
E
R
/
W
B
U
S
Y
I
N
T
A
L
1
0
L
L
L
C
C
R
R
R
1
0
R
R
L
L
1
2
3
4
5
6
7
47
48
49
50
51
52
9
8
10
11
12
13
14
15
16
17
18
19
20
27
26
25
24
23
22
21
33
32
31
30
29
28
35
34
36
37
38
39
40
41
42
43
44
45
46
2691 drw 02
,
INDEX
IDT71321/421PF or TF
PN64-1 / PP64-1
(4)
64-Pin TQFP
64-Pin STQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
2691 drw 03
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
6
4
N
/
C
A
1
0
R
N
/
C
N
/
C
A
1
0
L
N
/
C
G
N
D
N
/
C
N
/
C
G
N
D
N
/
C
R
/
W
R
C
E
R
V
C
C
V
C
C
B
U
S
Y
L
I
N
T
L
I
/
O
3
L
I
/
O
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
3
R
I
/
O
4
R
I
/
O
5
R
R
/
W
L
C
E
L
B
U
S
Y
R
I
N
T
R
,
Pin Configurations
(1,2,3)
Description
The IDT71321/IDT71421 are high-speed 2K x 8 Dual-Port Static
RAMs with internal interrupt logic for interprocessor communications.
The IDT71321 is designed to be used as a stand-alone 8-bit Dual-
Port Static RAM or as a "MASTER" Dual-Port Static RAM together
with the IDT71421 "SLAVE" Dual-Port in 16-bit-or-more word width
systems. Using the IDT MASTER/SLAVE Dual-Port Static RAM ap-
proach in 16-or-more-bit memory system applications results in full
speed, error-free operation without the need for additional discrete
logic.
Both devices provide two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by
CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (LA)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200W from a 2V battery.
The IDT71321/IDT71421 devices are packaged in 52-pin PLCCs,
64-pin TQFPs, and 64-pin STQFPs.
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 10%.
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 10ns.
2. V
TERM
must not exceed Vcc + 10%.
NOTES:
1. This is the parameter T
A
.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +7.0
V
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
I
OUT
DC Output
Current
50
mA
2691 tbl 01
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
5.0V
+
10%
Industrial
-40
O
C to +85
O
C
0V
5.0V
+
10%
2691 tbl 02
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
6.0
(2)
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2691 tbl 03
Capacitance
(1)
(TA = +25C, f = 1.0MHz) TQFP Only
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
2691 tbl 00
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,4,6)
(V
CC
= 5.0V 10%)
NOTES:
1. 'X' in part numbers indicates power rating (SA or LA).
2. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
, and using "AC TEST CONDITIONS" of input
levels of GND to 3V.
3. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
4. Vcc = 5V, T
A
=+25C for Typ and is not production tested. Vcc
DC
= 100mA (Typ)
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
6. Industrial temperature: for other speeds, packages and powers contact your sales office.
71321X20
71421X20
Com'l Only
71321X25
71421X25
Com'l Only
Symbol
Param eter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dy nam ic Op erating
Current
(Bo th Po rts Ac tive )
CE
L
and
CE
R
= V
IL
,
Outputs Ope n
f = f
MAX
(2)
COM'L
SA
LA
110
110
250
200
110
110
220
170
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB1
Stand by Curre nt
(Bo th Po rts - TTL
Lev el Inp uts )
CE
L
and
CE
R
= V
IH
f = f
MAX
(2)
COM'L
SA
LA
30
30
65
45
30
30
65
45
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB2
Stand by Curre nt
(One Po rt - TTL
Lev el Inp uts )
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
A ctive Po rt Outputs Op en,
f=f
MAX
(2)
COM'L
SA
LA
65
65
165
125
65
65
150
115
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB3
Full S tandb y Current
(Bo th Po rts -
CM OS Lev e l Inputs )
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V o r
V
IN
< 0.2V, f = 0
(3)
COM'L
SA
LA
1.0
0.2
15
5
1.0
0.2
15
5
mA
IND
SA
LA
____
____
____
____
____
____
____
____
I
SB4
Full S tandb y Current
(One Po rt -
CM OS Lev e l Inputs )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
A ctive Po rt Outputs Op en,
f = f
MAX
(2)
COM'L
SA
LA
60
60
155
115
60
60
145
105
mA
IND
SA
LA
____
____
____
____
____
____
____
____
2691 tbl 04a
71321X35
71421X35
Com'l Only
71321X55
71421X55
Com'l
& Ind
Symbol
Param eter
Test Condition
Version
Typ.
Max.
Typ.
Max.
Unit
I
CC
Dy namic Ope rating
Curre nt
(Bo th Po rts Ac tiv e)
CE
L
and
CE
R
= V
IL
,
Outputs Op en
f = f
MAX
(2)
COM'L
SA
LA
80
80
165
120
65
65
155
110
mA
IND
SA
LA
____
____
____
____
65
65
190
140
I
SB1
Stand by Curre nt
(Bo th Po rts - TTL
Lev el Inp uts)
CE
L
and
CE
R
= V
IH
f = f
MAX
(2)
COM'L
SA
LA
25
25
65
45
20
20
65
35
mA
IND
SA
LA
____
____
____
____
20
20
65
45
I
SB2
Stand by Curre nt
(One Po rt - TTL
Lev el Inp uts)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Ac tive P ort Outp uts Ope n,
f=f
MAX
(2)
COM'L
SA
LA
50
50
125
90
40
40
110
75
mA
IND
SA
LA
____
____
____
____
40
40
125
90
I
SB3
Full S tandb y Curre nt
(Bo th Po rts -
CM OS Lev el Inp uts )
CE
L
and
CE
R
> V
CC
- 0.2V,
V
IN
> V
CC
- 0.2V o r
V
IN
< 0.2V, f = 0
(3)
COM'L
SA
LA
1.0
0.2
15
4
1.0
0.2
15
4
mA
IND
SA
LA
____
____
____
____
1.0
0.2
30
10
I
SB4
Full S tandb y Curre nt
(One Po rt -
CM OS Lev el Inp uts )
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
V
IN
> V
CC
- 0.2V o r V
IN
< 0.2V
Ac tive P ort Outp uts Ope n,
f = f
MAX
(2)
COM'L
SA
LA
45
45
110
85
40
40
100
70
mA
IND
SA
LA
____
____
____
____
40
40
110
85
2691 tbl 04b
6.42
IDT71321SA/LA and IDT71421SA/LA
High Speed 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range (V
CC
= 5.0V 10%)
NOTE:
1. At Vcc < 2.0V leakages are undefined.
Data Retention Characteristics
(LA Version Only)
NOTES:
1. V
CC
= 2V, T
A
= +25C, and is not production tested.
2. t
RC
= Read Cycle Time
3. This parameter is guaranteed but not production tested.
Data Retention Waveform
V
CC
CE
4.5V
4.5V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
2691 drw 04
,
Symbol
Parameter
Test Conditions
71321SA
71421SA
71321LA
71421LA
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 5.5V, V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
(1)
CE = V
IH
, V
OUT
= 0V to V
CC
,
V
CC
- 5.5V
___
10
___
5
A
V
OL
Output Low Voltage (I/O
0
-I/O
7
)
I
OL
= 4mA
___
0.4
___
0.4
V
V
OL
Open Drain Output
Low Voltage (
BUSY/INT)
I
OL
= 16mA
___
0.5
___
0.5
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
2691 tbl 05
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
____
0
V
I
CCDR
Data Retention Current
V
CC
= 2.0V,
CE > V
CC
- 0.2V
COM'L
____
100
1500
A
V
IN
> V
CC
- 0.2V or VI
N
< 0.2V
IND
____
100
4000
A
t
CDR
(3)
Chip Deselect to Data Retention Time
0
____
____
ns
t
R
(3)
Operation Recovery Time
t
RC
(2)
____
____
ns
2691 tbl 06
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