FEBRUARY 2001
DSC-2986/09
1
2000 Integrated Device Technology, Inc.
Features
x
x
x
x
x
High speed (equal access and cycle time)
Military: 25/35/45/55/70/85ns (max.)
x
x
x
x
x
Low power consumption
x
x
x
x
x
Battery backup operation--2V data retention
(L version only)
x
x
x
x
x
JEDEC standard high-density 22-pin ceramic
DIP packaging
x
x
x
x
x
Produced with advanced CMOS high-performance
technology
x
x
x
x
x
Separate data input and output
x
x
x
x
x
Input and output directly TTL-compatible
x
x
x
x
x
Military product compliant to MIL-STD-883, Class B
Description
The IDT7187 is a 65,536-bit high-speed static RAM organized as 64K
x 1. It is fabricated using IDT's high-performance, high-reliability CMOS
technology. Access times as fast as 25ns are available.
Both the standard (S) and low-power (L) versions of the IDT7187
provide two standby modes--I
SB
and I
SB1
. I
SB
provides low-power
operation; I
SB1
provides ultra-low-power operation. The low-power (L)
version also provides the capability for data retention using battery
backup. When using a 2V battery, the circuit typically consumes only
30W.
Ease of system design is achieved by the IDT7187 with full
asynchronous operation, along with matching access and cycle times.
The device is packaged in an industry standard 22-pin, 300 mil ceramic
DIP.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
Functional Block Diagram
ROW
SELECT
65,536-BIT
MEMORY ARRAY
COLUMN I/O
2986 drw 01
WE
CS
V
CC
GND
DATA
OUT
A
A
A
A
A
A
A
A
A
A
A
A
A
A
DATA
IN
CMOS Static RAM
64K (64K x 1-Bit)
IDT7187S
IDT7187L
2
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
Pin Configuration
Capacitance
(T
A
= +25C, f = 1.0MH
z
)
Recommended DC Operations
Conditions
Recommended Operating
Temperature and Supply Voltage
Absolute Maximum Ratings
(1)
2986 drw 02
5
6
7
8
9
10
11
1
2
3
4
22
21
20
19
18
17
D22-1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CC
A
15
A
13
A
12
16
15
GND
CS
14
A
14
WE
DATA
OUT
A
11
13
12
A
10
A
9
A
8
DATA
IN
,
DIP
Top View
Truth Table
(1)
Pin Descriptions
NOTE:
1. H = V
IH
, L = V
IL
, X = don't care.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
Name
Description
A
0
- A
15
Address Inputs
CS
Chip Select
WE
Write Enable
V
CC
Power
DATA
IN
Data Input
DATA
OUT
Data Output
GND
Ground
2986 tbl 01
Mode
CS
WE
Output
Power
Standby
H
X
High-Z
Standby
Read
L
H
D
OUT
Active
Write
L
L
High-Z
Active
2986 tbl 02
Symbol
Rating
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
-0.5 to +7.0
V
T
A
Operating Temperature
-55 to +125
o
C
T
BIAS
Temperature Under Bias
-65 to +135
o
C
T
STG
Storage Temperature
-65 to +150
o
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
2986 tbl 03
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
8
pF
C
OUT
Output Capacitance
V
OUT
= 0V
8
pF
2986 tbl 04
NOTE:
1. V
IL
(min.) = 3.0V for pulse width less than 20ns, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
6.0
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2986 tbl 05
Grade
Temperature
GND
Vcc
Military
-55
O
C to +125
O
C
0V
5V 10%
2986 tbl 06
6.42
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
3
DC Electrical Characteristics
(V
CC
= 5.0V 10%)
Symbol
Parameter
Test Conditions
IDT7187S
IDT7187L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
=
GND to V
CC
____
10
____
5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS = V
IH
, V
OUT
= GND to V
CC
____
10
____
5
A
V
OL
Output Low Voltage
I
OL
= 10mA, V
CC
= Min.
____
0.5
____
0.5
V
I
OL
= 8mA, V
CC
= Min.
____
0.4
____
0.4
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
____
2.4
____
V
2986 tbl 07
DC Electrical Characteristics
(1)
(V
CC
= 5V 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
Symbol
Parameter
Power
7187S25
7187L25
7187S35
7187L35
7187S45
7187L45
7187S55
7187L55
7187S70
7187L70
7187S85
7187L85
Unit
I
CC1
Operating Power
Supply Current
CS = V
IL
, Outputs Open
V
CC
= Max., f
=
0
(2)
S
105
105
105
105
105
105
mA
L
85
85
85
85
85
85
I
CC2
Dynamic Operating Current
CS = V
IL
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
S
130
120
120
120
120
120
mA
L
110
100
95
90
90
90
I
SB
Standby Power Supply
Current (TTL Level)
CS > V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
S
55
50
50
50
50
50
mA
L
50
40
35
30
28
28
I
SB1
Full Standby Power
Supply Current (CMOS Level)
CS > V
HC
, V
CC
= Max., V
IN
< V
LC
or V
IN
> V
HC
, f = 0
(2)
S
20
20
20
20
20
20
mA
L
1.5
1.5
1.5
1.5
1.5
1.5
2986 tbl 08
4
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
Data Retention Characteristics
(L Version Only) (V
HC
= V
CC
- 0.2V, V
LC
= 0.2V)
AC Test Conditions
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
HZ
, t
LZ
, t
WZ
and t
OW
)
*Includes scope and jig capacitances
Low V
CC
Data Retention Waveform
2986 drw 04
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
2986 drw 05
480
30pF*
255
DATA
OUT
5V
,
2986 drw 06
480
5pF*
255
DATA
OUT
5V
,
NOTES:
1. T
A
= +25C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed, but not tested.
Typ.
(1)
V
CC
@
Max.
V
CC
@
Symbol
Parameter
Test Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
DR
V
CC
for Data Retention
____
2.0
____
____
____
____
V
I
CCDR
Data Retention Current
____
10
15
600
900
A
t
CDR
(3)
Chip Deselect to Data Retention Tim
CS > V
HC
V
IN
> V
HC
or <
V
LC
0
____
____
____
____
ns
t
R
(3)
Operation Recovery Time
t
RC
(2)
____
____
____
____
ns
I
I
LI
I
(3)
Input Leakage Current
____
____
____
2
2
A
2986 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2986 tbl 10
6.42
IDT7187S/L
CMOS Static RAM 64K (64K x 1-Bit) Military Temperature Range
5
AC Electrical Characteristics
(V
CC
= 5.0V 10%)
NOTE:
1. This parameter guaranteed but not tested.
Symbol
Parameter
7187S25
7187L25
7187S35/45
7187L35/45
7187S55
7187L55
7187S70
7187L70
7187S85
7187L85
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
25
____
35/45
____
55
____
70
____
85
____
ns
t
AA
Address Access Time
____
25
____
35/45
____
55
____
70
____
85
ns
t
ACS
Chip Select Access Time
____
25
____
35/45
____
55
____
70
____
85
ns
t
OH
Output Hold from Address Change
5
____
5
____
5
____
5
____
5
____
ns
t
LZ
(1)
Output Select to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
ns
t
HZ
(1)
Chip Desele ct to Output in High-Z
____
12
____
17/20
____
30
____
30
____
40
ns
t
PU
(1)
Chip Sele ct to Power Up Time
0
____
0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
20
____
30/35
____
35
____
35
____
40
ns
2986 tbl 11
Timing Waveform of Read Cycle No. 1
(1,2)
Timing Waveform of Read Cycle No. 2
(1,3)
NOTES:
1.
WE is HIGH for Read cycle.
2.
CS is LOW for Read cycle.
3. Address valid prior to or coincident with
CS transition LOW.
4. Transition is measured 200mV from steady state voltage with specified loading in Figure 2.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
2986 drw 07
ADDRESS
DATA
t
RC
t
AA
OUT
t
OH
PREVIOUS DATA VALID
DATA VALID
(5)
2986 drw 08
DATA
OUT
CS
t
ACS
(4)
t
LZ
(4)
HZ
t
t
PD
t
PU
I
CC
I
SB
SUPPLY
CURRENT
V
CC
t
RC (5)
HIGH
IMPEDANCE
DATA VALID
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