FEBRUARY 2001
DSC-2989/09
1
2000 Integrated Device Technology, Inc.
Features
x
x
x
x
x
High-speed (equal access and cycle times)
Military: 25/35/45/55/70/85ns (max.)
x
x
x
x
x
Low power consumption
x
x
x
x
x
Battery backup operation -- 2V data retention
(L version only)
x
x
x
x
x
Available in high-density industry standard 22-pin, 300 mil
ceramic DIP
x
x
x
x
x
Produced with advanced CMOS technology
x
x
x
x
x
Inputs/outputs TTL-compatible
x
x
x
x
x
Military product compliant to MIL-STD-883, Class B
Description
The IDT7188 is a 65,536-bit high-speed static RAM organized as
16K x 4. It is fabricated using IDT's high-performance, high-reliability
technology -- CMOS. This state-of-the-art technology, combined with
Functional Block Diagram
A
0
DECODER
65,536-BIT
MEMORY ARRAY
COLUMN I/O
2989 drw 01
INPUT
DATA
CONTROL
WE
CS
GND
A
13
I/O
0
I/O
1
I/O
2
I/O
3
V
CC
,
innovative circuit design techniques, provides a cost effective approach
for memory intensive applications.
Access times as fast as 25ns are available. The IDT7188 offers a
reduced power standby mode, I
SB1
, which is activated when
CS goes
HIGH. This capability significantly decreases power while enhancing
system reliability. The low-power version (L) version also offers a battery
backup data retention capability where the circuit typically consumes only
30W operating from a 2V battery.
All inputs and outputs are TTL-compatible and operate from a single
5V supply. The IDT7188 is packaged in a 22-pin, 300 mil ceramic DIP
providing excellent board-level packing densities.
Military grade product is manufactured in compliance with the latest
revision of MIL-STD-883, Class B, making it ideally suited to military
temperature applications demanding the highest level of performance
and reliability.
CMOS Static RAM
64K (16K x 4-Bit)
IDT7188S
IDT7188L
2
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
Absolute Maximum Ratings
(1)
Recommended DC Operating
Conditions
Recommended Operating
Temperature and Supply Voltage
Pin Configuration
Capacitance
(T
A
= +25C, f = 1.0MHz, V
CC
= 0V)
Pin Descriptions
Truth Table
(1)
NOTE:
1. H = V
IH
, L = V
IL
, X = don't care.
DIP
Top View
2989 drw 02
5
6
7
8
9
10
11
1
2
3
4
22
21
20
19
18
17
D22-1
A
0
A
1
A
2
A
3
A
4
A
5
A
6
A
7
V
CC
A
13
A
11
A
10
I/O
3
16
15
GND
I/O
2
I/O
1
I/O
0
CS
14
A
12
WE
A
8
A
9
13
12
,
Name
Description
A
0
- A
13
Address Inputs
CS
Chip Select
WE
Write Enable
I/O
0
- I/O
3
Data Input/Output
V
CC
Power
GND
Ground
2989 tbl 01
Mode
CS
WE
I/O
Power
Standby
H
X
High-Z
Standby
Read
L
H
D
OUT
Active
Write
L
L
D
IN
Active
2989 tbl 02
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
Symbol
Rating
Value
Unit
V
TERM
Terminal Voltage with Respect to GND
-0.5 to +7.0
V
T
A
Operating Temperature
-55 to +125
o
C
T
BIAS
Temperature Under Bias
-65 to +135
o
C
T
STG
Storage Temperature
-65 to +150
o
C
P
T
Power Dissipation
1.0
W
I
OUT
DC Output Current
50
mA
2989 tbl 03
NOTE:
1. This parameter is determined by device characterization, but is not production
tested.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 0V
6
pF
C
I/O
I/O Capacitance
V
OUT
= 0V
6
pF
2989 tbl 04
NOTE:
1. V
IL
(min.) = 3.0V for pulse width less than 20ns,once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.2
____
6.0
V
V
IL
Input Low Voltage
-0.5
(1)
____
0.8
V
2989 tbl 05
Grade
Temperature
GND
Vcc
Military
-55
O
C to +125
O
C
0V
5V 10%
2989 tbl 06
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
3
DC Electrical Characteristics
(V
CC
= 5.0V 10%)
DC Electrical Characteristics
(1)
(V
CC
= 5V 10%, V
LC
= 0.2V, V
HC
= V
CC
- 0.2V)
Symbol
Parameter
Test Conditions
IDT7188S
IDT7188L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
V
CC
= Max., V
IN
=
GND to V
CC
____
10
____
5
A
|I
LO
|
Output Leakage Current
V
CC
= Max.,
CS = V
IH
, V
OUT
= GND to V
CC
____
10
____
5
A
V
OL
Output Low Voltage
I
OL
= 10mA, V
CC
= Min.
____
0.5
____
0.5
V
I
OL
= 8mA, V
CC
= Min.
____
0.4
____
0.4
V
OH
Output High Voltage
I
OH
= -4mA, V
CC
= Min.
2.4
____
2.4
____
V
2989 tbl 07
NOTES:
1. All values are maximum guaranteed values.
2. At f = f
MAX
address and data inputs are cycling at the maximum frequency of read cycles of 1/t
RC
. f = 0 means no input lines change.
Symbol
Parameter
Power
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Unit
I
CC1
Operating Power
Supply Current
CS = V
IL
, Outputs Open
V
CC
= Max., f
=
0
(2)
S
105
105
105
105
105
105
mA
L
80
80
80
80
80
80
I
CC2
Dynamic Operating Current
CS = V
IL
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
S
155
140
140
140
140
140
mA
L
120
115
110
110
110
105
I
SB
Standby Power Supply
Current (TTL Level)
CS > V
IH
, Outputs Open
V
CC
= Max., f = f
MAX
(2)
S
60
50
50
50
50
50
mA
L
40
40
35
35
35
35
I
SB1
Full Standby Power
Supply Current (CMOS Level)
CS > V
HC
, V
CC
= Max., V
IN
> V
HC
or V
IN
< V
LC
, f = 0
(2)
S
20
20
20
20
20
20
mA
L
1.5
1.5
1.5
1.5
1.5
1.5
2989 tbl 08
4
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
Data Retention Characteristics
(L Version Only) (V
HC
= V
CC
- 0.2V)
Low V
CC
Data Retention Waveform
AC Test Conditions
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
HZ
, t
LZ
, t
WZ
, t
OHZ
and t
OW
)
*Includes scope and jig capacitances
2989 drw 03
DATA
RETENTION
MODE
4.5V
4.5V
V
DR
2V
V
IH
V
IH
t
R
t
CDR
V
CC
CS
V
DR
,
2989 drw 04
480
30pF*
255
DATA
OUT
5V
,
2989 drw 05
480
5pF*
255
DATA
OUT
5V
,
NOTES:
1. T
A
= +25C.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but is not production tested.
Typ.
(1)
V
CC
@
Max.
V
CC
@
Symbol
Parameter
Test
Condition
Min.
2.0V
3.0V
2.0V
3.0V
Unit
V
DR
V
CC
for Data Retention
____
2.0
____
____
____
____
V
I
CCDR
Data Retention Current
____
10
15
600
900
A
t
CDR
(3)
Chip Deselect to Data Retention Time
CS > V
HC
V
IN
> V
HC
or
< V
LC
0
____
____
____
____
ns
t
R
(3)
Operation Recovery Time
t
RC
(2)
____
____
____
____
ns
I
I
LI
I
(3)
Input Leakage Current
____
____
____
2
2
A
2989 tbl 09
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
5ns
1.5V
1.5V
See Figures 1 and 2
2989 tbl 10
6.42
IDT7188S/L
CMOS Static RAM 64K (16K x 4-Bit) Military Temperature Range
5
Timing Waveform of Read Cycle No. 2
(1,3)
NOTES:
1.
WE is HIGH for Read cycle.
2.
CS is LOW for Read cycle.
3. Address valid prior to or coincident with
CS transition LOW.
4. Transition is measured 200mV from steady state voltage.
5. All Read cycle timings are referenced from the last valid address to the first transitioning address.
Timing Waveform of Read Cycle No. 1
(1,2)
AC Electrical Characteristics
(V
CC
= 5.0V 10%)
ADDRESS
DATA
OUT
2989 drw 06
t
RC
t
AA
t
OH
PREVIOUS DATA VALID
DATA VALID
(5)
,
DATA
OUT
CS
I
CC
I
SB
V
CC
SUPPLY
CURRENT
2989 drw 07
t
ACS
(4)
t
LZ
(4)
t
HZ
t
PD
t
PU
(5)
t
RC
DATA VALID
HIGH IMPEDANCE
,
NOTE:
1. This parameter is guaranteed by device characterization but is not production tested.
Symbol
Parameter
7188S25
7188L25
7188S35
7188L35
7188S45
7188L45
7188S55
7188L55
7188S70
7188L70
7188S85
7188L85
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Read Cycle
t
RC
Read Cycle Time
25
____
35
--
45
--
55
____
70
____
85
____
ns
t
AA
Address Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
t
ACS
Chip Select Access Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
t
OH
Output Hold from Address Change
5
____
5
____
5
____
5
____
5
____
5
____
ns
t
LZ
(1)
Output Select to Output in Low-Z
5
____
5
____
5
____
5
____
5
____
5
____
ns
t
HZ
(1)
Chip Deselect to Output in High-Z
____
10
____
14
____
14
____
20
____
25
____
30
ns
t
PU
(1)
Chip Select to Power Up Time
0
____
0
____
0
____
0
____
0
____
0
____
ns
t
PD
(1)
Chip Deselect to Power Down Time
____
25
____
35
____
45
____
55
____
70
____
85
ns
2989 tbl 11
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