AUGUST 2001
DSC-5326/00
1
2001 Integrated Device Technology, Inc.
Features
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x
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x
x
64K x 16 advanced high-speed CMOS Static RAM
x
x
x
x
x
Equal access and cycle times
-- Commercial: 10/12/15/20ns
-- Industrial: 12/15/20ns
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x
x
x
x
One Chip Select plus one Output Enable pin
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x
x
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x
Bidirectional data inputs and outputs directly
LVTTL-compatible
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x
x
x
x
Low power consumption via chip deselect
x
x
x
x
x
Upper and Lower Byte Enable Pins
x
x
x
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x
Single 2.5V power supply
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x
x
x
x
Available in 44-pin Plastic SOJ, 44-pin TSOP, and 48-Ball
Plastic FBGA packages
Description
The IDT71T016 is a 1,048,576-bit high-speed Static RAM organized
as 64K x 16. It is fabricated using IDT's high-perfomance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs.
The IDT71T016 has an output enable pin which operates as fast as
5ns, with address access times as fast as 10ns. All bidirectional inputs and
outputs of the IDT71T016 are LVTTL-compatible and operation is from a
single 2.5V supply. Fully static asynchronous circuitry is used, requiring
no clocks or refresh for operation.
The IDT71T016 is packaged in a JEDEC standard a 44-pin Plastic
SOJ, 44-pin TSOP Type II, and a 48-ball plastic 7 x 7 mm FBGA.
Functional Block Diagram
2.5V CMOS Static RAM
1 Meg (64K x 16-Bit)
Advance
Information
IDT71T016SA
Output
Enable
Buffer
Address
Buffers
Chip
Enable
Buffer
Write
Enable
Buffer
Byte
Enable
Buffers
OE
A
0
A
15
Row / Column
Decoders
CS
WE
BHE
BLE
64K x 16
Memory
Array
Sense
Amps
and
Write
Drivers
16
Low
Byte
I/O
Buffer
8
8
8
8
I/O
8
I/O
15
I/O
7
I/O
0
5326 drw 01
High
Byte
I/O
Buffer
6.42
2
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
1
2
3
4
5
6
A
BLE
OE
A
0
A
1
A
2
NC
B
I/O
8
BHE
A
3
A
4
CS
I/O
0
C
I/O
9
I/O
10
A
5
A
6
I/O
1
I/O
2
D
V
SS
I/O
11
NC
A
7
I/O
3
V
DD
E
V
DD
I/O
12
NC
NC
I/O
4
V
SS
F
I/O
14
I/O
13
A
14
A
15
I/O
5
I/O
6
G
I/O
15
NC
A
12
A
13
WE
I/O
7
H
NC
A
8
A
9
A
10
A
11
NC
5326 tbl 02a
Pin Configurations
TSOP
Top View
Pin Description
Truth Table
(1)
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
A
0
A
15
Address Inputs
Input
CS
Chip Select
Input
WE
Write Enable
Input
OE
Output Enable
Input
BHE
High Byte Enable
Input
BLE
Low Byte Enable
Input
I/O
0
I/O
15
Data Input/Output
I/O
V
DD
2.5V Power
Power
V
SS
Ground
Gnd
5326 tbl 01
CS
OE
WE
BLE
BHE
I/O
0
-I/O
7
I/O
8
-I/O
15
Function
H
X
X
X
X
High-Z
High-Z
Deselected Standby
L
L
H
L
H
DATA
OUT
High-Z
Low Byte Read
L
L
H
H
L
High-Z
DATA
OUT
High Byte Read
L
L
H
L
L
DATA
OUT
DATA
OUT
Word Read
L
X
L
L
L
DATA
IN
DATA
IN
Word Write
L
X
L
L
H
DATA
IN
High-Z
Low Byte Write
L
X
L
H
L
High-Z
DATA
IN
High Byte Write
L
H
H
X
X
High-Z
High-Z
Outputs Disabled
L
X
X
H
H
High-Z
High-Z
Outputs Disabled
5326 tbl 02
FBGA (BF48-1)
Top View
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
I/O
7
NC
A
12
A
13
A
14
A
15
WE
I/O
6
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
I/O
1
I/O
0
CS
A
0
A
1
A
2
A
3
A
4
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
A
6
A
7
OE
BHE
BLE
I/O
15
I/O
14
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
I/O
9
I/O
8
A
8
A
9
A
10
A
11
NC
A
5
NC
SO44-1
SO44-2
5326 drw 02
6.42
3
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
Parameter
71T016SA10
71T016SA12
71T016SA15
71T016SA20
Symbol
Com'l
Com'l
Ind
Com'l
Ind
Com'l
Ind
Unit
I
CC
Dynamic Operating Current
CS < V
LC
,
Outputs Open, V
DD
= Max., f = f
MAX
(3)
Max.
160
150
160
130
130
120
120
mA
Typ.
(4)
125
120
____
110
____
110
____
I
SB
Dynamic Standby Power Supply Current
CS > V
HC
,
Outputs Open, V
DD
= Max., f = f
MAX
(3)
45
40
45
35
35
30
30
mA
I
SB
1
Full Standby Power Supply Current (static)
CS > V
HC
,
Outputs Open, V
DD
= Max., f = 0
(3)
10
15
15
15
15
15
15
mA
5326 tbl 8
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
Capacitance
(T
A
= +25C, f = 1.0MHz)
Recommended DC Operating
Conditions
DC Electrical Characteristics
(1,2)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
0.2V)
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
0.2V (High).
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
); f = 0 means no address input lines are changing
.
4. Typical values are measured at 2.5V, 25C and with equal read and write cycles.
Symbol
Rating
Value
Unit
V
DD
Supply Voltage Relative
to V
SS
0.3 to +3.6
V
V
IN
, V
OUT
Terminal Voltage Relative
to V
SS
0.3 to V
DD
+0.3
V
T
BIAS
Temperature Under Bias
55 to +125
o
C
T
STG
Storage Temperature
55 to +125
o
C
P
T
Power Dissipation
1.25
W
I
OUT
DC Output Current
50
mA
5326 tbl 03
Grade
Temperature
V
SS
V
DD
Commercial
0C to +70C
0V
See Below
Industrial
-40C to +85C
0V
See Below
5326 tbl 04
Sym bol
Param eter
Min.
Typ.
Max.
Unit
V
DD
S up p ly Vo ltag e
2.375
2.5
2.625
V
V ss
Gro und
0
0
0
V
V
IH
Inp ut Hig h Vo ltag e
1.7
____
V
DD
+0.3
V
V
IL
Inp ut Lo w Vo ltag e
0.3
____
0.7
V
5326 tbl 05
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
6
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5326 tbl 06
Symbol
Parameter
Test Condition
IDT71T016SA
Unit
Min.
Max.
|I
LI
|
Input Leakage Current
V
DD
= Max., V
IN
= V
SS
to V
DD
___
5
A
|I
LO
|
Output Leakage Current
V
DD
= Max.,
CS = V
IH
, V
OUT
= V
SS
to V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= 2.0mA, V
DD
= Min.
___
0.7
V
V
OH
Output High Voltage
I
OH
= 2.0mA, V
DD
= Min.
1.7
___
V
5326 tbl 07
6.42
4
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
AC Test Conditions
AC Test Loads
Figure 3. Output Capacitive Derating
Figure 1. AC Test Load
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
*Including jig and scope capacitance.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
0V to 2.5V
1.5ns
(V
DD
/2)
(V
DD
/2)
See Figure 1, 2 and 3
5326 tbl 09
+1.25V
50
I/O
Z
0
= 50
5326 drw 03
30pF
5326 drw 04
320
350
5pF*
DATA
OUT
2.5V
1
2
3
4
5
6
7
20 40 60 80 100 120 140 160 180 200
t
AA,
t
ACS
(Typical, ns)
CAPACITANCE (pF)
8
5326 drw 05
6.42
5
IDT71T016SA, 2.5V CMOS Static RAM
1 Meg (64K x 16-Bit) Commercial and Industrial Temperature Ranges
71T016SA10
(2)
71T016SA12
71T016SA15
71T016SA20
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
20
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
____
20
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
____
20
ns
t
CLZ
(1)
Chip Select Lo w to Output in Low-Z
4
____
4
____
5
____
5
____
ns
t
CHZ
(1)
Chip Select Hig h to Output in High-Z
____
5
____
6
____
6
____
8
ns
t
OE
Output Enable Low to Output Valid
____
5
____
6
____
7
____
8
ns
t
OLZ
(1)
Output Enable Lo w to Output in Low-Z
0
____
0
____
0
____
0
____
ns
t
OHZ
(1)
Output Enable Hig h to Output in High-Z
____
5
____
6
____
6
____
8
ns
t
OH
Output Hold from Address Change
4
--
4
--
4
--
4
--
ns
t
BE
Byte Enable Low to Output Valid
--
5
--
6
--
7
____
8
ns
t
BLZ
(1)
Byte Enable Lo w to Output in Low-Z
0
____
0
____
0
____
0
____
ns
t
BHZ
(1)
Byte Enable Hig h to Output in High-Z
____
5
____
6
____
6
____
8
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End of Write
7
____
8
____
10
____
12
____
ns
t
CW
Chip Select Low to End of Write
7
____
8
____
10
____
12
____
ns
t
BW
Byte Enable Low to End of Write
7
____
8
____
10
____
12
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
t
WR
Address Ho ld from End of Write
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
7
____
8
____
10
____
12
____
ns
t
DW
Data Valid to End of Write
5
____
6
____
7
____
9
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
0
____
ns
t
OW
(1)
Write Enable Hig h to Output in Low-Z
3
____
3
____
3
____
3
____
ns
t
WHZ
(1)
Write Enable Lo w to Output in High-Z
____
5
____
6
____
6
____
8
ns
5326 tbl 10
Timing Waveform of Read Cycle No. 1
(1,2,3)
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3.
OE, BHE, and BLE are LOW.
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
NOTES:
1. This parameter is guaranteed with the AC Load (Figure 2) by device characterization, but is not production tested.
2. 0
0
C to +70
0
C temperature range only.
D ATA
OU T
ADDRESS
5326 drw 06
t
R C
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
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