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Электронный компонент: 71V124SA

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1
2000- Integrated Device Technology, Inc.
AUGUST 2001
DSC-3873/06
Features
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x
x
x
x
128K x 8 advanced high-speed CMOS static RAM
x
x
x
x
x
JEDEC revolutionary pinout (center power/GND) for
reduced noise
x
x
x
x
x
Equal access and cycle times
Commercial: 10/12/15/20ns
Industrial: 12/15/20ns
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x
x
x
x
One Chip Select plus one Output Enable pin
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x
x
x
x
Inputs and outputs are LVTTL-compatible
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x
x
x
x
Single 3.3V supply
x
x
x
x
x
Low power consumption via chip deselect
x
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x
Available in a 32-pin 300- and 400-mil Plastic SOJ, and
32-pin Type II TSOP packages.
Functional Block Diagram
Description
The IDT71V124 is a 1,048,576-bit high-speed static RAM organized
as 128K x 8. It is fabricated using IDT's high-performance, high-reliability
CMOS technology. This state-of-the-art technology, combined with inno-
vative circuit design techniques, provides a cost-effective solution for high-
speed memory needs. The JEDEC center power/GND pinout reduces
noise generation and improves system performance.
The IDT71V124 has an output enable pin which operates as fast as
5ns, with address access times as fast as 9ns available. All bidirec-
tional inputs and outputs of the IDT71V124 are LVTTL-compatible and
operation is from a single 3.3V supply. Fully static asynchronous
circuitry is used; no clocks or refreshes are required for operation.
ADDRESS
DECODER
1,048,576-BIT
MEMORY ARRAY
I/O CONTROL


A
0
A
16
3873 drw 01
8
8
I/O
0
- I/O
7
8


CONTROL
LOGIC
WE
OE
CS
.
3.3V CMOS Static RAM
1 Meg (128K x 8-Bit)
Center Power &
Ground Pinout
IDT71V124SA
2
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
Truth Table
(1)
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
DC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
Pin Configuration
SOJ and TSOP
Top View
Capacitance
(T
A
= +25C, f = 1.0MHz, SOJ package)
5
6
7
8
9
10
11
12
A
0
A
1
A
2
1
2
3
4
32
31
30
29
28
27
26
25
24
23
22
21
A
15
A
3
CS
I/O
1
V
DD
A
14
OE
I/O
7
I/O
6
GND
I/O
5
3873 drw 02
GND
13
20
14
19
15
18
16
A
7
17
I/O
2
I/O
3
WE
A
4
A
5
A
6
A
12
A
11
A
10
A
9
A
8
SO32-2
SO32-3
SO32-4
I/O
0
A
16
A
13
V
DD
I/O
4
.
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliabilty.
Symbol
Rating
Value
Unit
V
DD
Supply Voltage Relative
to GND
-0.5 to +4.6
V
V
IN
, V
OUT
Terminal Voltage Relative
to GND
-0.5 to V
DD
+0.5
V
T
A
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature
-40 to +85
T
BIAS
Temperature Under Bias
-55 to +125
o
C
T
STG
Storage Temperature
-55 to +125
o
C
P
T
Power Dissipation
1.25
W
I
OUT
DC Output Current
50
mA
3873 tbl 02
NOTE:
1. H = V
IH
, L = V
IL
, X = Don't care.
CS
OE
WE
I/O
Function
L
L
H
DATA
OUT
Read Data
L
X
L
DATA
IN
Write Data
L
H
H
High-Z
Output Disabled
H
X
X
High-Z
Deselected Standby
3873 tbl 01
NOTE:
1. This parameter is guaranteed by device characterization, but is not production tested.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
6
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
3873 tbl 03
NOTES:
1. For 71V124SA10 only.
2. For all speed grades except 71V124SA10.
3. V
IH
(max.) = V
DD
+2V for pulse width less than 5ns, once per cycle.
4. V
IL
(min.) = 2V for pulse width less than 5ns, once per cycle.
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
(1)
Supply Voltage
3.15
3.3
3.6
V
V
DD
(2)
Supply Voltage
3.0
3.3
3.6
V
V
SS
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
DD
+0.3
(3)
V
V
IL
Input Low Voltage
0.5
(1)
____
0.8
V
3873 tbl 04
Symbol
Parameter
Test Conditions
Min.
Max.
Unit
|I
LI
|
Input Leakage Current
V
DD
= Max., V
IN
=
GND to V
DD
___
5
A
|I
LO
|
Output Leakage Current
V
DD
= Max.,
CS
=
V
IH
, V
OUT
=
GND to V
DD
___
5
A
V
OL
Output Low Voltage
I
OL
= 8mA, V
DD
= Min.
___
0.4
V
V
OH
Output High Voltage
I
OH
= 4mA, V
DD
= Min.
2.4
___
V
3873 tbl 05
Recommended Operating Tempera-
ture and Supply Voltage
Grade
Temperature
GND
V
DD
Commercial
0C to +70C
0V
See Below
Industrial
-40C to +85C
0V
See Below
3873 tbl 02a
6.42
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
3
+1.5V
50
I/O
Z
0
= 50
3873 drw 03
30pF
.
*Including jig and scope capacitance.
Figure 2. AC Test Load
(for t
CLZ
, t
OLZ
, t
CHZ
, t
OHZ
, t
OW,
and t
WHZ
)
Figure 1. AC Test Load
AC Test Conditions
DC Electrical Characteristics
(1, 2)
(V
DD
= Min. to Max., V
LC
= 0.2V, V
HC
= V
DD
0.2V)
3873 drw 04
320
350
5pF*
DATA
OUT
3.3V
NOTES:
1. All values are maximum guaranteed values.
2. All inputs switch between 0.2V (Low) and V
DD
0.2V (High).
3. f
MAX
= 1/t
RC
(all address inputs are cycling at f
MAX
)
;
f = 0 means no address input lines are changing.
Symbol
Parameter
71V124SA10
71V124SA12
71V124SA15
71V124SA20
Unit
Com'l Only
Com'l
Ind
Com'l
Ind
Com'l
Ind
I
CC
Dynamic Operating Current
CS < V
LC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
145
130
140
100
120
95
115
mA
I
SB
Dynamic Standby Power Supply Curren
t
CS > V
HC
, Outputs Open, V
DD
= Max., f = f
MAX
(3)
45
40
40
35
40
30
35
mA
I
SB1
Full Standby Power Supply Current (static)
CS > V
HC
, Outputs Open, V
DD
= Max., f = 0
(3)
10
10
10
10
10
10
10
mA
3873 tbl 06
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
AC Test Load
GND to 3.0V
3ns
1.5V
1.5V
See Figure 1 and 2
3873 tbl 07
4
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
AC Electrical Characteristics
(V
DD
= Min. to Max., Commercial and Industrial Temperature Ranges)
NOTES:
1. 0C to +70C temperature range only.
2. This parameter guaranteed with the AC load (Figure 2) by device characterization, but is not production tested.
Symbol
Parameter
71V124SA10
(1)
71V124SA12
71V124SA15
71V124SA20
Unit
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
10
____
12
____
15
____
20
____
ns
t
AA
Address Access Time
____
10
____
12
____
15
____
20
ns
t
ACS
Chip Select Access Time
____
10
____
12
____
15
____
20
ns
t
CLZ
(2)
Chip Select to Output in Low-Z
4
____
4
____
4
____
4
____
ns
t
CHZ
(2)
Chip Deselect to Output in High-Z
0
5
0
6
0
7
0
8
ns
t
OE
Output Enable to Output Valid
____
5
____
6
____
7
____
8
ns
t
OLZ
(2)
Output Enable to Output in Low-Z
0
____
0
____
0
____
0
____
ns
t
OHZ
(2)
Output Disable to Output in High-Z
0
5
0
5
0
5
0
7
ns
t
OH
Output Hold from Address Change
4
____
4
____
4
____
4
____
ns
WRITE CYCLE
t
WC
Write Cycle Time
10
____
12
____
15
____
20
____
ns
t
AW
Address Valid to End-of-Write
7
____
8
____
10
____
12
____
ns
t
CW
Chip Select to End-of-Write
7
____
8
____
10
____
12
____
ns
t
AS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
t
WP
Write Pulse Width
7
____
8
____
10
____
12
____
ns
t
WR
Write Recovery Time
0
____
0
____
0
____
0
____
ns
t
DW
Data Valid to End-of-Write
5
____
6
____
7
____
9
____
ns
t
DH
Data Hold Time
0
____
0
____
0
____
0
____
ns
t
OW
(2)
Output Active from End-of-Write
3
____
3
____
3
____
4
____
ns
t
WHZ
(2)
Write Enable to Output in High-Z
0
5
0
5
0
5
0
8
ns
3873 tbl 08
6.42
IDT71V124SA, 3.3V CMOS Static RAM
1 Meg (128K x 8-Bit) Center Power & Ground Pinout Commercial and Industrial Temperature Ranges
5
NOTES:
1.
WE is HIGH for Read Cycle.
2. Device is continuously selected,
CS is LOW.
3. Address must be valid prior to or coincident with the later of
CS transition LOW; otherwise t
AA
is the limiting parameter.
4.
OE is LOW.
5. Transition is measured 200mV from steady state.
Timing Waveform of Read Cycle No. 1
(1)
Timing Waveform of Read Cycle No. 2
(1, 2, 4)
ADDRESS
3873 drw 05
OE
CS
DATA
OUT
(5)
(5)
(5)
(5)
DATA
OUT
VALID
HIGH IMPEDANCE
t
AA
t
RC
t
OE
t
ACS
t
OLZ
t
CHZ
t
CLZ
(3)
t
OHZ
.
DATA
OUT
ADDRESS
3873 drw 06
t
RC
t
AA
t
OH
t
OH
DATA
OUT
VALID
PREVIOUS DATA
OUT
VALID
.