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2001 Integrated Device Technology, Inc.
AUGUST 2001
DSC-3026/8
1
HIGH SPEED 3.3V
2K X 8 DUAL-PORT
STATIC RAM WITH INTERRUPTS
IDT71V321S/L
IDT71V421S/L
.eatures
x
x
x
x
x
High-speed access
Commercial: 25/35/55ns (max.)
Industrial: 25ns (max.)
x
x
x
x
x
Low-power operation
IDT71V321/IDT71V421S
--
Active: 325mW (typ.)
--
Standby: 5mW (typ.)
IDT71V321/V421L
--
Active: 325mW (typ.)
--
Standby: 1mW (typ.)
x
x
x
x
x
Two
INT flags for port-to-port communications
.unctional Block Diagram
NOTES:
1. IDT71V321 (MASTER):
BUSY is an output. IDT71V421 (SLAVE): BUSY is input.
2.
BUSY and INT are totem-pole outputs.
x
x
x
x
x
MASTER IDT71V321 easily expands data bus width to 16-
or-more-bits using SLAVE IDT71V421
x
x
x
x
x
On-chip port arbitration logic (IDT71V321 only)
x
x
x
x
x
BUSY output flag on IDT71V321; BUSY input on IDT71V421
x
x
x
x
x
Fully asynchronous operation from either port
x
x
x
x
x
Battery backup operation--2V data retention (L only)
x
x
x
x
x
TTL-compatible, single 3.3V power supply
x
x
x
x
x
Available in 52-pin PLCC, 64-pin TQFP and STQFP
packages
x
x
x
x
x
Industrial temperature range (40C to +85C) is available
for selected speeds
I/O
Control
Address
Decoder
MEMORY
ARRAY
ARBITRATION
and
INTERRUPT
LOGIC
Address
Decoder
I/O
Control
R/
W
L
CE
L
OE
L
BUSY
L
A
10L
A
0L
3026 drw 01
I/O
0L
- I/O
7L
CE
L
OE
L
R/
W
L
INT
L
BUSY
R
I/O
0R
-I/O
7R
A
10R
A
0R
INT
R
CE
R
OE
R
(2)
(1,2)
(1,2)
(2)
R/
W
R
CE
R
OE
R
11
11
R/
W
R
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
2
IDT71V321/421J
J52-1
(4)
52-Pin PLCC
Top View
(5)
INDEX
I/O
A
A
A
A
A
A
A
A
A
I/O
I/O
I/O
1L
2L
3L
4L
5L
6L
7L
8L
9L
0L
1L
3L
2L
OE
R
A
A
A
A
A
A
A
A
A
A
NC
I/O
0R
1R
2R
3R
4R
5R
6R
7R
8R
9R
7R
4
L
5
L
6
L
7
L
N
C
G
N
D
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
I
/
O
0
R
1
R
2
R
3
R
4
R
6
R
5
R
A
0
L
O
E
L
A
1
0
L
I
N
T
L
B
U
S
Y
L
R
/
W
L
C
E
L
V
C
C
C
E
R
R
/
W
R
B
U
S
Y
R
I
N
T
R
A
1
0
R
1
2
3
4
5
6
7
47
48
49
50
51
52
9
8
10
11
12
13
14
15
16
17
18
19
20
27
26
25
24
23
22
21
33
32
31
30
29
28
35
34
36
37
38
39
40
41
42
43
44
45
46
3026 drw 02
,
Pin Configurations
(1,2,3)
Description
The IDT71V321/IDT71V421 are high-speed 2K x 8 Dual-Port
Static RAMs with internal interrupt logic for interprocessor communica-
tions. The IDT71V321 is designed to be used as a stand-alone 8-bit
Dual-Port RAM or as a "MASTER" Dual-Port RAM together with the
IDT71V421 "SLAVE" Dual-Port in 16-or-more-bit memory system ap-
plications results in full speed, error-free operation without the need for
additional discrete logic.
The device provides two independent ports with separate control,
address, and I/O pins that permit independent, asynchronous access
for reads or writes to any location in memory. An automatic power
down feature, controlled by
CE, permits the on chip circuitry of each
port to enter a very low standby power mode.
Fabricated using IDT's CMOS high-performance technology, these
devices typically operate on only 325mW of power. Low-power (L)
versions offer battery backup data retention capability, with each Dual-
Port typically consuming 200W from a 2V battery.
The IDT71V321/IDT71V421 devices are packaged in a 52-pin
PLCC, a 64-pin TQFP (thin quad flatpack), and a 64-pin STQFP
(super thin quad flatpack).
INDEX
IDT71V321/421PF or TF
PP64-1
(4)
&
PN64-1
(4)
64-Pin STQFP
64-Pin TQFP
Top View
(5)
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
46
45
44
43
42
41
40
39
38
37
36
35
34
47
48
33
1
7
1
8
1
9
2
0
3
2
3
1
3
0
2
9
2
8
2
7
2
6
2
5
2
4
2
3
2
2
2
1
4
9
5
0
5
1
5
2
6
3
6
2
6
1
6
0
5
9
5
8
5
7
5
6
5
5
5
4
5
3
6
4
I/O
6R
N/C
A
0R
A
1R
A
2R
A
3R
A
4R
A
5R
A
6R
A
7R
A
8R
A
9R
I/O
7R
OE
R
N/C
N/C
I/O
2L
A
0L
OE
L
A
1L
A
2L
A
3L
A
4L
A
5L
A
6L
A
7L
A
8L
A
9L
I/O
0L
I/O
1L
N/C
N/C
G
N
D
4
L
I
/
O
5
L
I
/
O
6
L
I
/
O
7
L
I
/
O
I
/
O
0
R
I
/
O
1
R
I
/
O
2
R
I
/
O
3
R
I
/
O
4
R
I
/
O
5
R
I
/
O
3
L
N
/
C
N
/
C
G
N
D
N
/
C
N
/
C
A
1
0
R
V
C
C
B
U
S
Y
L
R
/
W
L
C
E
R
R
/
W
R
B
U
S
Y
R
C
E
L
N
/
C
N
/
C
A
1
0
L
V
C
C
N
/
C
I
N
T
R
I
N
T
L
3026 drw 03
NOTES:
1. All V
CC
pins must be connected to power supply.
2. All GND pins must be connected to ground supply.
3. J52-1 package body is approximately .75 in x .75 in x .17 in.
PP64-1 package body is approximately 10mm x 10mm x 1.4mm.
PN64-1 package body is approximately 14mm x 14mm x 1.4mm.
4. This package code is used to reference the package diagram.
5. This text does not indicate orientation of the actual part-marking.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
3
Recommended DC Operating
Conditions
Absolute Maximum Ratings
(1)
Recommended Operating
Temperature and Supply Voltage
(1,2)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only
and functional operation of the device at these or any other conditions
above those indicated in the operational sections of the specification is not
implied. Exposure to absolute maximum rating conditions for extended
periods may affect reliability.
2. V
TERM
must not exceed V
CC
+ 10% for more than 25% of the cycle time or 10ns
maximum, and is limited to < 20mA for the period of V
TERM
> V
CC
+ 10%.
NOTES:
1. V
IL
(min.) = -1.5V for pulse width less than 20ns.
2. V
TERM
must not exceed Vcc + 0.3V.
NOTES:
1. This is the parameter T
A
. This is the "instant on" case temperature.
2. Industrial temperature: for specific speeds, packages and powers contact your
sales office.
Symbol
Rating
Commercial
& Industrial
Unit
V
TERM
(2)
Terminal Voltage
with Respect
to GND
-0.5 to +4.6
V
T
A
Operating
Temperature
0 to +70
C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-65 to +150
o
C
I
OUT
DC Output
Current
50
mA
3026 tbl 01
Grade
Ambient
Temperature
GND
Vcc
Commercial
0
O
C to +70
O
C
0V
3.3V
+
0.3V
Industrial
-40
O
C to +85
O
C
0V
3.3V
+
0.3V
3026 tbl 02
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
3.0
3.3
3.6
V
GND
Ground
0
0
0
V
V
IH
Input High Voltage
2.0
____
V
CC
+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
3026 tbl 03
Capacitance
(1)
(TA = +25C, f = 1.0MHz) TQ.P Only
Symbol
Parameter
Conditions
(2)
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
9
pF
C
OUT
Output Capacitance
V
OUT
= 3dV
10
pF
3026 tbl 04
NOTES:
1. This parameter is determined by device characterization but is not production
tested.
2. 3dv references the interpolated capacitance when the input and output signals
switch from 0V to 3V or from 3V to 0V.
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(V
CC
= 3.3V 0.3V)
Symbol
Parameter
Test Conditions
71V321S
71V421S
71V321L
71V421L
Unit
Min.
Max.
Min.
Max.
|I
LI
|
Input Leakage Current
(1)
V
CC
= 3.6V,
V
IN
= 0V to V
CC
___
10
___
5
A
|I
LO
|
Output Leakage Current
CE = V
IH
, V
OUT
= 0V to V
CC
V
CC
= 3.6V
___
10
___
5
A
V
OL
Output Low Voltage
I
OL
= 4mA
___
0.4
___
0.4
V
V
OH
Output High Voltage
I
OH
= -4mA
2.4
___
2.4
___
V
3026 tbl 05
NOTE:
1. At V
CC
< 2.0V input leakages are undefined.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
4
DC Electrical Characteristics Over the Operating
Temperature and Supply Voltage Range
(1,2)
(V
CC
= 3.3V 0.3V)
NOTES:
1. 'X' in part numbers indicates power rating (S or L).
2. V
CC
= 3.3V, T
A
= +25C, and are not production tested. I
CCDC
= 70mA (Typ.).
3. At f = f
MAX
, address and control lines (except Output Enable) are cycling at the maximum frequency read cycle of 1/t
RC
and using "AC Test Conditions" of input levels
of GND to 3V.
4. f = 0 means no address or control lines change. Applies only to inputs at CMOS level standby.
5. Port "A" may be either left or right port. Port "B" is opposite from port "A".
Symbol
Parameter
Test Condition
Version
71V321X25
71V421X25
Com'l
& Ind
71V321X35
71V421X35
Com'l Only
71V321X55
71V421X55
Com'l Only
Unit
Typ.
Max.
Typ.
Max.
Typ.
Max.
I
CC
Dynamic Operating
Current
(Both Ports Active)
CE = V
IL
, Outputs Disabled
SEM = V
IH
f = f
MAX
(3)
COM'L
S
L
55
55
130
100
55
55
125
95
55
55
115
85
mA
IND
S
L
55
55
150
130
___
___
___
___
I
SB1
Standby Current
(Both Ports - TTL
Level Inputs)
CE
R
=
CE
L
= V
IH
SEM
R
=
SEM
L
= V
IH
f = f
MAX
(3)
COM'L
S
L
15
15
35
20
15
15
35
20
15
15
35
20
mA
IND
S
L
15
15
50
35
___
___
___
___
I
SB2
Standby Current
(One Port - TTL
Level Inputs)
CE
"A"
= V
IL
and
CE
"B"
= V
IH
(5)
Active Port Outputs Disabled,
f=f
MAX
(3)
SEM
R
=
SEM
L
= V
IH
COM'L
S
L
25
25
75
55
25
25
70
50
25
25
60
40
mA
IND
S
L
25
25
95
75
___
___
___
___
I
SB3
Full Standby Current
(Both Po rts - All
CMOS Level Inputs)
Both Ports
CE
L
and
CE
R
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or
V
IN
< 0.2V, f = 0
(4)
SEM
R
=
SEM
L
> V
CC
- 0.2V
COM'L
S
L
1.0
0.2
5
3
1.0
0.2
5
3
1.0
0.2
5
3
mA
IND
S
L
1.0
0.2
10
6
___
___
___
___
I
SB4
Full Standby Current
(One Port - All
CMOS Level Inputs)
CE
"A"
< 0.2V and
CE
"B"
> V
CC
- 0.2V
(5)
SEM
R
=
SEM
L
> V
CC
- 0.2V
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
Active Port Outputs Disabled
f = f
MAX
(3)
COM'L
S
L
25
25
70
55
25
25
65
50
25
25
55
40
mA
IND
S
L
25
25
85
70
___
___
___
___
3026 tbl 06
Data Retention Characteristics
(L Version Only)
Symbol
Parameter
Test Condition
Min.
Typ.
(1)
Max.
Unit
V
DR
V
CC
for Data Retention
2.0
___
0
V
I
CCDR
Data Retention Current
V
CC
= 2
V,
CE > V
CC
- 0.2V
COM'L.
___
100
1500
A
t
CDR
(3)
Chip Deselect to Data
Retention Time
V
IN
> V
CC
- 0.2V or V
IN
< 0.2V
IND.
___
100
4000
A
0
___
___
V
t
R
(3)
Operation Recovery Time
t
RC
(2)
___
___
V
3026 tbl 07
NOTES:
1. V
CC
= 2V, T
A
= +25C, and is not production tested.
2. t
RC
= Read Cycle Time.
3. This parameter is guaranteed by device characterization but not production tested.
6.42
IDT71V321/71V421S/L
High Speed 3.3V 2K x 8 Dual-Port Static RAM with Interrupts Industrial and Commercial Temperature Ranges
5
Data Retention Waveform
V
CC
CE
3.0V
3.0V
DATA RETENTION MODE
t
CDR
t
R
V
IH
V
IH
V
DR
V
DR
2.0V
3026 drw 04
,
AC Test Conditions
590
30pF
435
DATA
OUT
590
435
5pF
DATA
OUT
3026 drw 05
3.3V
3.3V
BUSY
INT
Figure 1. AC Output Test Load
Figure 2. Output Test Load
(for t
HZ
, t
LZ
, t
WZ
, and t
OW
)
* Including scope and jig.
Input Pulse Levels
Input Rise/Fall Times
Input Timing Reference Levels
Output Reference Levels
Output Load
GND to 3.0V
5ns
1.5V
1.5V
Figures 1 and 2
3026 tbl 08
AC Electrical Characteristics Over the
Operating Temperature Supply Voltage Range
(2)
71V321X25
71V421X25
Com 'l
& Ind
71V321X35
71V421X35
Com 'l Only
71V321X55
71V421X55
Com 'l Only
Unit
Sym bol
Param eter
Min.
Max.
Min.
Max.
Min.
Max.
READ CYCLE
t
RC
Read Cycle Time
25
____
35
____
55
____
ns
t
AA
Address Access Time
____
25
____
35
____
55
ns
t
ACE
Chip Enable Access Time
____
25
____
35
____
55
ns
t
AOE
Output Enable Access Time
____
12
____
20
____
25
ns
t
OH
Output Hold from Address Change
3
____
3
____
3
____
ns
t
LZ
Output Low-Z Time
(1,2)
0
____
0
____
0
____
ns
t
HZ
Output High-Z Time
(1,2)
____
12
____
15
____
30
ns
t
PU
Chip Enable to Power Up Time
(2)
0
____
0
____
0
____
ns
t
PD
Chip Disable to Power Down Time
(2)
____
50
____
50
____
50
ns
3026 tbl 09
NOTES:
1. Transition is measured 0mV from Low or High-impedance voltage with Output Test Load (Figure 2).
2. This parameter is guaranteed by device characterization, but is not production tested.
3. 'X' in part numbers indicates power rating (S or L).