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Электронный компонент: 71V3548SA

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MAY 2002
DSC-5296/03
1
2002 Integrated Device Technology, Inc.
Pin Description Summary
Description
The IDT71V3548 are 3.3V high-speed 4,718,592-bit (4.5 Megabit)
synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or
writes and reads. Thus, they have been given the name ZBT
TM
, or
Zero Bus Turnaround.
Features
x
x
x
x
x
256K x 18 memory configurations
x
x
x
x
x
Supports high performance system speed - 133 MHz
(4.2 ns Clock-to-Data Access)
x
x
x
x
x
ZBT
TM
Feature - No dead cycles between write and read
cycles
x
x
x
x
x
Internally synchronized output buffer enable eliminates the
need to control
OE
x
x
x
x
x
Single R/
W (READ/WRITE) control pin
x
x
x
x
x
Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications
x
x
x
x
x
4-word burst capability (interleaved or linear)
x
x
x
x
x
Individual byte write (
BW
1
-
BW
4
) control (May tie active)
x
x
x
x
x
Three chip enables for simple depth expansion
x
x
x
x
x
3.3V power supply (5%), 3.3V I/O Supply (V
DDQ)
x
x
x
x
x
Optional Boundary Scan JTAG Interface (IEEE 1149.1
compliant)
x
x
x
x
x
Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array (fBGA)
A
0
-A
17
Address Inputs
Input
Synchronous
CE
1
, CE
2
,
CE
2
Chip Enables
Input
Synchronous
OE
Output Enable
Input
Asynchronous
R/
W
Read/Write Signal
Input
Synchronous
CEN
Clock Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV/
LD
Advance burst addre ss / Load new address
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
Static
TMS
Test Mode Select
Input
Synchronous
TDI
Test Data Input
Input
Synchronous
TCK
Test Clock
Input
N/A
TDO
Test Data Output
Output
Synchronous
TRST
JTAG Reset (Optional)
Input
Asynchronous
ZZ
Sleep Mode
Input
Synchronous
I/O
0
-I/O
15
, I/O
P1
-I/O
P2
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power, I/O Power
Supply
Static
V
SS
Ground
Supply
Static
5296 tbl 01
IDT71V3548S
IDT71V3548SA
256K x 18
3.3V Synchronous ZBT SRAM
3.3V I/O, Burst Counter
Pipelined Outputs
Address and control signals are applied to the SRAM during one
clock cycle, and two cycles later the associated data cycle occurs, be it
read or write.
The IDT71V3548 contain data I/O, address and control signal
registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.
A Clock Enable (
CEN) pin allows operation of the IDT71V3548
to be suspended as long as necessary. All synchronous inputs are
ignored when (
CEN) is high and the internal device registers will hold
their previous values.
There are three chip enable pins (
CE
1
, CE
2
,
CE
2
) that allow the user
to deselect the device when desired. If any one of these three are not
asserted when ADV/
LD is low, no new memory operation can be
initiated. However, any pending data transfers (reads or writes) will be
completed. The data bus will tri-state two cycles after chip is deselected
or a write is initiated.
The IDT71V3548 has an on-chip burst counter. In the burst
mode, the IDT71V3548 can provide four cycles of data for a single address
presented to the SRAM. The order of the burst sequence is defined by the
LBO input pin. The LBO pin selects between linear and interleaved burst
sequence. The ADV/
LD signal is used to load a new external address
(ADV/
LD = LOW) or increment the internal burst counter (ADV/LD =
HIGH).
The IDT71V3548 SRAMs utilize IDT's latest high-performance CMOS
process and are packaged in a JEDEC standard 14mm x 20mm 100- pin
plastic thin quad flatpack (TQFP) as well as a 119 ball grid array (BGA)
and 165 fine pitch ball grid array (fBGA).
6.42
2
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
TM
TM
TM
TM
TM
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Pin Definition
(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A
0
-A
17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combination of the rising
edge of CLK, ADV/
LD low, CEN low, and true chip enables.
ADV/
LD
Advance / Load
I
N/A
ADV/
LD is a synchronous input that is used to load the internal registers with new address and
control when it is sampled low at the rising edge of clock with the chip selected. When
ADV/
LD is low with the chip deselected, any burst in progress is terminated. When ADV/LD is
sampled high then the internal burst counter is advanced for any burst that was in progress.
The external addresses are ignored when ADV/
LD is sampled high.
R/W
Read / Write
I
N/A
R/W signal is a synchronous input that identifies whether the c urrent load cycle initiated is a
Read or Write access to the memory array. The data bus activ ity for the current cycle takes
place two clock cycles later.
CEN
Clock Enable
I
LOW
Synchronous Clock Enable Input. When
CEN is sampled high, all other synchronous inputs,
including clock are ignored and outputs remain unchang ed. The effect of CEN sampled high
on the device outputs is as if the low to high clock transition did not occur. For normal
operation, CEN must be sampled low at rising edge of clock.
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
Synchronous by te write enables. Each 9-bit byte has its own active low byte write enable. On
load write cycles (When R/W and ADV/LD are samp led low) the appropriate byte write signal
(
BW
1
-
BW
4
) must be valid. The byte write signal must also be valid on each cycle of a burst
write. Byte Write signals are ignored when R/
W is sampled high. The appropriate byte(s) of
data are written into the device two cycles later.
BW
1
-
BW
4
can all be tied low if always doing
write to the entire 36-bit word.
CE
1
,
CE
2
Chip Enables
I
LOW
Synchro nous active low chip enable.
CE
1
and
CE
2
are used with CE
2
to enable the
IDT71V3548. (
CE
1
or
CE
2
sampled high or CE
2
sampled low) and ADV/
LD low at the rising
edge of clock, initiates a deselect cycle. The ZBT
TM
has a two cycle deselect, i.e., the data
bus will tri-state two clock cycles after deselect is initiated.
CE
2
Chip Enable
I
HIGH
Synchronous active high chip enable. CE
2
is used with
CE
1
and
CE
2
to enable the chip. CE
2
has inverted polarity but otherwise identical to
CE
1
and
CE
2
.
CLK
Clock
I
N/A
This is the clock input to the IDT71V3548. Except for
OE, all timing references for the device
are made with respect to the rising edge of CLK.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.
LBO
Linear Burst Order
I
LOW
Burs t order selection input. When
LBO is high the Interleaved burst sequence is selected.
When
LBO is low the Linear burst sequence is selected. LBO is a static input and it must not
change during device operation.
OE
Output Enable
I
LOW
Asynchronous output enable.
OE must be low to read data from the 71V3548. When OE is
high the I/O pins are in a high-impedance state.
OE does not need to be actively controlled
for read and write cycles. In normal operation,
OE can be tied low.
TMS
Test Mode Select
I
N/A
Gives input command for TAP controller. Sampled on rising edge of TDK. This pin has an
internal pullup.
TDI
Test Data Input
I
N/A
Serial input of registers placed between TDI and TDO. Sampled on rising edge of TCK. This
pin has an internal pullup.
TCK
Test Clock
I
N/A
Clo ck input of TAP controller. Each TAP event is clocked. Test inputs are captured on rising
edge of TCK, while test outputs are driven from the falling edge of TCK. This pin has an
internal pullup.
TDO
Test Data Output
O
N/A
Serial output of registers placed between TDI and TDO. This outp ut is active depending on the
state of the TAP controller.
TRST
JTAG Reset
(Optional)
I
LOW
Optional Asynchronous JTAG reset. Can be used to reset the TAP controller, but not required.
JTAG reset occurs automatically at power up and also resets using TMS and TCK per IEEE
1149.1. If not used
TRST can be left floating. This pin has an internal pullup.
ZZ
Sleep Mode
I
HIGH
Synchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V3548 to its lowest power consumption le vel. Data retention is guaranteed in Sleep
Mode. This pin has an internal pulldown
V
DD
Power Supply
N/A
N/A
3.3V core power supply.
V
DDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
V
SS
Ground
N/A
N/A
Ground.
5296 tbl 02
6.42
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
TM
TM
TM
TM
TM
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
3
Recommended DC Operating
Conditions
NOTES:
1. V
IL
(min.) = 1.0V for pulse width less than t
CYC
/2, once per cycle.
2. V
IH
(max.) = +6.0V for pulse width less than t
CYC
/2, once per cycle.
Functional Block Diagram
Clk
D
Q
D
Q
D
Q
Address A [0:17]
Control Logic
Address
Control
DI
DO
I
nput
R
eg
i
s
t
e
r
5296 drw 01
Clock
Data I/O [0:15],
I/O P[1:2]
D
Q
Cl
k
Output Register
Mux
Sel
Gate
OE
CE
1, CE2,
CE
2
R/
W
CEN
ADV/
LD
BW
x
LBO
256x18 BIT
MEMORY ARRAY
,
JTAG
(SA Version)
TMS
TDI
TCK
TDO
TRST
(optional)
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core Supply Voltage
3.135
3.3
3.465
V
V
DDQ
I/O Supply Voltage
3.135
3.3
3.465
V
V
SS
Supply Voltage
0
0
0
V
V
IH
Input High Voltage - Inputs
2.0
____
V
DD
+0.3
V
V
IH
Input High Voltage - I/O
2.0
____
V
DDQ
+0.3
(2)
V
V
IL
Input Low Voltage
-0.3
(1)
____
0.8
V
5296 tbl 04
Recommended Operating
Temperature and Supply Voltage
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial
0C to +70C
0V
3.3V5%
3.3V5%
Industrial
-40C to +85C
0V
3.3V5%
3.3V5%
5296 tbl 05
NOTES:
1. T
A
is the "instant on" case temperature.
6.42
4
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
TM
TM
TM
TM
TM
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
Absolute Maximum Ratings
(1)
Pin Configuration - 256K x 18
100 Pin TQFP Capacitance
(1)
(T
A
= +25 C, f = 1.0MHz)
NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V
DD
as long as
the input voltage is
V
IH
.
2. Pins 83 and 84 are reserved for future 8M and 16M respectively.
3. Pin 64 does not have to be connected directly to V
SS
as long as the input
voltage is
V
IL
; on the latest die revision this pin supports ZZ (sleep
mode).
Top View
100 TQFP
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS
may cause permanent damage to the device. This is a stress rating only and
functional operation of the device at these or any other conditions above those
indicated in the operational sections of this specification is not implied. Exposure
to absolute maximum rating conditions for extended periods may affect
reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has
reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V
DDQ
during power
supply ramp up.
7. T
A
is the "instant on" case temperature.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Commercial &
Industrial Values
Unit
V
TERM
(2)
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
V
TERM
(3,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
+0.5
V
V
TERM
(5,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DDQ
+0.5
V
T
A
(7)
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature
-40 to +85
o
C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
P
T
Power Dissipation
2.0
W
I
OUT
DC Output Current
50
mA
5296 tbl 06
100 99 98 97 96 95 94 93 92 91 90
87 86 85 84 83 82 81
89 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
1
C
E
2
N
C
N
C
B
W
2
B
W
1
C
E
2
V
D
D
V
S
S
C
LK
R
/
W
C
E
N
O
E
A
D
V
/
LD
N
C
(2
)
N
C
(2
)
A
8
A
9
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
LB
O
A
15
A
14
A
13
A
12
A
11
V
D
D
V
S
S
A
0
A
1
A
2
A
3
A
4
A
5
NC
NC
V
DDQ
V
SS
NC
I/O
P2
I/O
15
I/O
14
V
SS
V
DDQ
I/O
13
I/O
12
V
SS
V
DD
I/O
11
I/O
10
V
DDQ
V
SS
I/O
9
I/O
8
NC
NC
V
SS
V
DDQ
NC
NC
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
NC
V
DDQ
V
SS
NC
I/O
P1
I/O
7
I/O
6
V
SS
V
DDQ
I/O
5
I/O
4
V
SS
V
DD
I/O
3
I/O
2
V
DDQ
V
SS
I/O
1
I/O
0
NC
NC
V
SS
V
DDQ
NC
NC
5296 drw 02
V
DD
(1)
NC
NC
V
DD
(1)
NC
A
16
A
17
NC
V
DD
(1)
A
10
V
SS/ZZ(3)
,
N
C
N
C
N
C
N
C
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
5
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5296 tbl 07
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5296 tbl 07a
119 BGA Capacitance
(1)
(T
A
= +25 C, f = 1.0MHz)
165 fBGA Capacitance
(1)
(T
A
= +25 C, f = 1.0MHz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
TBD
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
TBD
pF
5296 tbl 07b
6.42
IDT71V3548, 256K x 18, 3.3V Synchronous SRAMS with
ZBT
TM
TM
TM
TM
TM
Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges
5
1
2
3
4
5
6
7
A
V
DDQ
A
6
A
4
NC(2)
A
8
A
16
V
DDQ
B
NC
CE2
A
3
ADV/
LD
A
9
CE
2
NC
C
A
7
A
2
V
DD
A
13
A
17
NC
D
I/O
8
NC
V
SS
NC
V
SS
I/O
7
NC
E
NC
I/O
9
V
SS
V
SS
NC
I/O
6
F
V
DDQ
NC
V
SS
OE
V
SS
I/O
5
V
DDQ
G
NC
I/O
10
BW
2
NC
I/O
4
H
I/O
11
NC
V
SS
R/
W
V
SS
I/O
3
NC
J
V
DDQ
V
DD
V
DD
V
DD
V
DDQ
K
NC
I/O
12
V
SS
CLK
V
SS
NC
I/O
2
L
I/O
13
NC
NC
BW
1
I/O
1
NC
M
V
DDQ
I/O
14
V
SS
CEN
V
SS
NC
V
DDQ
N
I/O
15
NC
V
SS
A
1
V
SS
I/O
0
NC
P
NC
I/O
P2
V
SS
A
0
V
SS
NC
I/O
P1
R
NC
A
5
LBO
V
DD
A
12
T
NC
A
10
A
15
NC
A
14
A
11
NC/ZZ(5)
U
V
DDQ
V
DDQ
5296 drw 13
NC
DD(1)
V
NC
V
SS
V
SS
CE
1
NC(2)
V
DD(1)
V
DD(1)
,
NC/TMS
(3)
NC/
TRST
(3,4)
NC/TDO
(3)
NC/TCK
(3)
NC/TDI
(3)
Pin Configuration - 256K x 18, 119 BGA
Top View
NOTES:
1. J3, J5, and R5 do not have to be directly connected to V
DD
as long as the input voltage is
V
IH
.
2. G4 and A4 are reserved for future 8M and 16M respectively.
3. These pins are NC for the "S" version and the JTAG signal listed for the "SA" version.
4.
TRST is offered as an optional JTAG reset if required in the application. If not needed, can be left floating and will internally be pulled to V
DD.
5. Pin T7 supports ZZ (sleep mode) on the latest die revision.