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Электронный компонент: 71V3577

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APRIL 2003
DSC-5280/06
1
2003 Integrated Device Technology, Inc.
Features
x
128K x 36, 256K x 18 memory configurations
x
x
x
x
x
Supports fast access times:
Commercial:
7.5ns up to 117MHz clock frequency
Commercial and Industrial:
8.0ns up to 100MHz clock frequency
8.5ns up to 87MHz clock frequency
x
LBO input selects interleaved or linear burst mode
x
x
x
x
x
Self-timed write cycle with global write control (
GW), byte write
enable (
BWE), and byte writes (BWx)
x
x
x
x
x
3.3V core power supply
x
x
x
x
x
Power down controlled by ZZ input
x
x
x
x
x
3.3V I/O
x
x
x
x
x
Packaged in a JEDEC Standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch ball
grid array
Pin Description Summary
NOTE:
1.
BW
3
and
BW
4
are not applicable for the IDT71V3579.
Description
The IDT71V3577/79 are high-speed SRAMs organized as
128K x 36/256K x 18. The IDT71V3577/79 SRAMs contain write, data,
address and control registers. There are no registers in the data output
path (flow-through architecture). Internal logic allows the SRAM to gen-
erate a self-timed write based upon a decision which can be left until the
end of the write cycle.
The burst mode feature offers the highest level of performance to the
system designer, as the IDT71V3577/79 can provide four cycles of data
for a single address presented to the SRAM. An internal burst address
counter accepts the first cycle address from the processor, initiating the
access sequence. The first cycle of output data will flow-through from the
array after a clock-to-data access time delay from the rising clock edge of
the same cycle. If burst mode operation is selected (
ADV=LOW), the
subsequent three cycles of output data will be available to the user on the
next three rising clock edges. The order of these three addresses are
defined by the internal burst counter and the
LBO input pin.
The IDT71V3577/79 SRAMs utilize IDT's latest high-performance
CMOS process and are packaged in a JEDEC standard 14mm x 20mm
100-pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array
(BGA) and a 165 fine pitch ball grid array (fBGA).
A
0
-A
17
Address Inputs
Input
Synchronous
CE
Chip Enable
Input
Synchronous
CS
0
,
CS
1
Chip Selects
Input
Synchronous
OE
Output Enable
Input
Asynchronous
GW
Global Write Enable
Input
Synchronous
BWE
Byte Write Enable
Input
Synchronous
BW
1
,
BW
2
,
BW
3
,
BW
4
(1)
Individual Byte Write Selects
Input
Synchronous
CLK
Clock
Input
N/A
ADV
Burst Address Advance
Input
Synchronous
ADSC
Address Status (Cache Controller)
Input
Synchronous
ADSP
Address Status (Processor)
Input
Synchronous
LBO
Linear / Interleaved Burst Order
Input
DC
ZZ
Sleep Mode
Input
Asynchronous
I/O
0
-I/O
31
, I/O
P1
-I/O
P4
Data Input / Output
I/O
Synchronous
V
DD
, V
DDQ
Core Power, I/O Power
Supply
N/A
V
SS
Ground
Supply
N/A
5280 tbl 01
128K X 36, 256K X 18
3.3V Synchronous SRAMs
3.3V I/O, Flow-Through Outputs
Burst Counter, Single Cycle Deselect
IDT71V3577
IDT71V3579
6.42
2
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
Pin Definitions
(1)
NOTE:
1. All synchronous inputs must meet specified setup and hold times with respect to CLK.
Symbol
Pin Function
I/O
Active
Description
A
0
-A
17
Address Inputs
I
N/A
Synchronous Address inputs. The address register is triggered by a combi-nation of the rising
edge of CLK and
ADSC Low or ADSP Low and CE Low.
ADSC
Address Status
(Cache Controller)
I
LOW
Synchronous Address Status from Cache Controller.
ADSC is an active LOW input that is
used to load the address registers with new addresses.
ADSP
Address Status
(Processor)
I
LOW
Synchronous Address Status from Processor.
ADSP is an active LOW input that is used to
load the address registers with new addresses.
ADSP is gated by CE.
ADV
Burst Address
Advance
I
LOW
Synchronous Address Advance.
ADV is an active LOW input that is used to advance the
internal burst counter, controlling burst access after the initial address is loaded. When the
input is HIGH the burst counter is not incremented; that is, there is no address advance.
BWE
Byte Write Enable
I
LOW
Synchronous byte write enable gates the byte write inputs
BW
1
-
BW
4
. If
BWE is LOW at the
rising edge of CLK then
BWx inputs are passed to the next stage in the circuit. If BWE is
HIGH then the byte write inputs are blocked and only
GW can initiate a write cycle.
BW
1
-
BW
4
Individual Byte
Write Enables
I
LOW
Synchronous byte write enables.
BW
1
controls I/O
0-7
, I/O
P1
,
BW
2
controls I/O
8-15
, I/O
P2
, etc.
Any active byte write causes all outputs to be disabled.
CE
Chip Enable
I
LOW
Synchronous chip enable.
CE is used with CS
0
and
CS
1
to enable the IDT71V3577/79.
CE
also gates
ADSP.
CLK
Clock
I
N/A
This is the clock input. All timing references for the device are made with respect to this
input.
CS
0
Chip Select 0
I
HIGH
Synchronous active HIGH chip select. CS
0
is used with
CE and CS
1
to enable the chip.
CS
1
Chip Select 1
I
LOW
Synchronous active LOW chip select.
CS
1
is used with
CE and CS
0
to enable the chip.
GW
Global Write
Enable
I
LOW
Synchronous global write enable. This input will write all four 9-bit data bytes when LOW on
the rising edge of CLK.
GW supersedes individual byte write enables.
I/O
0
-I/O
31
I/O
P1
-I/O
P4
Data Input/Output
I/O
N/A
Synchronous data input/output (I/O) pins. The data input path is registered, triggered by the
rising edge of CLK. The data output path is flow-through (no output register).
LBO
Linear Burst Order
I
LOW
Asynchronous burst order selection input. When
LBO is HIGH, the inter-leaved burst
sequence is selected. When
LBO is LOW the Linear burst sequence is selected. LBO is a
static input and must not change state while the device is operating.
OE
Output Enable
I
LOW
Asynchronous output enable. When
OE is LOW the data output drivers are enabled on the
I/O pins if the chip is also selected. When OE is HIGH the I/O pins are in a high-impedance
state.
V
DD
Power Supply
N/A
N/A
3.3V core power supply.
V
DDQ
Power Supply
N/A
N/A
3.3V I/O Supply.
V
SS
Ground
N/A
N/A
Ground.
NC
No Connect
N/A
N/A
NC pins are not electrically connected to the device.
ZZ
Sleep Mode
1
HIGH
Asynchronous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
IDT71V3577/79 to its lowest power consumption level. Data retention is guaranteed in
Sleep Mode.
5280 tbl 02
6.42
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
3
Functional Block Diagram
A
0 -
A
16/17
ADDRESS
REGISTER
CLR
A1*
A0*
17/18
2
17/18
A
2 -
A
17
128K x 36/
256K x 18-
BIT
MEMORY
ARRAY
INTERNAL
ADDRESS
A
0
,A
1
BW
4
BW
3
BW
2
BW
1
Byte 1
Write Register
36/18
36/18
ADSP
ADV
CLK
ADSC
CS
0
CS
1
Byte 1
Write Driver
Byte 2
Write Driver
Byte 3
Write Driver
Byte 4
Write Driver
Byte 2
Write Register
Byte 3
Write Register
Byte 4
Write Register
9
9
9
9
GW
CE
BWE
LBO
I/O
0
- I/O
31
I/O
P1
- I/O
P4
OE
DATA INPUT
REGISTER
36/18
OUTPUT
BUFFER
D
Q
Enable
Register
OE
Burst
Sequence
CEN
CLK EN
CLK EN
Q1
Q0
2
Burst
Logic
Binary
Counter
5280 drw 01
ZZ
Powerdown
,
6.42
4
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
100 Pin TQFP Capacitance
(T
A
= +25 C, f = 1.0mhz)
Recommended Operating
Temperature Supply Voltage
Absolute Maximum Ratings
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may
cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.
2. V
DD
terminals only.
3. V
DDQ
terminals only.
4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supplies have
ramped up. Power supply sequencing is not necessary; however, the voltage
on any input or I/O pin cannot exceed V
DDQ
during power supply ramp up.
7. T
A
is the "instant on" case temperature.
Recommended DC Operating
Conditions
NOTES:
1. V
IH
(max) = V
DDQ
+ 1.0V for pulse width less than t
CYC/2
, once per cycle.
2. V
IL
(min) = -1.0V for pulse width less than t
CYC/2
, once per cycle.
NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.
Symbol
Rating
Commercial &
Industrial Values
Unit
V
TERM
(2)
Terminal Voltage with
Respect to GND
-0.5 to +4.6
V
V
TERM
(3,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
V
V
TERM
(4,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DD
+0.5
V
V
TERM
(5,6)
Terminal Voltage with
Respect to GND
-0.5 to V
DDQ
+0.5
V
T
A
(7)
Commercial
Operating Temperature
-0 to +70
o
C
Industrial
Operating Temperature
-40 to +85
o
C
T
BIAS
Temperature
Under Bias
-55 to +125
o
C
T
STG
Storage
Temperature
-55 to +125
o
C
P
T
Power Dissipation
2.0
W
I
OUT
DC Output Current
50
mA
5280 tbl 03
Grade
Temperature
(1)
V
SS
V
DD
V
DDQ
Commercial
0C to +70C
0V
3.3V5%
3.3V5%
Industrial
-40C to +85C
0V
3.3V5%
3.3V5%
5280 tbl 04
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
DD
Core Supply Voltage
3.135
3.3
3.465
V
V
DDQ
I/O Supply Voltage
3.135
3.3
3.465
V
V
SS
Supply Voltage
0
0
0
V
V
IH
Input High Voltage - Inputs
2.0
____
V
DD
+0.3
V
V
IH
Input High Voltage - I/O
2.0
____
V
DDQ
+0.3
(1)
V
V
IL
Input Low Voltage
-0.3
(2)
____
0.8
V
5280 tbl 06
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
5
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5280 tbl 07
NOTES:
1. T
A
is the "instant on" case temperature.
119 BGA Capacitance
(T
A
= +25 C, f = 1.0mhz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5280 tbl 07a
165 fBGA Capacitance
(T
A
= +25 C, f = 1.0mhz)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
Input Capacitance
V
IN
= 3dV
7
pF
C
I/O
I/O Capacitance
V
OUT
= 3dV
7
pF
5280 tbl 07b
6.42
IDT71V3577, IDT71V3579, 128K x 36, 256K x 18, 3.3V Synchronous SRAMs with
3.3V I/O, Flow-Through Outputs, Burst Counter, Single Cycle Deselect Commercial and Industrial Temperature Ranges
5
Pin Configuration 128K x 36
100 TQFP
Top View
NOTES:
1. Pin 14 does not have to be directly connected to V
SS
as long as the input voltage is < V
IL
.
2. Pins 38 and 39 can be either NC or connected to V
SS.
3. Pin 64 can be left unconnected and the device will always remain in active mode.
100 99 98 97 96 95 94 93 92 91 90
87 86 85 84 83 82 81
89 88
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
A
6
A
7
C
E
C
S
0
B
W
4
B
W
3
B
W
2
B
W
1
C
S
1
V
D
D
V
S
S
C
LK
G
W
B
W
E
O
E
A
D
S
C
A
D
S
P
A
D
V
A
8
A
9
NC
31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A
16
N
C
N
C
LB
O
A
14
A
13
A
12
A
11
A
10
V
D
D
V
S
S
A
0
A
1
A
2
A
3
A
4
A
5
I/O
P4
I/O
31
I/O
30
V
DDQ
V
SS
I/O
29
I/O
28
I/O
27
I/O
26
V
SS
V
DDQ
I/O
25
I/O
24
V
SS
(1)
V
DD
I/O
23
I/O
22
V
DDQ
V
SS
I/O
21
I/O
20
I/O
19
I/O
18
V
SS
V
DDQ
I/O
17
I/O
16
I/O
P3
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
I/O
P2
I/O
14
V
DDQ
V
SS
I/O
13
I/O
12
I/O
11
I/O
10
V
SS
V
DDQ
I/O
9
I/O
8
V
SS
NC
V
DD
ZZ
(3)
I/O
7
I/O
6
V
DDQ
V
SS
I/O
5
I/O
4
I/O
3
I/O
2
V
SS
V
DDQ
I/O
1
I/O
0
I/O
P1
V
SS
I/O
15
A
15
5280 drw 02a
N
C
(2
)
N
C
(2
)
,