DECEMBER 2002

DSC-5304/05

Pin Description Summary

Description

The IDT71V65603/5803 are 3.3V high-speed 9,437,184-bit

(9 Megabit) synchronous SRAMS. They are designed to eliminate dead bus
cycles when turning the bus around between reads and writes, or writes and
reads. Thus, they have been given the name ZBT

, or Zero Bus Turnaround.

Features

256K x 36, 512K x 18 memory configurations

Supports high performance system speed - 150MHz
(3.8ns Clock-to-Data Access)

ZBT

Feature - No dead cycles between write and read cycles

Internally synchronized output buffer enable eliminates the
need to control

Single R/

W (READ/WRITE) control pin

Positive clock-edge triggered address, data, and control
signal registers for fully pipelined applications

4-word burst capability (interleaved or linear)

Individual byte write (

) control (May tie active)

Three chip enables for simple depth expansion

3.3V power supply (±5%)

3.3V I/O Supply (V

DDQ

)

Power down controlled by ZZ input

Packaged in a JEDEC standard 100-pin plastic thin quad
flatpack (TQFP), 119 ball grid array (BGA) and 165 fine pitch
ball grid array(fBGA).

-A

Address Inputs

Input

Synchronous

, CE

Chip Enables

Input

Synchronous

Output Enable

Input

Asynchronous

Read/Write Signal

Input

Synchronous

CEN

Clock Enable

Input

Synchronous

Individual Byte Write Selects

Input

Synchronous

CLK

Clock

Input

N/A

ADV/

Advance burst address / Load new address

Input

Synchronous

LBO

Linear / Interleaved Burst Order

Input

Static

Sleep Mode

Input

Asynchronous

I/O

-I/O

, I/O

-I/O

Data Input / Output

I/O

Synchronous

, V

DDQ

Core Power, I/O Power

Supply

Static

Ground

Supply

Static

5304 tbl 01

256K x 36, 512K x 18
3.3V Synchronous ZBTTM SRAMs
ZBTTM Feature
3.3V I/O, Burst Counter
Pipelined Outputs

IDT71V65603
IDT71V65803

Address and control signals are applied to the SRAM during one clock

cycle, and two cycles later the associated data cycle occurs, be it read or write.

The IDT71V65603/5803 contain data I/O, address and control signal

registers. Output enable is the only asynchronous signal and can be used
to disable the outputs at any given time.

A Clock Enable (

CEN) pin allows operation of the IDT71V65603/5803 to

be suspended as long as necessary. All synchronous inputs are ignored when
(

CEN) is high and the internal device registers will hold their previous values.

There are three chip enable pins (

CE1, CE2, CE2) that allow the user

to deselect the device when desired. If any one of these three are not asserted
when ADV/

LD is low, no new memory operation can be initiated. However,

any pending data transfers (reads or writes) will be completed. The data bus
will tri-state two cycles after chip is deselected or a write is initiated.

The IDT71V65603/5803 have an on-chip burst counter. In the burst

mode, the IDT71V65603/5803 can provide four cycles of data for a single
address presented to the SRAM. The order of the burst sequence is
defined by the

LBO input pin. The LBO pin selects between linear and

interleaved burst sequence. The ADV/

LD signal is used to load a new

external address (ADV/

LD = LOW) or increment the internal burst counter

(ADV/

LD = HIGH).

The IDT71V65603/5803 SRAM utilize IDT's latest high-performance

CMOS process, and are packaged in a JEDEC Standard 14mm x 20mm 100-
pin thin plastic quad flatpack (TQFP) as well as a 119 ball grid array (BGA) and
165 fine pitch ball grid array (fBGA) .

ZBT and Zero Bus Turnaround are trademarks of Integrated Device Technology, Inc. and the architecture is supported by Micron Technology and Motorola, Inc.

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Pin Definitions

(1)

NOTE:

1. All synchronous inputs must meet specified setup and hold times with respect to CLK.

Symbol

Pin Function

I/O

Active

Description

-A

Address Inputs

N/A

Synchronous Address inputs. The address register is trig gered by a combination of the
rising edge of CLK, ADV/

LD low, CEN low, and true chip enables.

ADV/

Advance / Load

N/A

ADV/

LD is a synchronous input that is used to load the internal registers with new address

and control when it is sampled low at the rising edge of clock with the chip selected. When

ADV/

LD is low with the chip deselected, any burst in progress is terminated. When ADV/ LD

is sampled hig h then the internal burst counter is advanced for any burst that was in
progress. The external addresses are ignored when ADV/

LD is sampled high.

Read / Write

N/A

W signal is a synchronous input that identifies whether the current load cycle initiated is a

Read or Write access to the memory array. The data bus activity for the current cycle takes
place two clock cycles later.

CEN

Clock Enable

LOW

Synchronous Clock Enable Input. When

CEN is sampled high, all other synchronous

inputs, including clock are ignored and outputs re main unchanged. The effect of

CEN

sampled high on the device outp uts is as if the low to hig h clock transition did not occur.
For normal operation,

CEN must be sampled low at rising edge of clock.

Individual Byte

Write Enables

LOW

Synchro nous byte write enables. Each 9-bit byte has its own active low byte write enable.
On load write cycles (When R/

W and ADV/LD are sampled low) the appropriate byte write

signal (

) must be valid. The byte write signal must also be valid on each cycle of

a burst write. Byte Write signals are ignored when R/

W is sampled high. The appropriate

byte(s) of data are written into the device two cycles later.

can all be tied low if

always doing write to the entire 36-bit word.

Chip Enables

LOW

Synchronous active low chip enable.

and

are used with CE

to enable the

IDT71V65603/5803. (

sampled high or CE

sampled low) and ADV/

LD low at the

rising edge of clock, initiates a deselect cycle. The ZBT

has a two cycle deselect, i.e.,

the data bus will tri-state two clock cycles after deselect is initiated.

Chip Enable

HIGH

Synchrono us active high chip enable. CE

is used with

and

to enable the chip.

has inverted po larity but otherwise identical to

and

CLK

Clock

N/A

This is the clock input to the IDT71V65603/5803. Except for

OE, all timing references for the

device are made with respect to the rising edge of CLK.

I/O

-I/O

I/O

-I/O

Data Input/Output

I/O

N/A

Synchro nous data input/output (I/O) pins. Both the data input path and data output path are
registered and triggered by the rising edge of CLK.

LBO

Linear Burst Order

LOW

Burst order selection input. When

LBO is high the Interleaved burst sequence is selected.

When

LBO is low the Linear burst sequence is selected. LBO is a static input and it must

not change during device operation.

Output Enable

LOW

Asynchronous output enable.

OE must be low to read data from the 71V65603/5803. When

OE is high the I/O pins are in a high-impedance state. OE does not need to be actively

controlled for read and write cycles. In normal operation,

OE can be tied low.

Sleep Mode

N/A

Asynchro nous sleep mode input. ZZ HIGH will gate the CLK internally and power down the
71V65603/5803 to its lowest p ower consumption level. Data retention is guaranteed in

Sleep Mode.

Power Supply

N/A

3.3V core power supply.

DDQ

Power Supply

N/A

3.3V I/O Supply.

Ground

N/A

Ground.

5304tbl 02

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Recommended DC Operating

Conditions

NOTES:
1. V

(min.) = 1.0V for pulse width less than t

CYC

/2, once per cycle.

Functional Block Diagram

Symbol

Parameter

Min.

Typ.

Max.

Unit

Core Supply Voltage

3.135

3.3

3.465

DDQ

I/O Supply Voltage

3.135

3.3

3.465

Supply Voltage

Input High Voltage - Inputs

2.0

____

+0.3

Input High Voltage - I/O

2.0

____

DDQ

+0.3

Input Low Voltage

-0.3

(1)

____

0.8

5304 tbl 04

Clk

Address A [0:18]

Control Logic

Address

Control

i
s

t
e

5304 drw 01

Clock

Data I/O [0:15],

I/O P[1:2]

Output Register

Mux

Sel

Gate

1, CE2,

CEN

ADV/

LBO

512x18 BIT

MEMORY ARRAY

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

100 99 98 97 96 95 94 93 92 91 90

87 86 85 84 83 82 81

89 88

)

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

)

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

5304 drw 02

(1)

I/O

(1)

I/O

(1)

I/O

Recommended Operating

Temperature and Supply Voltage

Pin Configuration - 256K x 36

NOTES:

1. Pins 14, 16 and 66 do not have to be connected directly to VDD as long as the input voltage is

VIH.

2. Pin 84 is reserved for a future 16M.
3.

DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective JTAG pins: TMS, TDI, TDO and TCK. The

current die revision allows these pins to be left unconnected, tied LOW (V

), or tied HIGH (V

Top View

100 TQFP

Grade

Temperature

(1)

DDQ

Commercial

0° C to +70° C

3.3V±5%

Industrial

-40°C to +85°C

3.3V±5%

5304 tbl 05

NOTES:

is the "instant on" case temperature.

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Absolute Maximum Ratings

(1)

Pin Configuration - 512K x 18

119 BGA Capacitance

(1)

= +25° C, f = 1.0MHz)

Top View

100 TQFP

NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may

cause permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated
in the operational sections of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect reliability.

2. V

terminals only.

3. V

DDQ

terminals only.

4. Input terminals only.
5. I/O terminals only.
6. This is a steady-state DC parameter that applies after the power supply has

reached its nominal operating value. Power sequencing is not necessary;
however, the voltage on any input or I/O pin cannot exceed V

DDQ

during power

supply ramp up.

7. T

is the "instant on" case temperature.

NOTE:
1. This parameter is guaranteed by device characterization, but not production tested.

Symbol

Rating

Commercial &

Industrial

Unit

TERM

(2)

Terminal Voltage with

Respect to GND

-0.5 to +4.6

TERM

(3,6)

Terminal Voltage with

Respect to GND

-0.5 to V

TERM

(4,6)

Terminal Voltage with

Respect to GND

-0.5 to V

+0.5

TERM

(5,6)

Terminal Voltage with

Respect to GND

-0.5 to V

DDQ

+0.5

(7)

Commercial
Operating Temperature

-0 to +70

Industrial
Operating Temperature

-40 to +85

BIAS

Temperature

Under Bias

-55 to +125

STG

Storage

Temperature

-55 to +125

Power Dissipation

2.0

OUT

DC Output Current

5304 tbl 06

Symbol

Parameter

(1)

Conditions

Max.

Unit

Input Capacitance

= 3dV

I/O

I/O Capacitance

OUT

= 3dV

5304 tbl 07

100 99 98 97 96 95 94 93 92 91 90

87 86 85 84 83 82 81

89 88

)

31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50

)

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

NC
V

DDQ

NC
I/O

I/O

DDQ

I/O

DDQ

I/O

NC
NC
V

DDQ

NC
NC

5304 drw 02a

(1)

NOTES:
1. Pins 14, 16 and 66 do not have to be connected directly to V

as long as

the input voltage is

2. Pin 84 is reserved for a future 16M.
3. DNU=Do not use. Pins 38, 39, 42 and 43 are reserved for respective

JTAG pins: TMS, TDI, TDO and TCK. The current die revision allows
these pins to be left unconnected, tied LOW (V

), or tied HIGH (V

Symbol

Parameter

(1)

Conditions

Max.

Unit

Input Capacitance

= 3dV

I/O

I/O Capacitance

OUT

= 3dV

5304 tbl 07a

100 TQFP Capacitance

(1)

= +25° C, f = 1.0MHz)

Symbol

Parameter

(1)

Conditions

Max.

Unit

Input Capacitance

= 3dV

TBD

I/O

I/O Capacitance

OUT

= 3dV

TBD

5304 tbl 07b

165 fBGA Capacitance

(1)

= +25° C, f = 1.0MHz)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:
1. J3, J5, and R5 do not have to be directly connected to V

as long as the input voltage is

2. A4 is reserved for future 16M.
3. DNU = Do not use. Pin U2, U3, U4, U5 and U6 are reserved for respective JTAG pins: TMS, TDI, TCK, TDO and

TRST. The current die revision allows

these pins to be left unconnected, tied LOW (V

), or tied HIGH (V

Pin Configuration - 256K X 36, 119 BGA

Top View

Pin Configuration - 512K X 18, 119 BGA

Top View

DDQ

ADV/

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

CLK

I/O

DDQ

I/O

CEN

I/O

DDQ

I/O

LBO

DDQ

DNU

(3)

DNU

(3)

DNU

(3)

DDQ

5304 drw 13A

DD(1)

(2)

A17

DD(1)

DNU

(3)

DNU

(3)

DDQ

NC(2)

DDQ

CE2

ADV/

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

CLK

I/O

DDQ

I/O

CEN

DDQ

I/O

LBO

DDQ

DNU

(3)

DNU

(3)

DNU

(3)

DNU

(3)

DDQ

5304 drw 13B

DD(1)

DNU

(3)

A18

DD(1)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:
1. H1, H2, and N7 do not have to be directly connected to V

as long as the input voltage is

2. B9, B11, A1, R2 and P2 is reserved for future 18M, 36M, 72M, 144M and 288M, respectively.
3. DNU=Do not use. Pins P5, R5, P7 and R7 are reserved for respective JTAG pins: TDI, TMS, TDO and TCK on future revisions. The current die revision

allows these pins to be left unconnected, tied LOW (V

), or tied HIGH (V

Pin Configuration - 256K X 36, 165 fBGA

Pin Configuration - 512K X 18, 165 fBGA

(2)

CEN

ADV

/LD

CLK

(2)

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

DNU

(3)

(1)

DDQ

I/O

(2)

DNU

(3)

DNU

(3)

LBO

(2)

DNU

(3)

DNU

(3)

5304 tbl 25a

(2)

CEN

ADV

/LD

CLK

(2)

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

(1)

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

I/O

DDQ

DNU

(3)

(1)

DDQ

(2)

DNU

(3)

DNU

(3)

LBO

(2)

DNU

(3)

DNU

(3)

5304 tbl25b

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Synchronous Truth Table

(1)

Partial Truth Table for Writes

(1)

NOTES:
1. L = V

, H = V

, X = Don't Care.

2. When ADV/

LD signal is sampled high, the internal burst counter is incremented. The R/W signal is ignored when the counter is advanced. Therefore the nature of

the burst cycle (Read or Write) is determined by the status of the R/

W signal when the first address is loaded at the beginning of the burst cycle.

3. Deselect cycle is initiated when either (

, or

is sampled high or CE

is sampled low) and ADV/

LD is sampled low at rising edge of clock. The data bus will

tri-state two cycles after deselect is initiated.

4. When

CEN is sampled high at the rising edge of clock, that clock edge is blocked from propogating through the part. The state of all the internal registers and the I/

Os remains unchanged.

5. To select the chip requires

= L,

= L, CE

= H on these chip enables. Chip is deselected if any one of the chip enables is false.

6. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.
7. Q - Data read from the device, D - data written to the device.

NOTES:
1. L = V

, H = V

, X = Don't Care.

2. Multiple bytes may be selected during the same cycle.
3. N/A for X18 configuration.

CEN

Chip

(5)

Enable

ADV/

BWx

ADDRESS

USED

PREVIOUS CYCLE

CURRENT CYCLE

I/O

(2 cycles later)

Select

Valid

External

LOAD WRITE

(7)

Select

External

LOAD READ

(7)

Valid

Internal

LOAD WRITE /

BURST WRITE

(Advance burst counter)

(2)

(7)

Internal

LOAD READ /

BURST READ

(Advance burst counter)

(2)

(7)

Deselect

DESELECT or STOP

(3)

HiZ

DESELECT / NOOP

NOOP

HiZ

SUSPEND

(4)

Previous Value

5304 tbl 08

OPERATION

(3)

READ

WRITE ALL BYTES

WRITE BYTE 1 (I/O[0:7], I/O

)

(2)

WRITE BYTE 2 (I/O[8:15], I/O

)

(2)

WRITE BYTE 3 (I/O[16:23], I/O

)

(2,3)

WRITE BYTE 4 (I/O[24:31], I/O

)

(2,3)

NO WRITE

5304 tbl 09

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Linear Burst Sequence Table (LBO=V

)

Interleaved Burst Sequence Table (LBO=V

)

Functional Timing Diagram

(1)

NOTES:
1. This assumes

CEN, CE

, CE

are all true.

2. All Address, Control and Data_In are only required to meet set-up and hold time with respect to the rising edge of clock. Data_Out is valid after a clock-to-data

delay from the rising edge of clock.

NOTE:
1. Upon completion of the Burst sequence the counter wraps around to its initial state and continues counting.

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address

(1)

5304 tbl 10

Sequence 1

Sequence 2

Sequence 3

Sequence 4

First Address

Second Address

Third Address

Fourth Address

(1)

5304 tbl 11

n+29

A29

C29

D/Q27

ADDRESS

(2)

(A0 - A17)

CONTROL

(2)

(R/

, ADV/

DATA

(2)

I/O [0:31], I/O P[1:4]

CYCLE

CLOCK

n+30

A30

C30

D/Q28

n+31

A31

C31

D/Q29

n+32

A32

C32

D/Q30

n+33

A33

C33

D/Q31

n+34

A34

C34

D/Q32

n+35

A35

C35

D/Q33

n+36

A36

C36

D/Q34

n+37

A37

C37

D/Q35

5304 drw 03

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:
1. H = High; L = Low; X = Don't Care; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

Read Operation

(1)

Device Operation - Showing Mixed Load, Burst,

Deselect and NOOP Cycles

(2)

NOTES:
1.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

2. H = High; L = Low; X = Don't Care; Z = High Impedance.

Cycle

Address

ADV/

(1)

CEN

BWx

I/O

Comments

Load read

n+1

Burst read

n+2

Load read

n+3

0+1

Deselect or STOP

n+4

NOOP

n+5

Load read

n+6

Burst read

n+7

Deselect or STOP

n+8

2+1

Load write

n+9

Burst write

n+10

Load write

n+11

3+1

Deselect or STOP

n+12

NOOP

n+13

Load write

n+14

Load read

n+15

Load write

n+16

Burst write

n+17

Load read

n+18

7+1

Burst read

n+19

Load write

5304tbl 12

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid

n+2

Contents of Address A

Read Out

5304 tbl 13

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Burst Write Operation

(1)

Burst Read Operation

(1)

Write Operation

(1)

NOTES:
1. H = High; L = Low; X = Don't Care; Z = High Impedance..
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

NOTES:
1. H = High; L = Low; X = Don't Care; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

NOTES:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid, Advance Counter

n+2

Address A

Read Out, Inc. Count

n+3

0+1

Address A

0+1

Read Out, Inc. Count

n+4

0+2

Address A

0+2

Read Out, Inc. Count

n+5

0+3

Address A

0+3

Read Out, Load A

n+6

Address A

Read Out, Inc. Count

n+7

Address A

Read Out, Inc. Count

n+8

1+1

Address A

1+1

Read Out, Load A

5304 tbl 14

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid

n+2

Write to Address A

5304 tbl 15

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock Setup Valid, Inc. Count

n+2

Address A

Write, Inc. Count

n+3

0+1

Address A

0+1

Write, Inc. Count

n+4

0+2

Address A

0+2

Write, Inc. Count

n+5

0+3

Address A

0+3

Write, Load A

n+6

Address A

Write, Inc. Count

n+7

Address A

Write, Inc. Count

n+8

1+1

Address A

1+1

Write, Load A

5304 tbl 16

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Read Operation with Clock Enable Used

(1)

Write Operation with Clock Enable Used

(1)

NOTES:
1. H = High; L = Low; X = Don't Care; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

NOTES:
1. H = High; L = Low; X = Don't Care; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

Comments

Address and Control meet setup

n+1

Clock n+1 Ignored

n+2

Clock Valid

n+3

Clock Ignored, Data Q

is on the bus.

n+4

Clock Ignored, Data Q

is on the bus.

n+5

Address A

Read out (bus trans.)

n+6

Address A

Read out (bus trans.)

n+7

Ad dress A2 Read out (bus trans.)

5304 tbl 17

Cycle

Address

ADV

/LD

(2)

CEN

BWx

I/O

Comments

Address and Control meet setup.

n+1

Clock n+1 Ignored.

n+2

Clock Valid.

n+3

Clock Ignored.

n+4

Clock Ignored.

n+5

Write Data D

n+6

Write Data D

n+7

Write Data D

5304 tbl 18

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

3. Device Outputs are ensured to be in High-Z after the first rising edge of clock upon power-up.

Read Operation with Chip Enable Used

(1)

Write Operation with Chip Enable Used

(1)

NOTES:
1. H = High; L = Low; X = Don't Care; ? = Don't Know; Z = High Impedance.
2.

CE = L is defined as CE

= L,

= L and CE

= H.

CE = H is defined as CE

= H,

= H or CE

= L.

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

(3)

Comments

Deselected.

n+1

Deselected.

n+2

Address and Control meet setup

n+3

Deselected or STOP.

n+4

Address A

Read out. Load A

n+5

Deselected or STOP.

n+6

Address A

Read out. Deselected.

n+7

Address and control meet setup.

n+8

Deselected or STOP.

n+9

Address A

Read out. Deselected.

5304 tbl 19

Cycle

Address

ADV/

(2)

CEN

BWx

I/O

(3)

Comments

Deselected.

n+1

Deselected.

n+2

Address and Control meet setup

n+3

Deselected or STOP.

n+4

Address D

Write in. Load A

n+5

Deselected or STOP.

n+6

Address D

Write in. Deselected.

n+7

Address and control meet setup.

n+8

Deselected or STOP.

n+9

Address D

Write in. Deselected.

5304 tbl 20

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

20 30 50

100

200

tCD

(Typical, ns)

Capacitance (pF)

5304 drw 05

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

= 3.3V +/-5%)

Figure 2. Lumped Capacitive Load, Typical Derating

AC Test Conditions

DDQ

= 3.3V)

DC Electrical Characteristics Over the Operating

Temperature and Supply Voltage Range

(1)

= 3.3V +/-5%)

Figure 1. AC Test Load

AC Test Load

NOTE:
1. The

LBO pin will be internally pulled to V

if it is not actively driven in the application and the ZZ pin will be internally pulled to Vss if not actively driven.

NOTES:
1. All values are maximum guaranteed values.
2. At f = f

MAX,

inputs are cycling at the maximum frequency of read cycles of 1/t

CYC

; f=0 means no input lines are changing.

3. For I/Os V

= V

DDQ

0.2V, V

= 0.2V. For other inputs V

= V

0.2V, V

= 0.2V.

Symbol

Parameter

Test Conditions

Min.

Max.

Unit

Input Leakage Current

= Max., V

= 0V to V

___

µ A

LBO Input Leakage Current

(1)

= Max., V

= 0V to V

___

µ A

Output Leakage Current

OUT

= 0V to V

DDQ

, Device Deselected

___

µ A

Output Low Voltage

= +8mA, V

= Min.

___

0.4

Output High Voltage

= -8mA, V

= Min.

2.4

___

5304 tbl 21

Symbol

Parameter

Test Conditions

150MHz

133MHz

100MHz

Unit

Com'l

Ind

Com'l

Ind

Com'l

Ind

Operating Power
Supply Current

Device Selected, Outputs Open,

ADV/

LD = X, V

= Max.,

> V

or < V

, f = f

MAX

(2)

325

345

300

320

250

270

SB1

CMOS Standby Power
Supply Current

Device Deselected, Outputs Open,

= Max., V

> V

or < V

f = 0

(2,3)

SB2

Clock Running Power
Supply Current

Device Deselected, Outputs Open,

= Max., V

> V

or < V

f = f

MAX

(2.3)

120

140

110

130

100

120

SB3

Idle Power
Supply Current

Device Selected, Outputs Open,

CEN > V

, V

= Max.,

> V

or < V

, f = f

MAX

(2,3)

Full Sleep Mode
Supply Current

Device Selected, Outputs Open

CEN

, V

= Max., ZZ

, f = fMax

(2, 3)

5304 tbl 22

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Timing Reference Levels

AC Test Load

0 to

2ns

1.5V

See Figure 1

5304 tbl 23

DDQ

I/O

= 50

5304 drw 04

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

AC Electrical Characteristics

= 3.3V +/-5%, Commercial and Industrial Temperature Ranges)

NOTES:
1. t

= 1/t

CYC

2. Measured as HIGH above 0.6V

DDQ

and LOW below 0.4V

DDQ

3. Transition is measured ±200mV from steady-state.
4. These parameters are guaranteed with the AC load (Figure 1) by device characterization. They are not production tested.
5. To avoid bus contention, the output buffers are designed such that t

CHZ

(device turn-off) is about 1ns faster than

CLZ

(device turn-on) at a given temperature

and voltage.

The specs as shown do not imply bus contention because t

CLZ

is a Min. parameter that is worse case at totally different test conditions (0 deg. C, 3.465V) than t

CHZ

which is a Max. parameter (worse case at 70 deg. C, 3.135V).

6. Commercial temperature range only.

150MHz

(6)

133MHz

100MHz

Symbol

Parameter

Min.

Max.

Min.

Max.

Min.

Max.

Unit

CYC

Clock Cycle Time

6.7

____

7.5

____

(1)

Clock Frequency

____

150

____

133

____

100

MHz

(2)

Clock High Pulse Width

2.0

____

2.2

____

3.2

____

(2)

Clock Low Pulse Width

2.0

____

2.2

____

3.2

____

Output Parameters

Clock High to Valid Data

____

3.8.

____

4.2

____

CDC

Clock High to Data Change

1.5

____

1.5

____

1.5

____

CLZ

(3,4,5)

Clock High to Output Active

1.5

____

1.5

____

1.5

____

CHZ

(3,4,5)

Clock High to Data High-Z

1.5

3.3

Output Enable Access Time

____

3.8

____

4.2

____

OLZ

(3,4)

Output Enable Low to Data Active

____

OHZ

(3,4)

Output Enable High to Data High-Z

____

3.8

____

4.2

____

Set Up Times

Clock Enable Setup Time

1.5

____

1.7

____

2.0

____

Address Setup Time

1.5

____

1.7

____

2.0

____

Data In Setup Time

1.5

____

1.7

____

2.0

____

Read/Write (R/

W) Setup Time

1.5

____

1.7

____

2.0

____

SADV

Advance/Load (ADV/

LD) Setup Time

1.5

____

1.7

____

2.0

____

Chip Enable/Select Setup Time

1.5

____

1.7

____

2.0

____

Byte Write Enable (

BWx) Setup Time

1.5

____

1.7

____

2.0

____

Hold Times

Clock Enable Hold Time

0.5

____

0.5

____

0.5

____

Address Hold Time

0.5

____

0.5

____

0.5

____

Data In Hold Time

0.5

____

0.5

____

0.5

____

Read/Write (R/

W) Hold Time

0.5

____

0.5

____

0.5

____

HADV

Advance/Load (ADV/

LD) Hold Time

0.5

____

0.5

____

0.5

____

Chip Enable/Select Hold Time

0.5

____

0.5

____

0.5

____

Byte Write Enable (

BWx) Hold Time

0.5

____

0.5

____

0.5

____

5304 tbl 24

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of Read Cycle

(1,2,3,4)

NOTES:

1. Q (A

) represents the first output from the external address A

. Q (A

) represents the first output from the external address A

; Q (A

2+1

) represents the next output data in the burst sequence

of the base address A

, etc. where address bits A0 and A1 are advancing for the four word burst in the sequence defined by the state of the

LBO

input.

2. CE

timing transitions are identical but inverted to the

and

signals. For example, when

and

are LOW on this waveform, CE

is HIGH.

3. Burst ends when new address and control are loaded into the SRAM by sampling ADV/

LOW.

4. R/

is don't care when the SRAM is bursting (ADV/

sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/

signal when new address

and control are loaded into the SRAM.

(

i
g

lim

i
nat

curr

ent

L-H

edg

lin

urst

r
aps

ound

i
t
ia

t
a

)

l
i
n

lin

5304

)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

D (A

) represents the first input to the external address A

. D (A

) represents the first input to the external address A

; D (A

2+1

) represents the next input data in the burst sequence of

the base address A

, etc. where address bits A

and A

are advancing for the four word burst in the sequence defined by the state of the

LBO

input.

2. CE

timing transitions are identical but inverted to the

and

signals. For example, when

and

are LOW on this waveform, CE2 is HIGH.

3
.

Burst ends when new address and control are loaded into the SRAM by sampling ADV/

LOW.

/
W

is don't care when the SRAM is bursting (ADV/

sampled HIGH). The nature of the burst access (Read or Write) is fixed by the state of the R/

signal when new address

and control are loaded into the SRAM.

5
.

Individual Byte Write signals (

x) must be valid on all write and burst-write cycles. A write cycle is initiated when R/

signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

Timing Waveform of Write Cycles

(1,2,3,4,5)

elin

t
e

i
pel

i
n

elin

rit

oun

i
n

t
a

t
e

)

(

i
gh

lim

i
nat

rre

-
H

ge)

)

(

)

(

)

5304

)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

)

t
e

)

NOTES:

Q (A

) represents the first output from the external address A

. D (A

) represents the input data to the SRAM corresponding to address A

2. CE

timing transitions are identical but inverted to the

and

signals. For example, when

and

are LOW on this waveform, CE

is HIGH.

3
.

Individual Byte Write signals (

x) must be valid on all write and burst-write cycles. A write cycle is initiated when R/

signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

Timing Waveform of Combined Read and Write Cycles

(1,2,3)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

NOTES:

Q (A

) represents the first output from the external address A

. D (A

) represents the input data to the SRAM corresponding to address A

2. CE

timing transitions are identical but inverted to the

and

signals. For example, when

and

are LOW on this waveform, CE

is HIGH.

CEN

when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The

part will behave as if the L-H clock transition did not

occur. All internal registers in the SRAM will retain their previous state.

4
.

Individual Byte Write signals (

x) must be valid on all write and burst-write cycles. A write cycle is initiated when R/

signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

Timing Waveform of CEN Operation

(1,2,3,4)

)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of CS Operation

(1,2,3,4)

NOTES:

1
.

Q (A

) represents the first output from the external address A

. D (A

) represents the input data to the SRAM corresponding to address A

2. CE

timing transitions are identical but inverted to the

and

signals. For example, when

and

are LOW on this waveform, CE

is HIGH.

CEN

when sampled high on the rising edge of clock will block that L-H transition of the clock from propogating into the SRAM. The

part will behave as if the L-H clock transition did not

occur. All internal registers in the SRAM will retain their previous state.

4
.

Individual Byte Write signals (

x) must be valid on all write and burst-write cycles. A write cycle is initiated when R/

signal is sampled LOW. The byte write information comes in two

cycles before the actual data is presented to the SRAM.

L
D

)

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMS with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Timing Waveform of OE Operation

(1)

NOTE:
1. A read operation is assumed to be in progress.

Ordering Information

DATA

OUT

OHZ

OLZ

Valid

5304 drw 11

100 pin Plastic Thin Quad Flatpack, (TQFP)
119 Ball Grid Array (BGA)
165 Fine Pitch Ball Grid Array (fBGA)

Power

Speed

Package

PF
BG
BQ

IDT

XXXX

150
133
100

Clock Frequency in Megahertz

5304 drw 12

Device

Type

IDT71V65603
IDT71V65803

256Kx36 Pipelined ZBT SRAM
512Kx18 Pipelined ZBT SRAM

Process/

Temperature

Range

Blank
I

Commerical (0° to 70°C)
Industrial (-40° to 85°C)

CORPORATE HEADQUARTERS

for SALES:

for Tech Support:

2975 Stender Way

800-345-7015 or 408-727-6116

sramhelp@idt.com

Santa Clara, CA 95054

fax: 408-492-8674

800-544-7726, x4033

www.idt.com

The IDT logo is a registered trademark of Integrated Device Technology, Inc.

6.42

IDT71V65603, IDT71V65803, 256K x 36, 512K x 18, 3.3V Synchronous SRAMs with
ZBT

Feature, 3.3V I/O, Burst Counter, and Pipelined Outputs Commercial and Industrial Temperature Ranges

Datasheet Document History

12/31/99

Created new datasheet from obsolete devices IDT71V656 and IDT71V658

03/04/00

Pg. 1,14,15 Removed 166MHz speed grade offering; Added 150MHz speed grade offering

04/20/00

Pg. 5,6

Added JTAG test pins to TQFP pin configuration; removed footnote

Pg. 5,6

Add clarification note to Recommended Operating temperature and Absolute Max Ratings tables

Pg. 7

Add note to BGA pin Configuration; correct typo within pinout

Pg. 21

Insert TQFP Package Diagram Outline

05/23/00

Add new package offering, 13 x 15mm 165 fBGA

Pg. 23

Correction in BG 119 Package Diagram Outline

07/28/00

Add industrial temperature

Pg. 2

Correction V

DDQ

3.3V I/O supply

Pg. 5-8

Remove JTAG offerings, refer to IDT71V656xx and IDT71V658xx device errata sheet

Pg. 7

Correct pin B2

Pg. 8

Change pin B1 to NC

Pg. 23

Update BG119 Package Diagram Outline

11/04/00

Pg. 8

Add note to pin N5 on BQ165 pinout, reserved for JTAG

TRST

Pg. 15

Add Izz parameter to DC Electrical Characteristics

10/16/01

Pg. 16

Changed sub-header to include Commercial and Industrial Temperature Ranges. Corrected the TCH

from 22ns to 2.2ns and TSADV from 20ns to 2.0ns.

12/04/02

Pg. 1-25

Changed datasheet from Prelininary to final release.

Pg. 15

Added I temp to 150MHz.

Pg. 16

Corrected typo from 22 to 2.2.

12/19/02

Pg. 1,2,5,6, Removed JTAG functionality for current die revision.

7,8
Pg. 7

Corrected pin configuration on the x36, 119BGA. Switched pins I/O0 and I/OP1.

Ð­Ð»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 71V65803

ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 71V65803