1
2002 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-4671/2
SEPTEMBER 2002
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SuperSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
IDT72261LA
IDT72271LA
CMOS SuperSync FIFO
TM
16,384 x 9
32,768 x 9
FEATURES:
Choose among the following memory organizations:
IDT72261LA 16,384 x 9
IDT72271LA 32,768 x 9
Pin-compatible with the IDT72281/72291 SuperSync FIFOs
10ns read/write cycle time (8ns access time)
Fixed, low first word data latency time
Auto power down minimizes standby power consumption
Master Reset clears entire FIFO
Partial Reset clears data, but retains programmable settings
Retransmit operation with fixed, low first word data latency time
Empty, Full and Half-Full flags signal FIFO status
Programmable Almost-Empty and Almost-Full flags, each flag
can default to one of two preselected offsets
Program partial flags by either serial or parallel means
Select IDT Standard timing (using EF and FF flags) or First
Word Fall Through timing (using OR and IR flags)
Output enable puts data outputs into high impedance state
Easily expandable in depth and width
Independent Read and Write clocks (permit reading and writing
simultaneously)
FUNCTIONAL BLOCK DIAGRAM
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
16,384 x 9
32,768 x 9
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN
WCLK
D
0
-D
8
LD
MRS
REN
RCLK
OE
Q
0
-Q
8
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
4671 drw 01
Available in the 64-pin Thin Quad Flat Pack (TQFP) and the 64-
pin Slim Thin Quad Flat Pack (STQFP)
High-performance submicron CMOS technology
Industrial temperature range (40C to +85C) is available
DESCRIPTION:
The IDT72261LA/72271LA are exceptionally deep, high speed, CMOS
First-In-First-Out (FIFO) memories with clocked read and write controls.
These FIFOs offer numerous improvements over previous SuperSync
FIFOs, including the following:
The limitation of the frequency of one clock input with respect to the other
has been removed. The Frequency Select pin (FS) has been removed,
thus it is no longer necessary to select which of the two clock inputs,
RCLK or WCLK, is running at the higher frequency.
The period required by the retransmit operation is now fixed and short.
The first word data latency period, from the time the first word is written
to an empty FIFO to the time it can be read, is now fixed and short. (The
variable clock cycle counting delay associated with the latency period found
on previous SuperSync devices has been eliminated on this SuperSync
family.)
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72261LA/72271LA SuperSync FIFOTM
16,384 x 9 and 32,768 x 9
PIN CONFIGURATIONS
TQFP (PN64-1, ORDER CODE: PF)
STQFP (PP64-1, ORDER CODE: TF)
TOP VIEW
DESCRIPTION (CONTINUED)
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
WEN
SEN
DC
(1)
V
CC
V
CC
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
GND
(2)
D8
D7
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
DNC
(3)
DNC
(3)
GND
DNC
(3)
DNC
(3)
V
CC
DNC
(3)
DNC
(3)
DNC
(3)
GND
DNC
(3)
DNC
(3)
Q8
Q7
Q6
GND
WCLK
PRS
MRS
LD
FWFT/SI
GND
FF
/
IR
PAF
HF
V
CC
PAE
EF
/
OR
RCLK
REN
RT
OE
Q5
Q4
V
CC
Q3
Q2
GND
Q1
Q0
GND
D0
D1
D2
D3
D4
D5
D6
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NOTES:
1. DC = Don't Care. Must be tied to GND or V
CC
, cannot be left open.
2. This pin may either be tied to ground or left open.
3. DNC = Do Not Connect.
SuperSync FIFOs are particularly appropriate for network, video, telecom-
munications, data communications and other applications that need to buffer
large amounts of data.
The input port is controlled by a Write Clock (WCLK) input and a Write Enable
(
WEN) input. Data is written into the FIFO on every rising edge of WCLK when
WEN is asserted. The output port is controlled by a Read Clock (RCLK) input
and Read Enable (
REN) input. Data is read from the FIFO on every rising
edge of RCLK when
REN is asserted. An Output Enable (OE) input is provided
for three-state control of the outputs.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to fMAX with complete independence. There are no restrictions on the
frequency of one clock input with respect to the other.
There are two possible timing modes of operation with these devices:
IDT Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not
appear on the data output lines unless a specific read operation is
performed. A read operation, which consists of activating REN and enabling
a rising RCLK edge, will shift the word from internal memory to the data output
lines.
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72261LA/72271LA SuperSync FIFOTM
16,384 x 9 and 32,768 x 9
DESCRIPTION (CONTINUED)
Figure 1. Block Diagram of Single 16,384 x 9 and 32,768 x 9 Synchronous FIFO
DATA OUT (Q
0
- Q
n
)
DATA IN (D
0
- D
n
)
MASTER RESET (
MRS)
READ CLOCK (RCLK)
READ ENABLE (
REN)
OUTPUT ENABLE (
OE)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
WRITE CLOCK (WCLK)
WRITE ENABLE (
WEN)
LOAD (
LD)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72261LA
72271LA
PARTIAL RESET (
PRS)
FIRST WORD FALL THROUGH/SERIAL INPUT
(FWFT/SI)
RETRANSMIT (
RT)
4671 drw 03
HALF FULL FLAG (
HF)
SERIAL ENABLE(
SEN)
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN
does not have to be asserted for accessing the first word. However,
subsequent words written to the FIFO do require a LOW on
REN for
access. The state of the FWFT/SI input during Master Reset determines
the timing mode in use.
For applications requiring more data storage capacity than a single
FIFO can provide, the FWFT timing mode permits depth expansion by
chaining FIFOs in series (i.e. the data outputs of one FIFO are connected
to the corresponding data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and
PAF (Programmable Almost-Full flag). The EF
and
FF functions are selected in IDT Standard mode. The IR and OR
functions are selected in FWFT mode.
HF, PAE and PAF are always
available for use, irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point
in memory. (See Table I and Table II.) Programmable offsets determine
the flag switching threshold and can be loaded by two methods: parallel or
serial. Two default offset settings are also provided, so that
PAE can be
set to switch at 127 or 1,023 locations from the empty boundary and the
PAF threshold can be set at 127 or 1,023 locations from the full boundary.
These choices are made with the LD pin during Master Reset.
For serial programming,
SEN together with LD on each rising edge of
WCLK, are used to load the offset registers via the Serial Input (SI). For
parallel programming,
WEN together with LD on each rising edge of WCLK,
are used to load the offset registers via Dn.
REN together with LD on each rising
edge of RCLK can be used to read the offsets in parallel from Qn regardless
of whether serial or parallel offset loading has been selected.
During Master Reset (
MRS) the following events occur: The read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode. The
LD pin selects either a partial flag default
setting of 127 with parallel programming or a partial flag default setting of 1,023
with serial programming. The flags are updated according to the timing mode
and default offsets selected.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, partial flag program-
ming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the
timing mode and offsets in effect.
PRS is useful for resetting a device in
mid-operation, when reprogramming partial flags would be undesirable.
The Retransmit function allows data to be reread from the FIFO more
than once. A LOW on the
RT input during a rising RCLK edge initiates a
retransmit operation by setting the read pointer to the first location of the
memory array.
If, at any time, the FIFO is not actively performing an operation, the chip
will automatically power down. Once in the power down state, the standby
supply current consumption is minimized. Initiating any operation (by
activating control inputs) will immediately take the device out of the power
down state.
The IDT72261LA/72271LA are fabricated using IDT's high speed sub-
micron CMOS technology.
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COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72261LA/72271LA SuperSync FIFOTM
16,384 x 9 and 32,768 x 9
Symbol
Name
I/O
Description
D
0
D
8
Data Inputs
I
Data inputs for a 9-bit bus.
MRS
Master Reset
I
MRS initializes the read and write pointers to zero and sets the output register to all zeroes.
During Master Reset, the FIFO is configured for either FWFT or IDT Standard mode, one of
two programmable flag default settings, and serial or parallel programming of the offset settings.
PRS
Partial Reset
I
PRS initializes the read and write pointers to zero and sets the output method (serial or parallel),
and programmable flag settings are all retained.
RT
Retransmit
I
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to
LOW (
OR to HIGH in FWFT mode) temporarily and does not disturb the write pointer, programming
method, existing timing mode or programmable flag settings.
RT is useful to reread data from the
first physical location of the FIFO.
FWFT/SI
First Word Fall
I
During Master Reset, selects First Word Fall Through or IDT Standard mode. Through/Serial
In After Master Reset, this pin functions as a serial input for loading offset registers
WCLK
Write Clock
I
When enabled by
WEN, the rising edge of WCLK writes data into the FIFO and offsets into
the programmable registers for parallel programming, and when enabled by
SEN, the rising
edge of WCLK writes one bit of data into the programmable register for serial programming.
WEN
Write Enable
I
WEN enables WCLK for writing data into the FIFO memory and offset registers.
RCLK
Read Clock
I
When enabled by
REN, the rising edge of RCLK reads data from the FIFO memory and offsets
from the programmable registers.
REN
Read Enable
I
REN enables RCLK for reading data from the FIFO memory and offset registers.
OE
Output Enable
I
OE controls the output impedance of Q
n.
SEN
Serial Enable
I
SEN enables serial loading of programmable flag offsets.
LD
Load
I
During Master Reset,
LD selects one of two partial flag default offsets (127 or 1,023) and determines
the flag offset programming method, serial or parallel. After Master Reset, this pin enables writing to
and reading from the offset registers.
DC
Don't Care
I
This pin must be tied to either V
CC
or GND and must not toggle after Master Reset.
FF/IR
Full Flag/
O
In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO memory
Input Ready
is full. In the FWFT mode, the
IR function is selected. IR indicates whether or not there is space
available for writing to the FIFO memory.
EF/OR
Empty Flag/
O
In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO memory
Output Ready
is empty. In FWFT mode, the
OR function is selected. OR indicates whether or not there is valid data
available at the outputs.
PAF
Programmable
O
PAF goes LOW if the number of words in the FIFO memory is more than word capacity of the FIFO
Almost-Full Flag
minus the full offset value m, which is stored in the Full Offset register. There are two possible default
values for m: 127 or 1,023.
PAE
Programmable
O
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the
Almost-Empty Flag
Empty Offset register. There are two possible default values for n: 127 or 1,023. Other values for n
can be programmed into the device.
HF
Half-Full Flag
O
HF indicates whether the FIFO memory is more or less than half-full.
Q
0
Q
8
Data Outputs
O
Data outputs for a 9-bus
V
CC
Power
+5 Volt power supply pins.
GND
Ground
Ground pins.
PIN DESCRIPTION
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72261LA/72271LA SuperSync FIFOTM
16,384 x 9 and 32,768 x 9
Symbol
Parameter
Min.
Typ.
Max.
Unit
V C C
Supply Voltage
4.5
5.0
5.5
V
Commercial/Industrial
GND
Supply Voltage
0
0
0
V
VIH
Input High Voltage
2.0
--
--
V
Commercial/Industrial
VIL
(1)
Input Low Voltage
--
--
0.8
V
Commercial/Industrial
TA
Operating Temperature
0
--
+70
C
Commercial
TA
Operating Temperature
40
--
+85
C
Industrial
Symbol
Rating
Com'l & Ind'l
Unit
V
TERM
Terminal Voltage
0.5 to +7
V
with respect to GND
T
STG
Storage
55 to +125
C
Temperature
I
OUT
DC Output Current
50 to +50
mA
NOTES:
1. With output deselected, (
OE
VIH).
2. Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Commercial: VCC = 5V 10%, TA = 0
C to +70C; Industrial: VCC = 5V 10%, TA = 40C to +85C)
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
(2)
Input
V
IN
= 0V
10
pF
Capacitance
C
OUT
(1,2)
Output
V
OUT
= 0V
10
pF
Capacitance
NOTE:
1.5V undershoots are allowed for 10ns once per cycle.
IDT72261LA
IDT72271LA
Commercial and Industrial
(1)
t
CLK
= 10, 15, 20 ns
Symbol
Parameter
Min.
Max.
Unit
I
LI
(2)
Input Leakage Current
1
1
A
I
LO
(3)
Output Leakage Current
10
10
A
V
OH
Output Logic "1" Voltage, I
OH
= 2 mA
2.4
--
V
V
OL
Output Logic "0" Voltage, I
OL
= 8 mA
--
0.4
V
I
CC1
(4,5,6)
Active Power Supply Current
--
75
mA
I
CC2
(4,7)
Standby Current
--
20
mA
NOTES:
1. Industrial temperature range product for the 15ns and 20ns speed grade are available as a standard device.
2. Measurements with 0.4
V
IN
V
CC
.
3.
OE
V
IH
, 0.4
V
OUT
V
CC
.
4. Tested with outputs disabled (I
OUT
= 0).
5. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
6. Typical I
CC1
= 15 + 1.85*fS + 0.02*C
L
*f
S
(in mA) with V
CC
= 5V, t
A
= 25
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2,
C
L
= capacitive load (in pF).
7. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
ABSOLUTE MAXIMUM RATINGS
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED DC OPERATING
CONDITIONS
CAPACITANCE
(T
A
= +25C, f = 1.0MHz)
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