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Электронный компонент: 723652

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2001 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-5609/3
AUGUST 2001
CMOS SyncBiFIFO
TM
2,048 x 36 x 2
4,096 x 36 x 2
8,192 x 36 x 2
PRELIMINARY
IDT723652
IDT723662
IDT723672
COMMERCIAL TEMPERATURE RANGE
IDT, the IDT logo are registered trademarks of Integrated Device Technology, Inc. SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
.EATURES:




Memory storage capacity:
IDT723652
2,048 x 36 x 2
IDT723662
4,096 x 36 x 2
IDT723672
8,192 x 36 x 2




Supports clock frequencies up to 83MHz




Fast access times of 8ns




Free-running CLKA and CLKB may be asynchronous or coincident
(simultaneous reading and writing of data on a single clock edge
is permitted)




Two independent clocked FIFOs buffering data in opposite direc-
tions




Mailbox bypass register for each FIFO




Programmable Almost-Full and Almost-Empty flags




Microprocessor Interface Control Logic




FFA/IRA, EFA/ORA, AEA, and AFA flags synchronized by CLKA




FFB/IRB, EFB/ORB, AEB, and AFB flags synchronized by CLKB




Select IDT Standard timing (using
EFA, EFB, FFA and FFB flags
functions) or First Word Fall Through timing (using ORA, ORB, IRA
and IRB flag functions)




Available in 132-pin Plastic Quad Flatpack (PQFP) or space-saving
120-pin Thin Quad Flatpack (TQFP)




Pin compatible to the lower density parts, IDT723622/723632/723642




Industrial temperature range (40


C to +85


C) is available
DESCRIPTION:
The IDT723652/723662/723672 is a monolithic, high-speed, low-power,
CMOS Bidirectional SyncFIFO (clocked) memories which support clock
frequencies up to 83MHz and have read access times as fast as 8ns. Two
independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs on board each
chip buffer data in opposite directions. Communication between each port may
bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has
a flag to signal when new mail has been stored.
.UNCTIONAL BLOCK DIAGRAM
Mail 1
Register
Programmable Flag
Offset Registers
Input
Register
Output
Register
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
Write
Pointer
Read
Pointer
Status Flag
Logic
Input
Register
Output
Register
Write
Pointer
Read
Pointer
Status Flag
Logic
CLKA
CSA
W/
R
A
ENA
MBA
Port-A
Control
Logic
FIFO1,
Mail1
Reset
Logic
RST1
Mail 2
Register
MBF2
CLKB
CSB
W
/RB
ENB
MBB
Port-B
Control
Logic
FIFO2,
Mail2
Reset
Logic
RST2
MBF1
FIFO 1
FIFO 2
13
EFB
/ORB
AEB
36
36
FFB
/IRB
AFB
B
0
- B
35
FFA
/IRA
AFA
FS
0
FS
1
A
0
- A
35
EFA
/ORA
AEA
5609 drw 01
36
36
Timing
Mode
FWFT
RAM
ARRAY
2,048 x 36
4,096 x 36
8,192 x 36
2
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
DESCRIPTION (Continued)
NOTES:
1. NC no internal connection
2. Uses Yamaichi socket IC51-1324-828
PQFP
(2)
(PQ132-1, order code: PQF)
TOP VIEW
NC
NC
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
NC
NC
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
NC
NC
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
5609 drw 02
NC
NC
NC
V
CC
CLKB
ENB
W
/RB
CSB
GND
AFB AEB
V
CC
MBF1
MBB
RST2
FS1
GND
FS0
RST1
MBA
MBF2 AEA AFA
V
CC
EFA
/ORA
FFA
/IRA
CSA
W/
R
A
ENA CLKA
GND
117
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
132
131
130
129
128
127
126
125
124
123
122
121
120
119
118
NC
NC
B
11
B
10
B
9
B
7
B
8
V
CC
B
6
GND
B
5
B
4
B
3
B
2
B
1
B
0
GND
A
0
A
1
A
2
V
CC
A
3
A
4
A
5
GND
A
6
A
7
A
8
A
9
A
10
A
11
GND
NC
74
76
77
78
79
80
81
82
83
75
51
52
53
54
55
56
57
58
59
60
61 62
63
64
65
66
67
68
69
70
71
72
73
FFB
/IRB
EFB
/ORB
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the
FWFT pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (
EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/
IRB). The
EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty.
FF shows whether the
memory is full or not. The IR and OR functions are selected in the First Word
*
Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
PIN CON.IGURATION
3
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
PIN CON.IGURATION (Continued)
TQFP (PN120-1, order code: PF)
TOP VIEW
5609 drw 03
A
35
A
34
A
33
A
32
V
CC
A
31
A
30
GND
A
29
A
28
A
27
A
26
A
25
A
24
A
23
FWFT
A
22
V
CC
A
21
A
20
A
19
A
18
GND
A
17
A
16
A
15
A
14
A
13
V
CC
A
12
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
B
35
B
34
B
33
B
32
GND
B
31
B
30
B
29
B
28
B
27
B
26
V
CC
B
25
B
24
GND
B
23
B
22
B
21
B
20
B
19
B
18
GND
B
17
B
16
V
CC
B
15
B
14
B
13
B
12
GND
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
91
120
119
118
117
116
115
114
113
112
111
110
109
108
107
106
105
104
103
102
101
100
99
98
97
96
95
94
93
92
V
CC
GND
CLKA
ENA
W/
R
A
CSA FFA
/IRA
EFA
/ORA
V
CC
AFA AEA MBF2
MBA
RST1
FS0
GND
FS1
RST2
MBB
MBF1
V
CC
AEB AFB EFB
/
ORB
FFB
/
IRB
GND
CSB W
/RB
ENB
CLKB
GND
A
11
A
10
A
9
A
8
A
7
A
6
GND
A
5
A
4
A
3
V
CC
A
2
A
1
A
0
GND
B
0
B
1
B
2
B
3
B
4
B
5
GND
B
6
V
CC
B
7
B
8
B
9
B
10
B
11
31
32
33
34 35 36
37 38
39
40
41
42
43
44
45
46
47 48
49
50
51
52
53
54 55
56
57 58
59
60
Fall Through mode. IR indicates whether or not the FIFO has available memory
locations. OR shows whether the FIFO has data available for reading or not.
It marks the presence of valid data on the outputs.
Each FIFO has a programmable Almost-Empty flag (
AEA and AEB) and
a programmable Almost-Full flag (
AFA and AFB). AEA and AEB indicate when
a selected number of words remain in the FIFO memory.
AFA and AFB indicate
when the FIFO contains more than a selected number of words.
FFA/IRA, FFB/IRB, AFA and AFB are two-stage synchronized to the port
clock that writes data into its array.
EFA/ORA, EFB/ORB, AEA and AEB are two-
stage synchronized to the port clock that reads data from its array. Program-
mable offsets for
AEA, AEB, AFA and AFB are loaded by using Port A. Three
default offset settings are also provided. The
AEA and AEB threshold can be
set at 8, 16 or 64 locations from the empty boundary and the
AFA and AFB
threshold can be set at 8, 16 or 64 locations from the full boundary. All these
choices are made using the FS0 and FS1 inputs during Reset.
Two or more devices may be used in parallel to create wider data paths.
If, at any time, the FIFO is not actively performing a function, the chip will
automatically power down. During the power down state, supply current
consumption (I
CC
) is at a minimum. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
The IDT723652/723662/723672 are characterized for operation from 0
C
to 70
C. Industrial temperature range (-40
C to +85
C) is available by special
order. They are fabricated using IDT's high speed, submicron CMOS
technology.
4
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Symbol
Name
I/O
Description
A0-A35
Port A Data
I/0
36-bit bidirectional data port for side A.
AEA
Port A Almost-
O
Programmable Almost-Empty flag synchronized to CLKA. It is LOW when the number of words in FIFO2 is
Empty Flag
(Port A)
less than or equal to the value in the Almost-Empty A Offset register, X2.
AEB
Port B Almost-
O
Programmable Almost-Empty flag synchronized to CLKB. It is LOW when the number of words in FIFO1 is
Empty Flag
(Port B)
less than or equal to the value in the Almost-Empty B Offset register, X1.
AFA
Port A Almost-
O
Programmable Almost-Full flag synchronized to CLKA. It is LOW when the number of empty locations in
Full Flag
(Port A)
FIFO1 is less than or equal to the value in the Almost-Full A Offset register, Y1.
AFB
Port B Almost-
O
Programmable Almost-Full flag synchronized to CLKB. It is LOW when the number of empty locations in
Full Flag
(Port B)
FIFO2 is less than or equal to the value in the Almost-Full B Offset register, Y2.
B0 - B35
Port B Data
I/O
36-bit bidirectional data port for side B.
CLKA
Port A Clock
I
CLKA is a continuous clock that synchronizes all data transfers through port A and can be asynchronous or
coincident to CLKB.
FFA/IRA, EFA/ORA, AFA, and AEA are all synchronized to the LOW-to-HIGH
transition of CLKA.
CLKB
Port B Clock
I
CLKB is a continuous clock that synchronizes all data transfers through port Band can be asynchronous or
coincident to CLKA.
FFB/IRB, EFB/ORB, AFB, and AEB are synchronized to the LOW-to-HIGH
transition of CLKB.
CSA
Port A Chip
I
CSA must be LOW to enable a LOW-to-HIGH transition of CLKA to read or write on port A. The A0-A35
Select
outputs are in the high-impedance state when
CSA is HIGH.
CSB
Port B Chip
I
CSB must be LOW to enable a LOW-to-HIGH transition of CLKB to read or write data on port B. The
Select
B0- B35 outputs are in the high-impedance state when
CSB is HIGH.
EFA/ORA
Port A Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFA function is selected. EFA indicates
Output Ready
whether or not the FIFO2 memory is empty. In the FWFT mode, the ORA function is selected. ORA
Flag
indicates the presence of valid data on A0-A35 outputs, available for reading.
EFA/ORA is synchronized
to the LOW-to-HIGH transition of CLKA.
EFB/ORB
Port B Empty/
O
This is a dual function pin. In the IDT Standard mode, the
EFB function is selected. EFB indicates
Output Ready
whether or not the FIFO1 memory is empty. In the FWFT mode, the ORB function is selected. ORB
Flag
indicates the presence of valid data on B0-B35 outputs, available for reading.
EFB/ORB is synchronized to
the LOW-to-HIGH transition of CLKB.
ENA
Port A Enable
I
ENA must be HIGH to enable a LOW-to-HIGH transition of CLKA to read or write data on port A.
ENB
Port B Enable
I
ENB must be HIGH to enable a LOW-to-HIGH transition of CLKB to read or write data on port B.
FFA/IRA
Port A Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFA function is selected. FFA indicates
Input Ready
whether or not the FIFO1 memory is full. In the FWFT mode, the IRA function is selected. IRA
Flag
indicates whether or not there is space available for writing to the FIFO1 memory.
FFA/IRA is
synchronized to the LOW-to-HIGH transition of CLKA.
FFB/IRB
Port B Full/
O
This is a dual function pin. In the IDT Standard mode, the
FFB function is selected. FFB indicates
Input Ready
whether or not the FIFO2 memory is full. In the FWFT mode, the IRB function is selected. IRB
Flag
indicates whether or not there is space available for writing to the FIFO2 memory.
FFB/IRB is
synchronized to the LOW-to-HIGH transition of CLKB.
FWFT
First Word Fall
I
This pin selects the timing mode. A HIGH on
FWFT selects IDT Standard mode, a LOW selects First
Through Mode
Word Fall Through mode. Once the timing mode has been selected, the level on
FWFT must be static
throughout device operation.
FS1, FS0
Flag Offset
I
A LOW-to-HIGH transition of the FIFO Reset input latches the values of FS0 and FS1. If either FS0 or
Selects
FS1 is HIGH when the FIFO Reset input goes HIGH, one of three preset values is selected as the
offset for FIFOs Almost-Full and Almost-Empty flags. If both FIFOs are reset simultaneously and both
FS0 and FS1 are LOW when
RST1 and RST2 go HIGH, the first four writes to FIFO1 load the Almost-
Empty and Almost-Full offsets for both FIFOs.
PIN DESCRIPTIONS
5
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Symbol
Name
I/O
Description
MBA
Port A Mailbox
I
A HIGH level on MBA chooses a mailbox register for a port A read or write operation. When the
Select
A0-A35 outputs are active, a HIGH level on MBA selects data from the mail2 register for output and a
LOW level selects FIFO2 output register data for output.
MBB
Port B Mailbox
I
A HIGH level on MBB chooses a mailbox register for a port B read or write operation. When the
Select
B0-B35 outputs are active, a HIGH level on MBB selects data from the mail1 register or output and a
LOW level selects FIFO1 output register data for output.
MBF1
Mail1 Register
O
MBF1 is set LOW by a LOW-to-HIGH transition of CLKA that writes data to the mail1 register.
Flag
Writes to the mail1 register are inhibited while
MBF1 is LOW. MBF1 is set HIGH by a LOW-to-HIGH
transition of CLKB when a port B read is selected and MBB is HIGH.
MBF1 is set HIGH when FIFO1
is reset.
MBF2
Mail2 Register
O
MBF2 is set LOW by a LOW-to-HIGH transition of CLKB that writes data to the mail2 register. Writes
Flag
to the mail2 register are inhibited while
MBF2 is LOW. MBF2 is set HIGH by a LOW-to-HIGH
transition of CLKA when a port A read is selected and MBA is HIGH.
MBF2 is also set HIGH when
FIFO2 is reset.
RST1
FIFO1 Reset
I
To reset FIFO1, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur
while
RST1 is LOW. The LOW-to-HIGH transition of RST1 latches the status of FS0 and FS1 for AFA
and
AEB offset selection. FIFO1 must be reset upon power up before data is written to its RAM.
RST2
FIFO2 Reset
I
To reset FIFO2, four LOW-to-HIGH transitions of CLKA and four LOW-to-HIGH transitions of CLKB must occur
while
RST2 is LOW. The LOW-to-HIGH transition of RST2 latches the status of FS0 and FS1 for AFB
and
AEA offset selection. FIFO2 must be reset upon power up before data is written to its RAM.
W/
RA
Port A Write/
I
A HIGH selects a write operation and a LOW selects a read operation on port A for a LOW-to-HIGH
Read Select
transition of CLKA. The A0-A35 outputs are in the HIGH impedance state when W/
RA is HIGH.
W/RB
Port B Write/
I
A LOW selects a write operation and a HIGH selects a read operation on port B for a LOW-to-HIGH
Read Select
transition of CLKB. The B0-B35 outputs are in the HIGH impedance state when
W/RB is LOW.
PIN DESCRIPTIONS (Continued)
6
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
ABSOLUTE MAXIMUM RATINGS OVER OPERATING .REE-AIR
TEMPERATURE RANGE (Unless otherwise noted)
(1)
Symbol
Rating
Commercial
Unit
V
CC
Supply Voltage Range
0.5 to +7.0
V
V
I
(2)
Input Voltage Range
0.5 to V
CC
+0.5
V
V
O
(2)
Output Voltage Range
0.5 to V
CC
+0.5
V
I
IK
Input Clamp Current (V
I
< 0 or V
I
> V
CC
)
20
mA
I
OK
Output Clamp Current (V
O
= < 0 or V
O
> V
CC
)
50
mA
I
OUT
Continuous Output Current (V
O
= 0 to V
CC
)
50
mA
I
CC
Continuous Current Through V
CC
or GND
400
mA
T
STG
Storage Temperature Range
65 to 150
C
NOTES:
1. Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these
or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute maximum rated conditions for extended periods may affect
device reliability.
2. The input and output voltage ratings may be exceeded provided the input and output current ratings are observed.
ELECTRICAL CHARACTERISTICS OVER RECOMMENDED OPERATING .REE-
AIR TEMPERATURE RANGE (Unless otherwise noted)
NOTES:
1. All typical values are at V
CC
= 5V, T
A
= 25
C.
2. For additional I
CC
information, see Figure 1, Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
).
3. Characterized values, not currently tested.
4. Industrial temperature range is available by special order.
IDT723652
IDT723662
IDT723672
Commercial
t
CLK
= 12, 15 ns
Symbol
Parameter
Test Conditions
Min.
Typ.
(1)
Max.
Unit
V
OH
Output Logic "1" Voltage
V
CC
= 4.5V,
I
OH
= 4 mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage
V
CC
= 4.5V,
I
OL
= 8 mA
--
--
0.5
V
I
LI
Input Leakage Current (Any Input)
V
CC
= 5.5V,
V
I
= V
CC
or 0
--
--
10
A
I
LO
Output Leakage Current
V
CC
= 5.5V,
V
O
= V
CC
or 0
--
--
10
A
I
CC2
(2)
Standby Current (with CLKA & CLKB running)
V
CC
= 5.5V,
V
I
= V
CC
0.2V or 0V
--
--
8
mA
I
CC3
(2)
Standby Current (no clocks running)
V
CC
= 5.5V,
V
I
= V
CC
0.2V or 0V
--
--
1
mA
C
IN
(3)
Input Capacitance
V
I
= 0,
f = 1 MHz
--
4
--
pF
C
OUT
(3)
Output Capacitance
V
O
= 0,
f = 1 MHZ
--
8
--
pF
Symbol
Parameter
Min.
Max.
Unit
V
CC
Supply Voltage
4.5
5.5
V
V
IH
HIGH Level Input Voltage
2
V
V
IL
LOW-Level Input Voltage
0.8
V
I
OH
HIGH-Level Output Current
4
mA
I
OL
LOW-Level Output Current
8
mA
T
A
Operating Free-air Temperature
0
70
C
RECOMMENDED OPERATING CONDITIONS
7
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Figure 1. Typical Characteristics: Supply Current (I
CC
) vs. Clock Frequency (f
S
)
0
10
20
30
40
50
60
70
0
50
100
150
200
250
300
V
CC
= 5.0V
f
S
Clock Frequency
MHz
I
CC(f)
Supply Current
mA
f
data
= 1/2 f
S
T
A
= 25
o
C
C
L
= 0 pF
V
CC
= 4.5V
V
CC
= 5.5V
5609 drw03a
80
90
Calculating Power Dissipation
The I
CC(f)
current for the graph in Figure 1 was taken while simultaneously reading and writing a FIFO on the IDT723652/723662/723672 with
CLKA and CLKB set to f
S
. All data inputs and data outputs change state during each clock cycle to consume the highest supply current. Data outputs were
disconnected to normalize the graph to a zero capacitance load. Once the capacitance load per data-output channel and the number of these device's
inputs driven by TTL HIGH levels are known, the power dissipation can be calculated with the equation below.
With I
CC(f)
taken from Figure 1, the maximum power dissipation (P
T
) of these FIFOs may be calculated by:
P
T
= V
CC
x [I
CC
(f) + (N x I
CC
x dc)] +
(C
L
x V
CC
2
X fo)
where:
N
= number of inputs driven by TTL levels
I
CC
= increase in power supply current for each input at a TTL HIGH level
dc
= duty cycle of inputs at a TTL HIGH level of 3.4 V
C
L
= output capacitance load
fo
= switching frequency of an output
8
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Commercial
IDT723652L12
IDT723652L15
IDT723662L12
IDT723662L15
IDT723672L12
IDT723672L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
f
S
Clock Frequency, CLKA or CLKB
--
83
--
66.7
MHz
t
CLK
Clock Cycle Time, CLKA or CLKB
12
--
15
--
ns
t
CLKH
Pulse Duration, CLKA or CLKB HIGH
5
--
6
--
ns
t
CLKL
Pulse Duration, CLKA and CLKB LOW
5
--
6
--
ns
t
DS
Setup Time, A0-A35 before CLKA
and B0-B35 before CLKB
3
--
4
--
ns
t
ENS1
Setup Time,
CSA and W/RA, before CLKA
;
CSB, and W/RB before CLKB
4
--
4.5
--
ns
t
ENS2
Setup Time, ENA and MBA, before CLKA
; ENB, and MBB before CLKB
3
--
4.5
--
ns
t
RSTS
Setup Time,
RST1 or RST2 LOW before CLKA
or CLKB
(1)
5
--
5
--
ns
t
FSS
Setup Time, FS0 and FS1 before
RST1 and RST2 HIGH
7.5
--
7.5
--
ns
t
FWS
Setup Time,
FWFT before CLKA
0
--
0
--
ns
t
DH
Hold Time, A0-A35 after CLKA
and B0-B35 after CLKB
0.5
--
1
--
ns
t
ENH
Hold Time,
CSA, W/RA, ENA, and MBA after CLKA
;
CSB, W/RB, ENB, and
0.5
--
1
--
ns
MBB after CLKB
t
RSTH
Hold Time,
RST1 or RST2 LOW after CLKA
or CLKB
(1)
4
--
4
--
ns
t
FSH
Hold Time, FS0 and FS1 after
RST1 and RST2 HIGH
2
--
2
--
ns
t
SKEW1
(2)
Skew Time, between CLKA
and CLKB
for
EFA/ORA, EFB/ORB, FFA/IRA,
7.5
--
7.5
--
ns
and
FFB/IRB
t
SKEW2
(2,3)
Skew Time, between CLKA
and CLKB
for
AEA, AEB, AFA, and AFB
12
--
12
--
ns
NOTES:
1. Requirement to count the clock edge as one of at least four needed to reset a FIFO.
2. Skew time is not a timing constraint for proper device operation and is only included to illustrate the timing relationship between CLKA cycle and CLKB cycle.
3. Design simulated, not tested.
4. Industrial temperature range is available by special order.
TIMING REQUIREMENTS OVER RECOMMENDED RANGES O. SUPPLY
VOLTAGE AND OPERATING .REE-AIR TEMPERATURE
(Commercial: V
CC
= 5V 10%, T
A
= 0
C to +70
C)
9
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
SWITCHING CHARACTERISTICS OVER RECOMMENDED RANGES O. SUPPLY
VOLTAGE AND OPERATING .REE-AIR TEMPERATURE, C
L
= 30 p.
Commercial
IDT723652L12
IDT723652L15
IDT723662L12
IDT723662L15
IDT723672L12
IDT723672L15
Symbol
Parameter
Min.
Max.
Min.
Max.
Unit
t
A
Access Time, CLKA
to A0-A35 and CLKB
to B0-B35
2
8
2
10
ns
t
PIR
Propagation Delay Time, CLKA
to
FFA/IRA and CLKB
to
FFB/IRB
2
8
2
8
ns
t
POR
Propagation Delay Time, CLKA
to
EFA/ORA and CLKB
to
EFB/ORB
1
8
1
8
ns
t
PAE
Propagation Delay Time, CLKA
to
AEA and CLKB
to
AEB
1
8
1
8
ns
t
PAF
Propagation Delay Time, CLKA
to
AFA and CLKB
to
AFB
1
8
1
8
ns
t
PMF
Propagation Delay Time, CLKA
to
MBF1 LOW or MBF2 HIGH and CLKB
to
MBF2 LOW
0
8
0
8
ns
or
MBF1 HIGH
t
PMR
Propagation Delay Time, CLKA
to B0-B35
(1)
and CLKB
to A0-A35
(2)
2
8
2
10
ns
t
MDV
Propagation Delay Time, MBA to A0-A35 valid and MBB to B0-B35 Valid
2
8
2
10
ns
t
PRF
Propagation Delay Time
,
RST1 LOW to AEB LOW, AFA HIGH, and MBF1 HIGH, and RST2
1
10
1
15
ns
LOW to
AEA LOW, AFB HIGH, and MBF2 HIGH
t
EN
Enable Time,
CSA and W/RA LOW to A0-A35 Active and CSB LOW and W/RB HIGH
2
6
2
10
ns
to B0-B35 Active
t
DIS
Disable Time,
CSA or W/RA HIGH to A0-A35 at high-impedance and CSB HIGH or W/RB LOW
1
6
1
8
ns
to B0-B35 at high-impedance
NOTES:
1. Writing data to the mail1 register when the B0-B35 outputs are active and MBB is HIGH.
2. Writing data to the mail2 register when the A0-A35 outputs are active and MBA is HIGH.
3. Industrial temperature range is available by special order.
(Commercial: V
CC
= 5V 10%, T
A
= 0
C to +70
C)
10
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
read request necessary. Subsequent words must be accessed by performing
a formal read operation.
Following Reset, the level applied to the
FWFT input to choose the desired
timing mode must remain static throughout FIFO operation. Refer to Figure 2
(Reset) for a First Word Fall Through select timing diagram.
ALMOST-EMPTY FLAG AND ALMOST-FULL FLAG OFFSET PROGRAM-
MING
Four registers in these devices are used to hold the offset values for the
Almost-Empty and Almost-Full flags. The port B Almost-Empty flag (
AEB) Offset
register is labeled X1 and the port A Almost-Empty flag (
AEA) Offset register
is labeled X2. The port A Almost-Full flag (
AFA) Offset register is labeled Y1
and the port B Almost-Full flag (
AFB) Offset register is labeled Y2. The index
of each register name corresponds to its FIFO number. The offset registers can
be loaded with preset values during the reset of a FIFO or they can be
programmed from port A (see Table 1).
FS0 and FS1 function the same way in both IDT Standard and FWFT
modes.
-- PRESET VALUES
To load the FIFO's Almost-Empty flag and Almost-Full flag Offset registers
with one of the three preset values listed in Table 1, at least one of the flag select
inputs must be HIGH during the LOW-to-HIGH transition of its reset input. For
example, to load the preset value of 64 into X1 and Y1, FS0 and FS1 must be
HIGH when FlFO1 Reset (
RST1) returns HIGH. Flag offset registers
associated with FIFO2 are loaded with one of the preset values in the same way
with FIFO2 Reset (
RST2) toggled simultaneously with FIFO1 Reset (RST1).
For preset value loading timing diagram, see Figure 2.
-- PARALLEL LOAD FROM PORT A
To program the X1, X2, Y1, and Y2 registers from port A, both FlFOs should
be reset simultaneously with FS0 and FS1 LOW during the LOW-to-HIGH
transition of the Reset inputs. It is important to note that once parallel programming
has been selected during a Master Reset by holding both FS0 & FS1 LOW, these
inputs must remain LOW during all subsequent FIFO operation. They can only
be toggled HIGH when future Master Resets are performed and other
programming methods are desired.
After this reset is complete, the first four writes to FIFO1 do not store data
in the FIFO memory but load the offset registers in the order Y1, X1, Y2, X2.
SIGNAL DESCRIPTION
RESET
After power up, a Master Reset operation must be performed by providing
a LOW pulse to
RST1 and RST2 simultaneously. Afterwards, the FIFO
memories of the IDT723652/723662/723672 are reset separately by taking
their Reset (
RST1, RST2) inputs LOW for at least four port-A Clock (CLKA)
and four port-B Clock (CLKB) LOW-to-HIGH transitions. The Reset inputs can
switch asynchronously to the clocks. A FIFO reset initializes the internal read
and write pointers and forces the Input Ready flag (IRA, IRB) LOW, the Output
Ready flag (ORA, ORB) LOW, the Almost-Empty flag (
AEA, AEB) LOW, and
the Almost-Full flag (
AFA, AFB) HIGH. Resetting a FIFO also forces the
Mailbox Flag (
MBF1, MBF2) of the parallel mailbox register HIGH. After a
FIFO is reset, its Input Ready flag is set HIGH after two clock cycles to begin
normal operation.
A LOW-to-HIGH transition on a FIFO Reset (
RST1, RST2) input latches
the value of the Flag Select (FS0, FS1) inputs for choosing the Almost-Full and
Almost-Empty offset programming method. (For details see Table 1, Flag
Programming
, and the Programming the Almost-Empty and Almost-Full Flags
section). The relevant FIFO Reset timing diagram can be found in Figure 2.
FIRST WORD FALL THROUGH (
FWFT)
After Master Reset, the FWFT select function is active, permitting a choice
between two possible timing modes: IDT Standard mode or First Word Fall
Through (FWFT) mode. Once the Reset (
RST1, RST2) input is HIGH, a HIGH
on the
FWFT input during the next LOW-to-HIGH transition of CLKA (for
FIFO1) and CLKB (for FIFO2) will select IDT Standard mode. This mode uses
the Empty Flag function (
EFA, EFB) to indicate whether or not there are any
words present in the FIFO memory. It uses the Full Flag function (
FFA, FFB)
to indicate whether or not the FIFO memory has any free space for writing. In
IDT Standard mode, every word read from the FIFO, including the first, must
be requested using a formal read operation.
Once the Reset (
RST1, RST2) input is HIGH, a LOW on the FWFT input
during the next LOW-to-HIGH transition of CLKA (for FIFO1) and CLKB (for
FIFO2) will select FWFT mode. This mode uses the Output Ready function
(ORA, ORB) to indicate whether or not there is valid data at the data outputs
(A0-A35 or B0-B35). It also uses the Input Ready function (IRA, IRB) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to data outputs, no
NOTES:
1. X1 register holds the offset for
AEB; Y1 register holds the offset for AFA.
2. X2 register holds the offset for
AEA; Y2 register holds the offset for AFB.
3. If parallel programming is selected during a Master Reset, then FS0 & FS1 must remain LOW during FIFO operation.
FS1
FS0
RST1
RST2
X1 AND Y1 REGlSTERS
(1)
X2 AND Y2 REGlSTERS
(2)
H
H
X
64
X
H
H
X
X
64
H
L
X
16
X
H
L
X
X
16
L
H
X
8
X
L
H
X
X
8
L
L
Parallel programming via Port A
(3)
Parallel programming via Port A
(3)
TABLE 1
.LAG PROGRAMMING
11
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
The port A data inputs used by the offset registers are (A7-A0), (A8-A0), or (A9-
A0) for the IDT723652, IDT723662, or IDT723672, respectively. The highest
numbered input is used as the most significant bit of the binary number in each
case. Valid programming values for the registers ranges from 1 to 2,044 for the
IDT723652; 1 to 4,092 for the IDT723662; and 1 to 8,188 for the IDT723672.
After all the offset registers are programmed from port A, the port B Full/Input
Ready flag (
FFB/IRB) is set HIGH, and both FIFOs begin normal operation.
See Figure 3 for relevant offset register parallel programming timing diagram.
FIFO WRITE/READ OPERATION
The state of the port A data (A0-A35) outputs is controlled by port A Chip
Select (
CSA) and port A Write/Read select (W/RA). The A0-A35 outputs are
in the high-impedance state when either
CSA or W/RA is HIGH. The A0-A35
outputs are active when both
CSA and W/RA are LOW.
Data is loaded into FIFO1 from the A0-A35 inputs on a LOW-to-HIGH
transition of CLKA when
CSA is LOW, W/RA is HIGH, ENA is HIGH , MBA is
LOW, and
FFA/IRA is HIGH. Data is read from FIFO2 to the A0-A35 outputs
by a LOW-to-HIGH transition of CLKA when
CSA is LOW, W/RA is LOW, ENA
is HIGH, MBA is LOW, and
EFA/ORA is HIGH (see Table 2). FIFO reads and
writes on port A are independent of any concurrent port B operation. Write and
Read cycle timing diagrams for Port A can be found in Figure 4 and 7.
The port B control signals are identical to those of port A with the exception
that the port B Write/Read select (
W/RB) is the inverse of the port A Write/Read
select (W/
RA). The state of the port B data (B0-B35) outputs is controlled by the
port B Chip Select (
CSB) and port B Write/Read select (W/RB). The B0-B35
outputs are in the high-impedance state when either
CSB is HIGH or W/RB is
LOW. The B0-B35 outputs are active when
CSB is LOW and W/RB is HIGH.
Data is loaded into FIFO2 from the B0-B35 inputs on a LOW-to-HIGH
transition of CLKB when
CSB is LOW, W/RB is LOW, ENB is HIGH, MBB is
LOW, and
FFB/IRB is HIGH. Data is read from FIFO1 to the B0-B35 outputs
by a LOW-to-HIGH transition of CLKB when
CSB is LOW, W/RB is HIGH, ENB
is HIGH, MBB is LOW, and
EFB/ORB is HIGH (see Table 3). FIFO reads and
writes on port B are independent of any concurrent port A operation. Write and
Read cycle timing diagrams for Port B can be found in Figure 5 and 6.
The setup and hold time constraints to the port Clocks for the port Chip
Selects and Write/Read selects are only for enabling write and read operations
and are not related to high-impedance control of the data outputs. If a port enable
is LOW during a clock cycle, the port's Chip Select and Write/Read select may
change states during the setup and hold time window of the cycle.
When operating the FIFO in FWFT mode and the Output Ready flag is LOW,
the next word written is automatically sent to the FIFO's output register by the
LOW-to-HIGH transition of the port clock that sets the Output Ready flag HIGH.
When the Output Ready flag is HIGH, subsequent data is clocked to the output
registers only when a read is selected using the port's Chip Select, Write/Read
select, Enable, and Mailbox select.
When operating the FIFO in IDT Standard mode, the first word will cause
the Empty Flag to change state on the second LOW-to-HIGH transition of the
Read Clock. The data word will not be automatically sent to the output register.
Instead, data residing in the FIFO's memory array is clocked to the output
register only when a read is selected using the port's Chip Select, Write/Read
select, Enable, and Mailbox select.
CSB
W/RB
ENB
MBB
CLKB
Data B (B0-B35) I/O
Port Function
H
X
X
X
X
High-Impedance
None
L
L
L
X
X
Input
None
L
L
H
L
Input
FIFO2 write
L
L
H
H
Input
Mail2 write
L
H
L
L
X
Output
None
L
H
H
L
Output
FIFO1 read
L
H
L
H
X
Output
None
L
H
H
H
Output
Mail1 read (set
MBF1 HIGH)
TABLE 3
PORT B ENABLE .UNCTION TABLE
TABLE 2
PORT A ENABLE .UNCTION TABLE
CSA
W/
RA
ENA
MBA
CLKA
Data A (A0-A35) I/O
Port Function
H
X
X
X
X
High-Impedance
None
L
H
L
X
X
Input
None
L
H
H
L
Input
FIFO1 write
L
H
H
H
Input
Mail1 write
L
L
L
L
X
Output
None
L
L
H
L
Output
FIFO2 read
L
L
L
H
X
Output
None
L
L
H
H
Output
Mail2 read (set
MBF2 HIGH)
12
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
a write pointer and read pointer comparator that indicates when the FIFO
memory status is empty, empty+1, or empty+2.
In FWFT mode, from the time a word is written to a FIFO, it can be shifted
to the FIFO output register in a minimum of three cycles of the Output Ready
flag synchronizing clock. Therefore, an Output Ready flag is LOW if a word
in memory is the next data to be sent to the FlFO output register and three cycles
of the port Clock that reads data from the FIFO have not elapsed since the time
the word was written. The Output Ready flag of the FIFO remains LOW until
the third LOW-to-HIGH transition of the synchronizing clock occurs, simulta-
neously forcing the Output Ready flag HIGH and shifting the word to the FIFO
output register.
In IDT Standard mode, from the time a word is written to a FIFO, the Empty
Flag will indicate the presence of data available for reading in a minimum of two
cycles of the Empty Flag synchronizing clock. Therefore, an Empty Flag is LOW
if a word in memory is the next data to be sent to the FlFO output register and
two cycles of the port Clock that reads data from the FIFO have not elapsed
since the time the word was written. The Empty Flag of the FIFO remains LOW
until the second LOW-to-HIGH transition of the synchronizing clock occurs,
forcing the Empty Flag HIGH; only then can data be read.
A LOW-to-HIGH transition on an Empty/Output Ready flag synchronizing
clock begins the first synchronization cycle of a write if the clock transition occurs
at time t
SKEW1
or greater after the write. Otherwise, the subsequent clock cycle
Synchronized
Synchronized
Number of Words in FIFO
(1,2)
to CLKB
to CLKA
IDT723652
(3)
IDT723662
(3)
IDT723672
(3)
EFB/ORB
AEB
AFA
FFA/IRA
0
0
0
L
L
H
H
1 to X1
1 to X1
1 to X1
H
L
H
H
(X1+1) to [2,048-(Y1+1)]
(X1+1) to [4,096-(Y1+1)]
(X1+1) to [8,192-(Y1+1)]
H
H
H
H
(2,048-Y1) to 2,047
(4,096-Y1) to 4,095
(8,192-Y1) to 8,191
H
H
L
H
2,048
4,096
8,192
H
H
L
L
SYNCHRONIZED FIFO FLAGS
Each FIFO is synchronized to its port clock through at least two flip-flop
stages. This is done to improve flag signal reliability by reducing the probability
of metastable events when CLKA and CLKB operate asynchronously to one
another.
EFA/ORA, AEA, FFA/IRA, and AFA are synchronized to CLKA. EFB/
ORB,
AEB, FFB/IRB, and AFB are synchronized to CLKB. Tables 4 and 5
show the relationship of each port flag to FIFO1 and FIFO2.
EMPTY/OUTPUT READY FLAGS (
EFA/ORA, EFB/ORB)
These are dual purpose flags. In the FWFT mode, the Output Ready (ORA,
ORB) function is selected. When the Output Ready flag is HIGH, new data is
present in the FIFO output register. When the Output Ready flag is LOW, the
previous data word is present in the FIFO output register and attempted FIFO
reads are ignored.
In the IDT Standard mode, the Empty Flag (
EFA, EFB) function is selected.
When the Empty Flag is HIGH, data is available in the FIFO's RAM for reading
to the output register. When the Empty Flag is LOW, the previous data word
is present in the FIFO output register and attempted FIFO reads are ignored.
The Empty/Output Ready flag of a FIFO is synchronized to the port clock
that reads data from its array. For both the FWFT and IDT Standard modes,
the FIFO read pointer is incremented each time a new word is clocked to its
output register. The state machine that controls an Output Ready flag monitors
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X1 is the Almost-Empty offset for FIFO1 used by
AEB. Y1 is the Almost-Full offset for FIFO1 used by AFA. Both X1 and Y1 are selected during a reset of FIFO1 or programmed from
port A.
4. The ORB and IRA functions are active during FWFT mode; the
EFB and FFA functions are active in IDT Standard mode.
TABLE 4
.I.O1 .LAG OPERATION (IDT STANDARD AND .W.T MODES)
Synchronized
Synchronized
Number of Words in FIFO
(1,2)
to CLKA
to CLKB
IDT723652
(3)
IDT723662
(3)
IDT723672
(3)
EFA/ORA
AEA
AFB
FFB/IRB
0
0
0
L
L
H
H
1 to X2
1 to X2
1 to X2
H
L
H
H
(X2+1) to [2,048-(Y2+1)]
(X2+1) to [4,096-(Y2+1)]
(X2+1) to [8,192-(Y2+1)]
H
H
H
H
(2,048-Y2) to 2,047
(4,096-Y2) to 4,095
(8,192-Y2) to 8,191
H
H
L
H
2,048
4,096
8,192
H
H
L
L
NOTES:
1. When a word loaded to an empty FIFO is shifted to the output register, its previous FIFO memory location is free.
2. Data in the output register does not count as a "word in FIFO memory". Since in FWFT mode, the first word written to an empty FIFO goes unrequested to the output register (no
read operation necessary), it is not included in the FIFO memory count.
3. X2 is the Almost-Empty offset for FIFO2 used by
AEA. Y2 is the Almost-Full offset for FIFO2 used by AFB. Both X2 and Y2 are selected during a reset of FIFO2 or programmed from
port A.
4. The ORA and IRB functions are active during FWFT mode; the
EFA and FFB functions are active in IDT Standard mode.
TABLE 5
.I.O2 .LAG OPERATION (IDT STANDARD AND .W.T MODES)
13
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
ALMOST-FULL FLAGS (
AFA, AFB)
The Almost-Full flag of a FIFO is synchronized to the port clock that writes
data to its array. The state machine that controls an Almost-Full flag monitors a
write pointer and read pointer comparator that indicates when the FIFO memory
status is almost-full, almost-full-1, or almost-full-2. The almost-full state is defined
by the contents of register Y1 for
AFA and register Y2 for AFB. These registers
are loaded with preset values during a FlFO reset or programmed from port
A (see Almost-Empty flag and Almost-Full flag offset programming section).
An Almost-Full flag is LOW when the number of words in its FIFO is greater than
or equal to (2,048-Y), (4,096-Y), or (8,192-Y) for the IDT723652, IDT723662,
or IDT723672 respectively. An Almost-Full flag is HIGH when the number of
words in its FIFO is less than or equal to [2,048-(Y+1)], [4,096-(Y+1)], or [8,192-
(Y+1)] for the IDT723652, IDT723662, or IDT723672 respectively. Note that
a data word present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Full flag synchronizing clock
are required after a FIFO read for its Almost-Full flag to reflect the new level of
fill. Therefore, the Almost-Full flag of a FIFO containing [2,048/4,096/8,192-
(Y+1)] or less words remains LOW if two cycles of its synchronizing clock have
not elapsed since the read that reduced the number of words in memory to
[2,048/4,096/8,192-(Y+1)]. An Almost-Full flag is set HIGH by the second LOW-
to-HIGH transition of its synchronizing clock after the FIFO read that reduces
the number of words in memory to [2,048/4,096/8,192-(Y+1)]. A LOW-to-HIGH
transition of an Almost-Full flag synchronizing clock begins the first synchroni-
zation cycle if it occurs at time t
SKEW2
or greater after the read that reduces the
number of words in memory to [2,048/4,096/8,192-(Y+1)]. Otherwise, the
subsequent synchronizing clock cycle may be the first synchronization cycle
(see Figures 18 and 19).
MAILBOX REGISTERS
Each FIFO has a 36-bit bypass register to pass command and control
information between port A and port B without putting it in queue. The Mailbox
select (MBA, MBB) inputs choose between a mail register and a FIFO for a port
data transfer operation. A LOW-to-HIGH transition on CLKA writes A0-A35 data
to the mail1 register when a port A Write is selected by
CSA, W/RA, and ENA
and with MBA HIGH. A LOW-to-HIGH transition on CLKB writes B0-B35 data
to the mail2 register when a port B Write is selected by
CSB, W/RB, and ENB
and with MBB HIGH. Writing data to a mail register sets its corresponding flag
(
MBF1 or MBF2) LOW. Attempted writes to a mail register are ignored while
the mail flag is LOW.
When data outputs of a port are active, the data on the bus comes from the
FIFO output register when the port Mailbox select input is LOW and from the mail
register when the port mailbox select input is HIGH. The Mail1 Register Flag
(
MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when a port B Read
is selected by
CSB, W/RB, and ENB and with MBB HIGH. The Mail2 Register
Flag (
MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when a port
A read is selected by
CSA, W/RA, and ENA and with MBA HIGH. The data
in a mail register remains intact after it is read and changes only when new data
is written to the register. For mail register and Mail Register Flag timing diagrams,
see Figure 20 and 21.
can be the first synchronization cycle (see Figures 8 through 11 for
EFA/ORA
and
EFB/ORB timing diagrams).
FULL/INPUT READY FLAGS (
FFA/IRA, FFB/IRB)
This is a dual purpose flag. In FWFT mode, the Input Ready (IRA and IRB)
function is selected. In IDT Standard mode, the Full Flag (
FFA and FFB)
function is selected. For both timing modes, when the Full/Input Ready flag is
HIGH, a memory location is free in the FIFO to receive new data. No memory
locations are free when the Full/Input Ready flag is LOW and attempted writes
to the FIFO are ignored.
The Full/Input Ready flag of a FlFO is synchronized to the port clock that
writes data to its array. For both FWFT and IDT Standard modes, each time
a word is written to a FIFO, its write pointer is incremented. The state machine
that controls a Full/Input Ready flag monitors a write pointer and read pointer
comparator that indicates when the FlFO memory status is full, full-1, or full-2.
From the time a word is read from a FIFO, its previous memory location is ready
to be written to in a minimum of two cycles of the Full/Input Ready flag
synchronizing clock. Therefore, a Full/Input Ready flag is LOW if less than two
cycles of the Full/Input Ready flag synchronizing clock have elapsed since the
next memory write location has been read. The second LOW-to-HIGH
transition on the Full/Input Ready flag synchronizing clock after the read sets
the Full/Input Ready flag HIGH.
A LOW-to-HIGH transition on a Full/Input Ready flag synchronizing clock
begins the first synchronization cycle of a read if the clock transition occurs at
time t
SKEW1
or greater after the read. Otherwise, the subsequent clock cycle
can be the first synchronization cycle (see Figures 12 through 15 for
FFA/IRA
and
FFB/IRB timing diagrams).
ALMOST-EMPTY FLAGS (
AEA, AEB)
The Almost-Empty flag of a FIFO is synchronized to the port clock that reads
data from its array. The state machine that controls an Almost-Empty flag monitors
a write pointer and read pointer comparator that indicates when the FIFO
memory status is almost-empty, almost-empty+1, or almost-empty+2. The
almost-empty state is defined by the contents of register X1 for
AEB and register
X2 for
AEA. These registers are loaded with preset values during a FIFO reset
or programmed from port A (see Almost-Empty flag and Almost-Full flag offset
programming
section). An Almost-Empty flag is LOW when its FIFO contains
X or less words and is HIGH when its FIFO contains (X+1) or more words. A
data word present in the FIFO output register has been read from memory.
Two LOW-to-HIGH transitions of the Almost-Empty flag synchronizing
clock are required after a FIFO write for its Almost-Empty flag to reflect the new
level of fill. Therefore, the Almost-Full flag of a FIFO containing (X+1) or more
words remains LOW if two cycles of its synchronizing clock have not elapsed
since the write that filled the memory to the (X+1) level. An Almost-Empty flag
is set HIGH by the second LOW-to-HIGH transition of its synchronizing clock after
the FIFO write that fills memory to the (X+1) level. A LOW-to-HIGH transition
of an Almost-Empty flag synchronizing clock begins the first synchronization
cycle if it occurs at time t
SKEW2
or greater after the write that fills the FIFO to (X+1)
words. Otherwise, the subsequent synchronizing clock cycle may be the first
synchronization cycle. (See Figures 16 and 17).
14
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTES:
1. FIFO2 is reset in the same manner to load X2 and Y2 with a preset value.
2. If
FWFT is HIGH, then EFB/ORB will go LOW one CLKB cycle earlier than in this case where FWFT is LOW.
Figure 2. FIFO1 Reset and Loading X1 and Y1 with a Preset Value of Eight
(1)
(IDT Standard and FWFT Modes)
NOTES:
1. t
SKEW1
is the minimum time between the rising CLKA edge and a rising CLKB edge for
FFB/IRB to transition HIGH in the next cycle. If the time between the rising edge of CLKA and rising
edge of CLKB is less than t
SKEW1
, then
FFB/IRB may transition HIGH one CLKB cycle later than shown.
2.
CSA = LOW, W/RA = HIGH, MBA = LOW. It is not necessary to program offset register on consecutive clock cycles.
Figure 3. Parallel Programming of the Almost-Full Flag and Almost-Empty Flag Offset Values after Reset (IDT Standard and FWFT Modes)
CLKA
RST1
FFA
/IRA
AEB
AFA
MBF1
CLKB
EFB
/ORB
FS1,FS0
5609 drw 04
t
RSTS
t
RSTH
t
FSH
t
FSS
t
PIR
t
PIR
t
POR
t
PRF
0,1
t
PRF
t
PRF
t
FWS
FWFT
5609 drw 05
CLKA
RST1
,
RST2
FFA
/IRA
CLKB
FFB
/IRB
A0 - A35
FS1,FS0
ENA
t
FSS
t
FSH
t
PIR
t
ENH
t
ENS2
t
SKEW1
t
DS
t
DH
t
PIR
4
0,0
AFA
Offset
(Y1)
AEB
Offset
(X1)
AFB
Offset
(Y2)
AEA
Offset
(X2)
First Word to FIFO1
1
2
(1)
1
2
15
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Figure 5. Port B Write Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. Written to FIFO1.
Figure 4. Port A Write Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
NOTE:
1. Written to FIFO2.
5609 drw 06
CLKA
FFA
/IRA
ENA
A0 - A35
MBA
CSA
W/
R
A
t
CLKH
t
CLKL
t
CLK
t
ENS1
t
ENS1
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
ENS2
t
ENH
t
ENH
t
ENS2
No Operation
HIGH
t
ENS2
5609 drw 07
CLKB
FFB
/IRB
ENB
B0 - B35
MBB
CSB
W
/RB
t
CLK
t
CLKH
t
CLKL
t
ENH
t
ENH
t
ENH
t
ENH
t
DH
W1
(1)
W2
(1)
t
DS
t
ENH
t
ENH
No Operation
HIGH
t
ENS1
t
ENS1
t
ENS2
t
ENS2
t
ENS2
16
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. Read From FIFO1.
Figure 6. Port B Read Cycle Timing for FIFO1 (IDT Standard and FWFT Modes)
Figure 7. Port A Read Cycle Timing for FIFO2 (IDT Standard and FWFT Modes)
NOTE:
1. Read From FIFO2.
5609 drw 08
CLKB
EFB
/ORB
ENB
MBB
CSB
W
/RB
t
CLK
t
CLKH
t
CLKL
t
A
t
MDV
t
EN
t
A
t
ENH
t
ENH
Previous Data
W1
W2
(1)
(1)
t
ENH
t
DIS
No Operation
HIGH
t
A
t
MDV
t
EN
t
A
W1
W2
W3
(1)
(1)
(1)
t
DIS
B0-B35
(FWFT Mode)
B0-B35
(IDT Standard Mode)
OR
t
ENS2
t
ENS2
t
ENS2
CLKA
EFA
/ORA
ENA
MBA
CSA
W/
R
A
t
CLK
t
CLKH
t
CLKL
t
ENH
t
ENH
t
ENH
No Operation
t
A
t
EN
t
A
W1
W2
W3
(1)
(1)
(1)
t
DIS
A0-A35
(FWFT Mode)
t
EN
W2
(1)
(1)
t
DIS
W1
Previous Data
A0-A35
(Standard Mode)
t
MDV
t
A
OR
t
A
t
MDV
5609 drw 09
HIGH
t
ENS2
t
ENS2
t
ENS2
17
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for ORB to transition HIGH and to clock the next word to the FIFO1 output register in three CLKB cycles.
If the time between the rising CLKA edge and rising CLKB edge is less than t
SKEW1
, then the transition of ORB HIGH and load of the first word to the output register may occur one CLKB
cycle later than shown.
Figure 8. ORB Flag Timing and First Data Word Fall Through when FIFO1 is Empty (FWFT Mode)
CSA
W
R
A
MBA
IRA
A0 - A35
CLKB
ORB
CSB
W
/RB
MBB
ENA
ENB
B0 -B35
CLKA
5609 drw 10
1
2
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO1 Output Register
W1
FIFO1Empty
LOW
HIGH
LOW
HIGH
LOW
t
CLKH
W1
HIGH
(1)
18
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for
EFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW1
, then the transition of
EFB HIGH may occur one CLKB cycle later than shown.
Figure 9.
EFB
Flag Timing and First Data Read Fall Through when FIFO1 is Empty (IDT Standard Mode)
CSA
W
R
A
MBA
FFA
A0-A35
CLKB
EFB
CSB
W
/RB
MBB
ENA
ENB
B0-B35
CLKA
1
2
5609 drw11
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKL
t
ENS2
t
ENH
t
A
W1
FIFO1 Empty
LOW
HIGH
LOW
HIGH
LOW
t
CLKH
W1
HIGH
(1)
t
POR
t
POR
19
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for ORA to transition HIGH and to clock the next word to the FIFO2 output register in three CLKA cycles.
If the time between the rising CLKB edge and rising CLKA edge is less than t
SKEW1
, then the transition of ORA HIGH and load of the first word to the output register may occur one CLKA
cycle later than shown.
Figure 10. ORA Flag Timing and First Data Word Fall Through when FIFO2 is Empty (FWFT Mode)
CSB
W
/RB
MBB
IRB
B0 - B35
CLKA
ORA
CSA
W/
R
A
MBA
ENB
ENA
A0 -A35
CLKB
5609 drw 12
1
2
3
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
t
CLK
t
CLKH
t
POR
t
POR
t
ENS2
t
ENH
t
A
Old Data in FIFO2 Output Register
W1
FIFO2 Empty
t
CLKL
LOW
LOW
LOW
LOW
LOW
HIGH
W1
(1)
20
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for
EFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW1
, then the transition of
EFA HIGH may occur one CLKA cycle later than shown.
Figure 11.
EFA
Flag Timing and First Data Read when FIFO2 is Empty (IDT Standard Mode)
CSB
W
/RB
MBB
FFB
B0-B35
CLKA
EFA
CSA
W/
R
A
MBA
ENB
ENA
A0-A35
CLKB
1
2
5609 drw13
t
CLKH
t
CLKL
t
CLK
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
t
SKEW1
(1)
t
CLK
t
CLKL
t
ENS2
t
ENH
t
A
W1
FIFO2 Empty
LOW
LOW
LOW
LOW
LOW
t
CLKH
W1
HIGH
t
POR
t
POR
21
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for IRA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW1
, then IRA may transition HIGH one CLKA cycle later than shown.
Figure 12. IRA Flag Timing and First Available Write when FIFO1 is Full (FWFT Mode)
CSB
ORB
W
/RB
MBB
ENB
B0 -B35
CLKB
IRA
CLKA
CSA
5609 drw 14
W/
R
A
A0 - A35
MBA
ENA
1
2
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
PIR
t
PIR
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
Write
22
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Figure 13.
FFA
Flag Timing and First Available Write when FIFO1 is Full (IDT Standard Mode)
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKB edge and a rising CLKA edge for
FFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW1
, then
FFA may transition HIGH one CLKA cycle later than shown.
CSB
EFB
MBB
ENB
B0-B35
CLKB
FFA
CLKA
CSA
5609 drw15
W/
R
A
1
2
A0-A35
MBA
ENA
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO1
Previous Word in FIFO1 Output Register
Next Word From FIFO1
LOW
W
/RB
HIGH
LOW
HIGH
LOW
HIGH
(1)
FIFO1 Full
t
PIR
t
PIR
Write
23
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for IRB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW1
, then IRB may transition HIGH one CLKB cycle later than shown.
Figure 14. IRB Flag Timing and First Available Write when FIFO2 is Full (FWFT Mode)
CSA
ORA
W/
R
A
MBA
ENA
A0 -A35
CLKA
IRB
CLKB
CSB
5609 drw 16
W
/RB
B0 - B35
MBB
ENB
1
2
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
PIR
t
ENS2
t
ENS2
t
ENH
t
ENH
t
DS
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
FIFO2 FULL
LOW
LOW
LOW
HIGH
LOW
LOW
(1)
Write
t
PIR
24
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Figure 16. Timing for
AEB
when FIFO1 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AEB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW2
, then
AEB may transition HIGH one CLKB cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = LOW, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
Figure 15.
FFB
Flag Timing and First Available Write when FIFO2 is Full (IDT Standard Mode)
NOTE:
1. t
SKEW1
is the minimum time between a rising CLKA edge and a rising CLKB edge for
FFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW1
, then
FFB may transition HIGH one CLKB cycle later than shown.
CSA
EFA
MBA
ENA
A0-A35
CLKA
FFB
CLKB
CSB
5609 drw17
W
/RB
1
2
B0-B35
MBB
ENB
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENH
t
A
t
SKEW1
t
CLK
t
CLKH
t
CLKL
t
ENS2
t
ENS2
t
DS
t
ENH
t
ENH
t
DH
To FIFO2
Previous Word in FIFO2 Output Register
Next Word From FIFO2
LOW
W/
R
A LOW
LOW
HIGH
LOW
LOW
(1)
FIFO2 Full
t
PIR
t
PIR
Write
AEB
CLKA
ENB
5609 drw 18
ENA
CLKB
2
1
t
ENS2
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
X1 Words in FIFO1
(X1+1) Words in FIFO1
(1)
25
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AEA to transition HIGH in the next CLKA cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW2
, then
AEA may transition HIGH one CLKA cycle later than shown.
2. FIFO2 Write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
Figure 17. Timing for
AEA
when FIFO2 is Almost-Empty (IDT Standard and FWFT Modes)
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKA edge and a rising CLKB edge for
AFA to transition HIGH in the next CLKA cycle. If the time between the rising CLKA edge and rising
CLKB edge is less than t
SKEW2
, then
AFA may transition HIGH one CLKA cycle later than shown.
2. FIFO1 Write (
CSA = LOW, W/RA = HIGH, MBA = LOW), FIFO1 read (CSB = LOW, W/RB = HIGH, MBB = LOW). Data in the FIFO1 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723652, 4,096 for the IDT723662, 8,192 for the IDT723672.
Figure 18. Timing for
AFA
when FIFO1 is Almost-Full (IDT Standard and FWFT Modes)
AEA
CLKB
ENA
5609 drw 19
ENB
CLKA
2
1
t
ENS2
t
ENH
t
SKEW2
t
PAE
t
PAE
t
ENS2
t
ENH
(X2+1) Words in FIFO2
X2 Words in FIFO2
(1)
AFA
CLKA
ENB
5609 drw 20
ENA
CLKB
1
2
t
SKEW2
t
ENS2
t
ENH
t
PAF
t
ENS2
t
ENH
t
PAF
[D-(Y1+1)] Words in FIFO1
(D-Y1) Words in FIFO1
(1)
26
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
NOTES:
1. t
SKEW2
is the minimum time between a rising CLKB edge and a rising CLKA edge for
AFB to transition HIGH in the next CLKB cycle. If the time between the rising CLKB edge and rising
CLKA edge is less than t
SKEW2
, then
AFB may transition HIGH one CLKB cycle later than shown.
2. FIFO2 write (
CSB = LOW, W/RB = LOW, MBB = LOW), FIFO2 read (CSA = LOW, W/RA = LOW, MBA = LOW). Data in the FIFO2 output register has been read from the FIFO.
3. D = Maximum FIFO Depth = 2,048 for the IDT723652, 4,096 for the IDT723662, 8,192 for the IDT723672.
Figure 19. Timing for
AFB
when FIFO2 is Almost-Full (IDT Standard and FWFT Modes)
Figure 20. Timing for Mail1 Register and
MBF1
Flag (IDT Standard and FWFT Modes)
AFB
CLKB
ENA
5609 drw 21
ENB
CLKA
1
2
t
SKEW2
t
ENS2
t
ENH
t
PAF
t
ENS2
t
ENH
t
PAF
[D-(Y2+1)] Words in FIFO2
(D-Y2) Words in FIFO2
(1)
5609 drw 22
CLKA
ENA
A0 - A35
MBA
CSA
W/
R
A
CLKB
MBF1
CSB
MBB
ENB
B0 - B35
W
/RB
W1
t
ENS1
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
EN
t
MDV
t
PMR
t
ENH
t
DIS
W1 (Remains valid in Mail1 Register after read)
FIFO1 Output Register
t
ENS1
t
ENS2
t
ENS2
t
ENH
t
ENH
t
ENH
t
ENS2
27
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Figure 21. Timing for Mail2 Register and
MBF2
Flag (IDT Standard and FWFT Modes)
5609 drw 23
CLKB
ENB
B0 - B35
MBB
CSB
W
/RB
CLKA
MBF2
CSA
MBA
ENA
A0 - A35
W/
R
A
W1
t
ENS1
t
ENH
t
DS
t
DH
t
PMF
t
PMF
t
ENH
t
DIS
t
EN
t
MDV
t
PMR
FIFO2 Output Register
W1 (Remains valid in Mail 2 Register after read)
t
ENS1
t
ENH
t
ENS2
t
ENH
t
ENS2
t
ENH
t
ENS2
28
COMMERCIAL TEMPERATURE RANGE
IDT723652/723662/723672 CMOS SyncBiFIFO
TM
2,048 x 36 x 2, 4,096 x 36 x 2, 8,192 x 36 x 2
Figure 22. Load Circuit and Voltage Waveforms
NOTE:
1. Includes probe and jig capacitance.
5609 drw 24
PARAMETER MEASUREMENT INFORMATION
From Output
Under Test
30 pF
1.1K
5.0V
680
PROPAGATION DELAY
LOAD CIRCUIT
3V
GND
Timing
Input
Data,
Enable
Input
GND
3V
1.5V
1.5V
VOLTAGE WAVEFORMS
SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS
PULSE DURATIONS
VOLTAGE WAVEFORMS
ENABLE AND DISABLE TIMES
VOLTAGE WAVEFORMS
PROPAGATION DELAY TIMES
1.5V
1.5V
1.5V
1.5V
t
W
Output
Enable
Low-Level
Output
High-Level
Output
3V
OL
GND
3V
1.5V
1.5V
1.5V
1.5V
OH
OV
GND
OH
OL
1.5V
1.5V
1.5V
1.5V
Input
In-Phase
Output
High-Level
Input
Low-Level
Input
V
V
V
V
1.5V
3V
t
S
t
h
t
PLZ
t
PHZ
t
PZL
t
PZH
t
PD
t
PD
(1)
3V
GND
GND
3V
29
CORPORATE HEADQUARTERS
for SALES:
for TECH SUPPORT:
2975 Stender Way
800-345-7015 or 408-727-6116
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
FIFOhelp@idt.com
www.idt.com
ORDERING IN.ORMATION
5609 drw 25
Commercial (0
C to +70
C)
Thin Quad Flat Pack (TQFP, PN120-1)
Plastic Quad Flat Pack (PQFP, PQ132-1)
Low Power
2,048 x 36 x 2
SyncBiFIFO
4,096 x 36 x 2
SyncBiFIFO
8,192 x 36 x 2
SyncBiFIFO
XXXXXX
IDT
Device Type
X
XX
X
X
Power
Speed
Package
Process/
Temperature
Range
Commercial Only
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
BLANK
PF
PQF
12
15
L
723652
723662
723672
NOTE:
1. Industrial temperature range is available by special order.
DATASHEET DOCUMENT HISTORY
12/19/2000
pg. 11.
03/21/2001
pgs. 6 and 7.
08/01/2001
pgs. 6, 8, 9 and 29.