Integrated Device Technology, Inc.

MILITARY AND COMMERCIAL TEMPERATURE RANGES

MAY 1998

DSC-2747/7

FEATURES:

· First-ln/First-Out Dual-Port memory
· 64 x 4 organization (IDT72401/72403)
· 64 x 5 organization (IDT72402/72404)
· RAM-based FIFO with low falI-through time
· Low-power consumption

-- Active: 175mW (typ.)

· Maximum shift rate -- 45MHz
· High data output drive capability
· Asynchronous and simultaneous read and write
· Fully expandable by bit width
· Fully expandable by word depth
· IDT72403/72404 have Output Enable pin to enable

output data

· High-speed data communications applications
· High-performance CMOS technology
· Available in CERDIP, plastic DIP and SOIC
· Military product compliant to MlL-STD-883, Class B
· Standard Military Drawing #5962-86846 and

5962-89523 is listed on this function.

· Industrial temperature range (40

C to +85

C) is avail-

able (plastic packages only)

64 words by 5 bits. The IDT72403 and IDT72404 also have an
Output Enable (

) pin. The FlFOs accept 4-bit or 5-bit data

at the data input (D

0-D3, 4

). The stored data stack up on a first-

in/first-out basis.

A Shift Out (SO) signal causes the data at the next to last

word to be shifted to the output while all other data shifts down
one location in the stack. The Input Ready (IR) signal acts like
a flag to indicate when the input is ready for new data
(IR = HIGH) or to signal when the FIFO is full (IR = LOW). The
IR signal can also be used to cascade multiple devices
together. The Output Ready (OR) signal is a flag to indicate
that the output remains valid data (OR = HIGH) or to indicate
that the FIFO is empty (OR = LOW). The OR can also be used
to cascade multiple devices together.

Width expansion is accomplished by logically ANDing the

IR and OR signals to form composite signals.

Depth expansion is accomplished by tying the data inputs

of one device to the data outputs of the previous device. The
IR pin of the receiving device is connected to the SO pin of the
sending device and the OR pin of the sending device is
connected to the Shift In (SI) pin of the receiving device.

Reading and writing operations are completely asynchro-

nous allowing the FIFO to be used as a buffer between two
digital machines of widely varying operating frequencies. The
45MHz speed makes these FlFOs ideal for high-speed com-
munication and controller applications.

Military grade product is manufactured in compliance with

the latest revision of MIL-STD-883, Class B.

IDT72401
IDT72402
IDT72403
IDT72404

CMOS PARALLEL FIFO
64 x 4 and 64 x 5

The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FAST is a trademark of National Semiconductor, Inc.

FUNCTIONAL BLOCK DIAGRAM

0-3

2747 drw 01

INPUT

CONTROL

LOGIC

DATA

MASTER

RESET

WRITE POINTER

WRITE MULTIPLEXER

MEMORY

ARRAY

READ MULTIPLEXER

READ POINTER

OUTPUT

ENABLE

DATA

OUTPUT

CONTROL

LOGIC

OUT

(IDT72402

and IDT72404)

OE (IDT72403 and
IDT72404)

0-3

(IDT72402 and
IDT72404)

DESCRIPTION:

The IDT72401 and IDT72403 are asynchronous high-

performance First-ln/First-Out memories organized 64 words
by 4 bits. The IDT72402 and IDT72404 are asynchronous
high-performance First-ln/First-Out memories organized as

For latest information contact IDT's web site at www.idt.com or fax-on-demand at 408-492-8391.

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

PIN CONFIGURATIONS

NOTES:
1. Pin 1: NC - No Connection IDT72401,

- IDT72403

2. Pin 1: NC - No Connection IDT72402,

- IDT72404

IDT72401/IDT72403

PLASTIC DIP (P18-1, order code: P)

CERDIP (D18-1, order code: D)

SOIC (SO18-1, order code: SO)

TOP VIEW

IDT72402/IDT72404

NC/OE

Vcc

GND

(1)

2747 drw 02

NC/OE

Vcc

GND

(2)

2747 drw 03

PLASTIC DIP (P16-1, order code: P)

CERDIP (D16-1, order code: D)

SOIC (SO16-1, order code: SO)

TOP VIEW

ABSOLUTE MAXIMUM RATINGS

(1)

Symbol

Rating

Commercial

Military

Unit

TERM

Terminal Voltage

0.5 to +7.0

with Respect
to GND

STG

Storage Temp.

55 to +125

65 to +150

OUT

DC Output

50 to +50

Current

NOTE:

2747 tbl 01

1. Stresses greater than those listed under ABSOLUTE MAXIMUM

RATINGS may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other
conditions above those indicated in the operational sections of this
specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.

RECOMMENDED OPERATING CONDITIONS

Symbol

Parameter

Min.

Typ. Max. Unit

Supply Voltage

4.5

5.0

5.5

Commercial/Military

GND

Supply Voltage

Input High Voltage

2.0

(1)

Input High Voltage

0.8

Operating Temperature

Commercial

Operating Temperature

125

Military

NOTE:

2747 tbl 02

1. 1.5V undershoots are allowed for 10ns once per cycle.

DC ELECTRICAL CHARACTERISTICS

(Commercial: V

= 5.0V

10%, T

= 0

C to +70

C; Military: V

= 5.0V

10%, T

= 55

C to +125

IDT72401

IDT72402

IDT72403

IDT72404

Commercial

Military

= 45,35,25,15,10 MHz

= 35,25,15,10 MHz

Symbol

Parameter

Test Conditions

Min.

Max.

Min.

Max.

Unit

Low-Level Input Current

= Max., GND

High-Level Input Current

= Max., GND

Low-Level Output Voltage

= Min., I

= 8mA

0.4

High-Level Output Voltage

= Min., I

= -4mA

2.4

(1)

Output Short-Circuit Current

= Max., V

= GND

110

(2)

HIGH Impedance Output Current V

= Max., V

= 2.4V

(2)

LOW Impedance Output Current

= Max., V

= 0.4V

(3,4)

Active Supply Current

= Max., f = 10MHz

NOTES:

2747 tbl 04

1. Not more than one output should be shorted at a time and duration of the short-circuit should not exceed one second. Guaranteed but not tested.
2. IDT72403 and IDT72404 only.
3. Tested with outputs open (I

OUT

= 0).

is HIGH for IDT72403/72404.

4. For frequencies greater than 10MHz, I

= 35mA + (1.5mA x [f - 10MHz]) commercial, and I

= 45mA + (1.5mA x [f - 10MHz]) military.

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

OPERATING CONDITIONS

(Commercial: V

= 5.0V

10%, T

= 0

C to +70

C; Military: V

= 5.0V

10%, T

= 55

C to +125

Commercial

Commercial and Military

IDT72401L45

IDT72401L35

IDT72401L25

IDT72401L15

IDT72401L10

IDT72402L45

IDT72402L35

IDT72402L25

IDT72402L15

IDT72402L10

IDT72403L45

IDT72403L35

IDT72403L25

IDT72403L15

IDT72403L10

IDT72404L45

IDT72404L35

IDT72404L25

IDT72404L15

IDT72404L10

Symbol

Parameter

Figure

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

SIH

(1)

Shift in HIGH Time

SIL

Shift in LOW TIme

IDS

Input Data Set-up

IDH

Input Data Hold Time

SOH

(1)

Shift Out HIGH Time

SOL

Shift Out LOW Time

MRW

Master Reset Pulse

MRS

Master Reset Pulse to SI

SIR

Data Set-up to IR

HIR

Data Hold from IR

SOR

(4)

Data Set-up to OR HIGH

2747 tbl 05

AC ELECTRICAL CHARACTERISTICS

(Commercial: V

= 5.0V

10%, T

= 0

C to +70

C; Military: V

= 5.0V

10%, T

= 55

C to +125

Commercial

Commercial and Military

IDT72401L45

IDT72401L35

IDT72401L25

IDT72401L15

IDT72401L10

IDT72402L45

IDT72402L35

IDT72402L25

IDT72402L15

IDT72402L10

IDT72403L45

IDT72403L35

IDT72403L25

IDT72403L15

IDT72403L10

IDT72404L45

IDT72404L35

IDT72404L25

IDT72404L15

IDT72404L10

Symbol

Parameter

Figure

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Min.

Max.

Unit

Shift In Rate

MHz

IRL

(1)

Shift In to Input Ready LOW

IRH

(1)

Shift In to Input Ready HIGH

OUT

Shift Out Rate

MHz

ORL

(1)

Shift Out to Output Ready LOW

ORH

(1)

Shift Out to Output Ready HIGH

ODH

Output Data Hold (Previous Word)

ODS

Output Data Shift (Next Word)

Data Throughput or "Fall-Through"

4, 7

MRORL

Master Reset to OR LOW

MRIRH

Master Reset to IR HIGH

MRQ

Master Reset to Data Output LOW

OOE

(3)

Output Valid from

LOW

HZOE

(3,4)

Output High-Z from

HIGH

IPH

(2,4)

Input Ready Pulse HIGH

OPH

(2,4)

Output Ready Pulse HIGH

NOTES:

2747 tbl 06

1. Since the FIFO is a very high-speed device, care must be excercised in the design of the hardware and timing utilized within the design. Device grounding

and decoupling are crucial to correct operation as the FIFO will respond to very small glitches due to long reflective lines, high capacitances and/or poor
supply decoupling and grounding. A monolithic ceramic capacitor of 0.1

F directly between V

and GND with very short lead length is recommended.

2. This parameter applies to FIFOs communicating with each other in a cascaded mode. IDT FIFOs are guaranteed to cascade with other IDT FIFOs of

like speed grades.

3. IDT72403 and IDT72404 only.
4. Guaranteed by design but not currently tested.

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

560

30pF*

1.1K

OUTPUT

2747 drw 05

AC TEST CONDITIONS

Input Pulse Levels

GND to 3.0V

Input Rise/Fall Times

3ns

Input Timing Reference Levels

1.5V

Output Reference Levels

1.5V

Output Load

See Figure 1

2747 tbl 07

ALL INPUT PULSES:

SIGNAL DESCRIPTIONS

INPUTS:

DATA INPUT (D

0-3

)

Data input lines. The IDT72401 and IDT72403 have a 4-bit

data input. The IDT72402 and IDT72404 have a 5-bit data input.

CONTROLS:

SHIFT IN (SI)

Shift In controls the input of the data into the FIFO. When

SI is HIGH, data can be written to the FIFO via the D

0-3, 4

lines.

SHIFT OUT (SO)

Shift Out controls the output of data of the FIFO. When SO

is HIGH, data can be read from the FIFO via the Data Output
(Q

0-3, 4

) lines.

MASTER RESET (

)

Master Reset clears the FIFO of any data stored within.

Upon power up, the FIFO should be cleared with a

is active LOW.

INPUT READY (IR)

When Input Ready is HIGH, the FIFO is ready for new input

data to be written to it. When IR is LOW the FIFO is unavailable
for new input data. IR is also used to cascade many FlFOs
together, as shown in Figures 10 and 11.

OUTPUT READY (OR)

When Output Ready is HIGH, the output (Q

0-3, 4

) contains

valid data. When OR is LOW, the FIFO is unavailable for new
output data. OR is also used to cascade many FlFOs together,
as shown in Figures 10 and 11.

OUTPUT ENABLE (

) (IDT72403 AND IDT72404 ONLY)

Output enable is used to read FIFO data onto a bus.

active LOW.

OUTPUTS:

DATA OUTPUT (Q

0-3

)

Data Output lines. The IDT72401 and IDT72403 have a 4-

bit data output. The IDT72402 and IDT72404 have a 5-bit data
output.

or equivalent circuit

Figure 1. AC Test Load

*Including scope and jig

CAPACITANCE

= +25

C, f = 1.0MHz)

Symbol

Parameter

Conditions

Max.

Unit

Input Capacitance

= 0V

OUT

Output Capacitance

OUT

= 0V

NOTE:

2747 tbl 03

1. Characterized values, not currently tested.

2747 drw 04

GND

3.0V

90%

10%

90%

10%

<3ns

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

FUNCTIONAL DESCRIPTION

These 64 x 4 and 64 x 5 FIFOs are designed using a dual

port RAM architecture as opposed to the traditional shift
register approach. This FIFO architecture has a write pointer,
a read pointer and control logic, which allow simultaneous
read and write operations. The write pointer is incremented by
the falling edge of the Shift In (Sl) control; the read pointer is
incremented by the falling edge of the Shift Out (SO). The
Input Ready (IR) signals when the FIFO has an available
memory location; Output Ready (OR) signals when there is
valid data on the output. Output Enable (

) provides the

capability of three-stating the FIFO outputs.

FIFO RESET

The FIFO must be reset upon power up using the Master

Reset (

) signal. This causes the FlFO to enter an empty state,

signified by Output Ready (OR) being LOW and Input Ready (IR)
being HIGH. In this state, the data outputs (Q

0-3, 4

) will be LOW.

DATA INPUT

Data is shifted in on the LOW-to-HlGH transition of Shift In (Sl).

This loads input data into the first word location of the FIFO and
causes Input Ready (IR) to go LOW. On the HlGH-to-LOW transi-
tion of SI, the write pointer is moved to the next word position and
IR goes HIGH, indicating the readiness to accept new data. If the
FIFO is full, IR will remain LOW until a word of data is shifted out.

DATA OUTPUT

Data is shifted out on the HlGH-to-LOW transition of Shift

Out (SO). This causes the internal read pointer to be
advanced to the next word location. If data is present, valid
data will appear on the outputs and Output Ready (OR) will
go HIGH. If data is not present, OR will stay LOW indicating
the FIFO is empty. The last valid word read from the FIFO will
remain at the FlFOs output when it is empty. When the FIFO
is not empty, OR goes LOW on the LOW-to-HIGH transition of
SO. Previous data remains on the output until the HIGH-to-
LOW transition of SO).

FALL THROUGH MODE

The FIFO operates in a fall-through mode when data gets

shifted into an empty FIFO. After a fall-through delay the data
propagates to the output. When the data reaches the output,
the Output Ready (OR) goes HIGH. Fall-through mode also
occurs when the FIFO is completely full. When data is shifted
out of the full FIFO, a location is available for new data. After
a fall-through delay, the Input Ready (IR) goes HIGH. If Shift
In (SI) is HIGH, the new data can be written to the FIFO.

Since these FlFOs are based on an internal dual-port RAM

architecture with separate read and write pointers, the fall-
through time (t

) is one cycle long. A word may be written into

the FIFO on a clock cycle and can be accessed on the next
clock cycle.

Figure 3. The Mechanism of Shifting Data Into the FIFO

NOTES:
1. IR HIGH indicates space is available and a SI pulse may be applied.
2. Input Data is loaded into the first word.
3. IR goes LOW indicating the first word is full.
4. The write pointer is incremented.
5. The FIFO is ready for the next word.
6. If the FIFO is full then the IR remains LOW.
7. SI pulses applied while IR is LOW will be ignored (see Figure 4).

Figure 2. Input Timing

INPUT DATA

IRL

2747 drw 06

1/f

SIH

SIL

IRH

IDH

IDS

INPUT DATA

STABLE DATA

(2)

(3)

(5)

2747 drw 07

(6)

(4)

(1)

(7)

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 6. The Mechanism of Shifting Data Out of the FIFO

NOTES:
1. OR HIGH indicates that data is available and a SO pulse may be applied.
2. SO goes HIGH causing the next step.
3. OR goes LOW.
4. The read pointer is incremented.
5. OR goes HIGH indicating that new data (B) is now available at the FIFO outputs.
6. If the FIFO has only one word loaded (A DATA) then OR stays LOW and the A DATA remains unchanged at the outputs.
7. SO pulses applied when OR is LOW will be ignored.

Figure 5. Output TIming

STABLE DATA

INPUT DATA

(2)

(3)

(1)

IPH

(4)

(5)

2747 drw 08

HIR

SIR

NOTES:
1. FIFO is initially full.
2. SO pulse is applied.
3. SI is held HIGH.
4. As soon as IR becomes HIGH the Input Data is loaded into the FIFO.
5. The write pointer is incremented. SI should not go LOW until (t

+ t

IPH

Figure 4. Data is Shifted In Whenever Shift In and Input Ready are Both HIGH

OUTPUT DATA

A- DATA

(2)

(3)

(5)

2747 drw 10

(6)

(4)

(1)

(7)

A or B

B- DATA

OUTPUT DATA

ORL

2747 drw 09

1/f

OUT

1/f

OUT

SOH

SOL

ODH

ORH

C-DATA

B-DATA

A-DATA

ODS

(2)

(1)

NOTES:
1. This data is loaded consecutively A, B, C.
2. Data is shifted out when SO makes a HIGH to LOW transition.

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

Figure 7. t

and t

OPH

Specification

Figure 8. Master Reset Timing

Figure 9. Output Enable Timing, IDT72403 and IDT72404 Only

NOTE:
1. High-Z transitions are referenced to the steady-state V

-500mV and V

+500mV levels on the output. t

HZOE

is tested with 5pF load capacitance

instead of 30pF as shown in Figure 1.

2747 drw 14

SHIFT IN

INPUT READY

DATA IN

OUTPUT READY

SHIFT OUT

DATA OUT

NOTE:
1. FIFOs can be easily cascaded to any desired path. The handshaking and associated timing between the FIFOs are handled by the inherent timing of

the devices.

Figure 10. 128 x 4 Depth Expansion

(1)

OPH

2747 drw 11

DATA OUTPUT

DATA VALID

SOR

HZOE

2747 drw 13

DATA OUT

OOE

NOTE:
1. FIFO initially empty.

MRW

2747 drw 12

DATA OUTPUT

MRIRH

MRQ

(1)

MRORL

MRS

NOTE:
1. Worst case, FIFO initially full.

IDT72401/72402/72403/72404 CMOS PARALLEL FIFO
64 x 4 and 64 x 5

MILITARY AND COMMERCIAL TEMPERATURE RANGES

NOTES:
1. When the memory is empty, the last word will remain on the outputs until the

is strobed or a new data word falls through to the output. However,

OR will remain LOW, indicating data at the output is not valid.

2. When the output data changes as a result of a pulse on SO, the OR signal always goes LOW before there is any change in output data and stays

LOW until the new data has appeared on the outputs. Anytime OR is HIGH, there is valid stable data on the outputs.

3. If SO is held HIGH while the memory is empty and a word is written into the input, that word will appear at the output after a fall-through time. OR will

go HIGH for one internal cycle (at least t

ORL

) and then go back LOW again. The stored word will remain on the outputs. If more words are written

into the FIFO, they will line up behind the first word and will not appear on the outputs until SO has been brought LOW.

4. When the

is brought LOW, the outputs are cleared to LOW, IR goes HIGH and OR goes LOW. If SI is HIGH when the

goes HIGH, the data

on the inputs will be written into the memory and IR will return to the LOW state until SI is brought LOW. If SI is LOW when the

is ended, IR will

go HIGH, but the data in the inputs will not enter the memory until SI goes HIGH.

5. FIFOs are expandable on depth and width. However, in forming wider words, two external gates are required to generate composite Input and OR

flags. This is due to the variation of delays of the FIFOs.

Figure 11. 192 x 12 Depth and Width Expansion

ORDERING INFORMATION

2747 drw 15

SHIFT OUT

COMPOSITE
OUTPUT
READY

SHIFT IN

COMPOSITE

INPUT

READY

IDT

XXXXX

Device Type

Speed

Power

Package

Process/

Temperature

Range

Blank
B

P
D
SO

72401
72402
72403
72404

45
35
25
15
10

Commercial (0

C to+70

Military (55

C to+125

Compliant to MIL-STD-883, Class B

Plastic DIP
CERDIP
Small Outline IC

Commercial Only
Commercial and Military
Commercial and Military
Commercial and Military
Commercial and Military

Low Power

64 x 4 FIFO
64 x 5 FIFO
64 x 4 FIFO
64 x 5 FIFO

Shift Frequency (fs)
Speed in MHz

2747 drw 16

300 mil, P16-1
300 mil, D16-1
SOIC, SO16-1

300 mil, P18-1
300 mil, D18-1
SOIC, SO18-1

72401/72403

72402/72404

NOTE:
1. Industrial temperature range is available by special order.

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ÐÐ»ÐµÐºÑ‚Ñ€Ð¾Ð½Ð½Ñ‹Ð¹ ÐºÐ¾Ð¼Ð¿Ð¾Ð½ÐµÐ½Ñ‚: 72401