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CMOS SyncBiFIFO
TM
256 x 18 x 2
512 x 18 x 2
IDT72605
IDT72615
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-2704/7
APRIL 2003
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The SyncBiFIFO is a trademark of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
FUNCTIONAL BLOCK DIAGRAM
FEATURES:




Two independent FIFO memories for fully bidirectional data
transfers




256 x 18 x 2 organization (IDT72605)




512 x 18 x 2 organization (IDT72615)




Synchronous interface for fast (20ns) read and write cycle times




Each data port has an independent clock and read/write control




Output enable is provided on each port as a three-state control
of the data bus




Built-in bypass path for direct data transfer between two ports




Two fixed flags, Empty and Full, for both the A-to-B and the B-
to-A FIFO




Programmable flag offset can be set to any depth in the FIFO




The synchronous BiFIFO is packaged in a 64-pin TQFP (Thin
Quad Flatpack) and 68-pin PLCC




Industrial temperature range (40


C to +85C)
DESCRIPTION:
The IDT72605 and IDT72615 are very high-speed, low-power bidirec-
tional First-In, First-Out (FIFO) memories, with synchronous interface for fast
read and write cycle times. The SyncBiFIFOTM is a data buffer that can store
or retrieve information from two sources simultaneously. Two Dual-Port FIFO
memory arrays are contained in the SyncBiFIFO; one data buffer for each
direction.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Each Port has its own independent clock. Data transfers to the
I/O registers are gated by the enable signals. The transfer direction for each
port is controlled independently by a read/write signal. Individual output enable
signals control whether the SyncBiFIFO is driving the data lines of a port or
whether those data lines are in a high-impedance state.
Bypass control allows data to be directly transferred from input to output
register in either direction.
The SyncBiFIFO has eight flags. The flag pins are Full, Empty, Almost-Full,
and Almost-Empty for both FIFO memories. The offset depths of the Almost-Full
and Almost-Empty flags can be programmed to any location.
The SyncBiFIFO is fabricated using IDT's high-speed, submicron CMOS
technology.
CLK
A
FLAG
LOGIC
MEMORY
ARRAY
512 x 18
256 x 18
INPUT REGISTER
MUX
OUTPUT REGISTER
HIGH
Z
CONTROL
OUTPUT REGISTER
INPUT REGISTER
CLK
B
MUX
MEMORY
ARRAY
512 x 18
256 x 18
HIGH
Z
CONTROL
FLAG
LOGIC
RESET
LOGIC
POWER
SUPPLY
R/
W
A
CS
A
A
2
A
1
A
0
EF
AB
PAE
AB
PAF
AB
FF
AB
OE
B
R/
W
B
EN
B
EN
A
OE
A
RS
EF
BA
PAE
BA
PAF
BA
FF
BA
V
CC
GND
3
BYP
B
P
INTERFACE
7
D
B0
-D
B17
D
A0
-D
A17
2704 drw 01
2
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
PIN CONFIGURATIONS
TQFP (PN64-1, order code: PF)
TOP VIEW
61
62
63
64
65
66
67
68
1
2
3
4
5
6
7
8
9
10
11
18
19
20
21
22
23
24
25
26
17
16
15
14
13
12
52
51
50
49
48
47
46
45
44
53
54
55
56
57
60
59
58
35
43
42
41
40
39
38
37
36
34
33
32
31
30
29
28
27
D
A16
C
A17
CLK
A
R/
W
A
EN
A
CS
A
A
0
A
1
A
2
V
CC
EF
AB
FF
AB
PAE
AB
PAF
AB
OE
A
D
B17
D
B16
D
A2
D
A1
D
A0
EF
BA
FF
BA
PAE
BA
PAF
BA
GND
BYP
B
OE
B
EN
B
R/
W
B
CLK
B
RS
D
B0
D
B1
D
B2
D
B15
GND
D
B14
D
B13
D
B12
D
B11
D
B10
V
CC
GND
D
B9
D
B8
D
B7
D
B6
D
B5
GND
D
B4
D
B3
D
A15
GND
D
A14
D
A13
D
A12
D
A11
D
A10
V
CC
GND
D
A9
D
A8
D
A7
D
A6
D
A5
GND
D
A4
D
A3
2704 drw 02
D
A2
D
A3
D
A4
D
A5
D
A6
D
A7
D
A8
D
A9
GND
V
CC
D
A10
D
A11
D
A12
D
A13
D
A14
D
A15
D
B3
D
B4
GND
D
B5
D
B6
D
B7
D
B8
D
B9
D
B10
D
B11
D
B12
D
B13
D
B14
GND
D
B15
D
B16
D
A16
D
A17
CLK
A
R/
W
A
EN
A
CS
A
A
0
A
1
A
2
V
CC
EF
AB
FF
AB
PAE
AB
PAF
AB
OE
A
D
B17
D
A1
D
A0
EF
BA
FF
BA
PAE
BA
PAF
BA
GND
BYB
B
OE
B
EN
B
R/
W
B
CLK
B
RS
D
B0
D
B1
D
B2
2704 drw 03
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32
PIN 1
PLCC (J68-1, order code: J)
TOP VIEW
3
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTION
Symbol
Name
I/O
Description
D
A0
-D
A17
Data A
I/O
Data inputs & outputs for the 18-bit Port A bus.
CS
A
Chip Select A
I
Port A is accessed when
CS
A
is LOW. Port A is inactive if
CS
A
is HIGH.
R/
W
A
Read/Write A
I
This pin controls the read or write direction of Port A. If R/
W
A
is LOW, Data A input data is written into Port A. If R/
W
A
is HIGH,
Data A output data is read from Port A. In bypass mode, when R/
W
A
is LOW, message is written into A
B output register. If
R/
W
A
is HIGH, message is read from B
A output register.
CLK
A
Clock A
I
CLK
A
is typically a free running clock. Data is read or written into Port A on the rising edge of CLK
A
.
EN
A
Enable A
I
When
EN
A
is LOW, data can be read or written to Port A. When
EN
A
is HIGH, no data transfers occur.
OE
A
Output Enable A
I
When R/
W
A
is HIGH, Port A is an output bus and
OE
A
controls the high-impedance state of D
A0
-D
A17
. If
OE
A
is HIGH, Port A is
in a high-impedance state. If
OE
A
is LOW while
CS
A
is LOW and R/
W
A
is HIGH, Port A is in an active (low-impedance) state.
A
0
, A
1
, A
2
Addresses
I
When
CS
A
is asserted, A
0
, A
1
, A
2
and R/
W
A
are used to select one of six internal resources.
D
B0
-D
B17
Data B
I/O
Data inputs & outputs for the 18-bit Port B bus.
R/
W
B
Read/Write B
I
This pin controls the read or write direction of Port B. If R/
W
B
is LOW, Data B input data is written into Port B. If R/
W
B
is HIGH,
Data B output data is read from Port B. In bypass mode, when R/
W
B
is LOW, message is written into B
A output register. If
R/
W
B
is HIGH, message is read from A
B output register.
CLK
B
Clock B
I
Clock B is typically a free running clock. Data is read or written into Port B on the rising edge of CLK
B
.
EN
B
Enable B
I
When
EN
B
is LOW, data can be read or written to Port B. When
EN
B
is HIGH, no data transfers occur.
OE
B
Output Enable B
I
When R/
W
B
is HIGH, Port B is an output bus and
OE
B
controls the high-impedance state of D
B0
-D
B17
. If OE
B
is HIGH, Port B is
in a high-impedance state. If
OE
B
is LOW while R/
W
B
is HIGH, Port B is in an active (low-impedance) state.
EF
AB
A
B Empty
O
When
EF
AB
is LOW, the A
B FIFO is empty and further data reads from Port B are inhibited. When EF
AB
is HIGH, the FIFO is
Flag
not empty.
EF
AB
is synchronized to CLK
B
. In the bypass mode,
EF
AB
HIGH indicates that data D
A0
-D
A17
is available for passing
through. After the data D
B0
-D
B17
has been read,
EF
AB
goes LOW.
PAE
AB
A
B
O
When
PAE
AB
is LOW, the A
B FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
Programmable
programmed into
PAE
AB
Register. When
PAE
AB
is HIGH, the A
B FIFO contains more than offset in PAE
AB
Register. The
Almost-Empty
default offset value for
PAE
AB
Register is 8.
PAE
AB
is synchronized to CLK
B
.
Flag
PAF
AB
A
B
O
When
PAF
AB
is LOW, the A
B FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
Programmable
programmed into
PAF
AB
Register. When
PAF
AB
is HIGH, the A
B FIFO contains less than or equal to the depth minus the
Almost-Full
offset in
PAF
AB
Register. The default offset value for
PAF
AB
Register is 8.
PAF
AB
is synchronized to CLK
A
.
Flag
FF
AB
A
B Full Flag
O
When
FF
AB
is LOW, the A
B FIFO is full and further data writes into Port A are inhibited. When FF
AB
is HIGH, the FIFO is not
full.
FF
AB
is synchronized to CLK
A
. In bypass mode,
FF
AB
tells Port A that a message is waiting in Port B's output register. If
FF
AB
is LOW, a bypass message is in the register. If
FF
AB
is HIGH, Port B has read the message and another message can be
written into Port A.
EF
BA
B
A Empty
O
When
EF
BA
is LOW, the B
A FIFO is empty and further data reads from Port A are inhibited. When EF
BA
is HIGH, the FIFO
Flag
is not empty.
EF
BA
is synchronized to CLK
A
. In the bypass mode,
EF
BA
HIGH indicates that data D
B0
-D
B17
is available for
passing through. After the data D
A0
-D
A17
has been read,
EF
BA
goes LOW on the following cycle.
PAE
BA
B
A
O
When
PAE
BA
is LOW, the B
A FIFO is almost-empty. An almost-empty FIFO contains less than or equal to the offset
Programmable
programmed into
PAE
BA
Register. When
PAE
BA
is HIGH, the B
A FIFO contains more than offset in PAE
BA
Register. The
Almost-Empty
default offset value for
PAE
BA
Register is 8.
PAE
BA
is synchronized to CLK
A
.
Flag
PAF
BA
B
A
O
When
PAF
BA
is LOW, the B
A FIFO is almost-full. An almost-full FIFO contains greater than the FIFO depth minus the offset
Programmable
programmed into
PAF
BA
Register. When
PAF
BA
is HIGH, the B
A FIFO contains less than or equal to the depth minus the
Almost-Full
offset in
PAF
BA
Register. The default offset value for
PAF
BA
Register is 8.
PAF
BA
is synchronized to CLK
B
.
Flag
FF
BA
B
A Full Flag
O
When
FF
BA
is LOW, the B
A FIFO is full and further data writes into Port B are inhibited. When FF
BA
is HIGH, the FIFO is
not full.
FF
BA
is synchronized to CLK
B
. In bypass mode,
FF
BA
tells Port B that a message is waiting in Port A's output register. If
FF
BA
is LOW, a bypass message is in the register. If
FF
BA
is HIGH, Port A has read the message and another message can be
written into Port B.
BYP
B
Port B Bypass
O
This flag informs Port B that the synchronous BiFIFO is in bypass mode. When BYP
B
is LOW, Port A has placed the FIFO into
Flag
bypass mode. If
BYP
B
is HIGH, the synchronous BiFIFO passes data into memory.
BYP
B
is synchronized to CLK
B
.
RS
Reset
I
A LOW on this pin will perform a reset of all synchronous BiFIFO functions.
V
CC
Power
There are three +5V power pins for the PLCC and two for the TQFP.
GND
Ground
There are seven ground pins for the PLCC and four for the TQFP.
4
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
ABSOLUTE MAXIMUM RATINGS
(1)
DC ELECTRICAL CHARACTERISTICS
RECOMMENDED DC OPERATING
CONDITIONS
SYMBOL
PARAMETER
MIN. TYP.
MAX. UNIT
V
CC
Supply Voltage
4.5
5.0
5.5
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage
2.0
--
--
V
V
IL
(1)
Input Low Voltage
--
--
0.8
V
T
A
Operating Temperature
-40
--
85
C
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
Symbol
Rating
Industrial
Unit
V
TERM
Terminal Voltage with
0.5 to +7.0
V
Respect to Ground
T
STG
Storage Temperature
55 to +125
C
I
OUT
DC Output Current
50 to +50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
(Industrial: V
CC
= 5V 10%, T
A
= -40
C to +85
C)
IDT72615L
IDT72605L
Industrial
t
CLK
= 20, 25, 35, 50ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
I
LI
(1)
Input Leakage Current (Any Input)
1
--
1
A
I
LO
(2)
Output Leakage Current
10
--
10
A
V
OH
Output Logic "1" Voltage I
OUT
= 2mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage I
OUT
= 8mA
--
--
0.4
V
I
CC
(3)
Active Power Supply Current
--
--
230
mA
NOTES:
1. Measurements with 0.4V
V
IN
V
CC
.
2.
OEA, OEB
V
IH
; 0.4
V
OUT
V
CC
.
3. Tested with outputs open (I
OUT
= 0). Testing frequency f=20MHz.
CAPACITANCE
(T
A
= +25
C, F = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
(2)
Input Capacitance
V
IN
= 0V
10
pF
C
OUT
(1,2)
Output Capacitance
V
OUT
= 0V
10
pF
NOTES:
1. With output deselected.
2. Characterized values, not currently tested.
5
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 5V 10%, T
A
= -40
C to +85C)
+5V
1.1K
680
30pF*
D.U.T.
2704 drw 04
Industrial
IDT72615L20
IDT72615L25
IDT72615L35
IDT72615L50
IDT72605L20
IDT72605L25
IDT72605L35
IDT72605L50
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
Timing Figures
f
CLK
Clock frequency
--
50
--
40
--
28
--
20
MHz
--
t
CLK
Clock cycle time
20
--
25
--
35
--
50
--
ns
4,5,6,7
t
CLKH
Clock HIGH time
8
--
10
--
14
--
20
--
ns
4,5,6,7,12,13,14,15
t
CLKL
Clock LOW time
8
--
10
--
14
--
20
--
ns
4,5,6,7,12,13,14,15
t
RS
Reset pulse width
20
--
25
--
35
--
50
--
ns
3
t
RSS
Reset setup time
12
--
15
--
21
--
30
--
ns
3
t
RSR
Reset recovery time
12
--
15
--
21
--
30
--
ns
3
t
RSF
Reset to flags in initial state
--
27
--
28
--
35
--
50
ns
3
t
A
Data access time
3
10
3
15
3
21
3
25
ns
5,7,8,9,10,11
t
CS
Control signal setup time
(1)
6
--
6
--
8
--
10
--
ns
4,5,6,7,8,9,10,11,
12, 13,14,15
t
CH
Control signal hold time
(1)
1
--
1
--
1
--
1
--
ns
4,5,6,7,10,11,12,
13, 14,15
t
DS
Data setup time
6
--
6
--
8
--
10
--
ns
4,6,8,9,10,11
t
DH
Data hold time
1
--
1
--
1
--
1
--
ns
4,6
t
OE
Output Enable LOW to output data valid
(2)
3
10
3
13
3
20
3
28
ns
5,7,8,9,10,11
t
OLZ
Output Enable LOW to data bus at Low-Z
(2)
0
--
0
--
0
--
0
--
ns
5,7,8,9,10,11
t
OHZ
Output Enable HIGH to data bus at High-Z
(2)
3
10
3
13
3
20
3
28
ns
5,7,10,11
t
FF
Clock to Full Flag time
--
10
--
15
--
21
--
30
ns
4,6,10,11
t
EF
Clock to Empty Flag time
--
10
--
15
--
21
--
30
ns
5,7,8,9,10,11
t
PAE
Clock to Programmable
--
12
--
15
--
21
--
30
ns
12,14
Almost-Empty Flag time
t
PAF
Clock to Programmable
--
12
--
15
--
21
--
30
ns
13,15
Almost-Full Flag time
t
SKEW1
Skew between CLK
A
& CLK
B
10
--
12
--
17
--
20
--
ns
4,5,6,7,8,9,10,11
for Empty/Full Flags
(2)
t
SKEW2
Skew between CLK
A
& CLK
B
17
--
19
--
25
--
34
--
ns
4, 7,12,13,14,15
for Programmable Flags
(2)
NOTES:
1. Control signals refer to
CS
A
, R/
W
A
,
EN
A
, A
2
, A
1
, A
0
, R/
W
B
,
EN
B
.
2. Minimum values are guaranteed by design.
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 2
or equivalent circuit
Figure 2. Output Load
* Includes jig and scope capacitances.
6
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
CLK
DATA
ADDR, I/0
CONTROL
LOGIC
RAM A
IDT
SYNCBIFIFO
DATA B
CONTROL B
SYSTEM
CLOCK A
CONTROL
LOGIC
CLK
MICROPROCESSOR
A
MICROPROCESSOR
B
DATA
ADDR, I/0
RAM B
SYSTEM
CLOCK B
IDT
SYNCBIFIFO
DATA B
CLK
B
CONTROL B
DATA A
CLK
A
CONTROL A
DATA A
CONTROL A
2704 drw 05
CLK
B
CLK
A
FUNCTIONAL DESCRIPTION
IDTs SyncBiFIFO is versatile for both multiprocessor and peripheral
applications. Data can be stored or retrieved from two sources simultaneously.
The SyncBiFIFO has registers on all inputs and outputs. Data is only
transferred into the I/O registers on clock edges, hence the interfaces are
synchronous. Two Dual-Port FIFO memory arrays are contained in the
SyncBiFIFO; one data buffer for each direction. Each port has its own
independent clock. Data transfers to the I/O registers are gated by the enable
signals. The transfer direction for each port is controlled independently by a
read/write signal. Individual output enable signals control whether the SyncBiFIFO
is driving the data lines of a port or whether those data lines are in a high-
impedance state. The processor connected to Port A of the BiFIFO can send
or receive messages directly to the Port B device using the 18-bit bypass path.
The SyncBiFIFO can be used in multiples of 18-bits. In a 36- to 36-bit
configuration, two SyncBiFIFOs operate in parallel. Both devices are pro-
grammed simultaneously, 18 data bits to each device. This configuration can
be extended to wider bus widths (54- to 54-bits, 72- to 72-bits, etc.) by adding
more SyncBiFIFOs to the configuration. Figure 1 shows multiple SyncBiFIFOs
configured for multiprocessor communication.
The microprocessor or microcontroller connected to Port A controls all
operations of the SyncBiFIFO. Thus, all Port A interface pins are inputs driven
by the controlling processor. Port B interfaces with a second processor. The
Port B control pins are inputs driven by the second processor.
RESET
Reset is accomplished whenever the Reset (
RS) input is taken to a LOW state
with
CS
A
,
EN
A
and
EN
B
HIGH. During reset, both internal read and write
pointers are set to the first location. A reset is required after power up before a
write operation can take place. The A
B and BA FIFO Empty Flags (EF
AB
,
EF
BA
) and Programmable Almost-Empty flags (
PAE
AB
,
PAE
BA
) will be set to
LOW after t
RSF
. The A
B and BA FIFO Full Flags (FF
AB
,
FF
BA
) and
Programmable Almost- Full flags (
PAF
AB
,
PAF
BA
) will be set to HIGH after t
RSF
.
After the reset, the offsets of the Almost-Empty flags and Almost- Full flags for the
A
B and BA FIFO offset default to 8.
PORT A INTERFACE
The SyncBiFIFO is straightforward to use in micro-processor-based
systems because each port has a standard microprocessor control set. Port A
interfaces with microprocessor through the three address pins (A
2
-A
0
) and a
Chip Select
CS
A
pins. When
CS
A
is asserted, A
2
,A
1
,A
0
and R/
W
A
are used
to select one of six internal resources (Table 1).
With A
2
=0 and A
1
=0, A
0
determines whether data can be read out of output
register or be written into the FIFO (A
0
=0), or the data can pass through the
FIFO through the bypass path (A
0
=1).
With A
2
=1, four programmable flags (two A
B FIFO programmable flags
and two B
A FIFO programmable flags) can be selected: the AB FIFO
Almost-Empty flag Offset (A
1
=0, A
0
=0), A
B FIFO Almost-Full flag Offset
(A
1
=0, A
0
=1), B
A FIFO Almost-Empty flag Offset (A
1
=1, A
0
=0), B
A FIFO
Almost-Full flag Offset (A
1
=1, A
0
=1).
Port A is disabled when CSA is deasserted and data A is in high-impedance
state.
BYPASS PATH
The bypass paths provide direct communication between Port A and Port
B. There are two full 18-bit bypass paths, one in each direction. During a bypass
operation, data is passed directly between the input and output registers, and
the FIFO memory is undisturbed.
Port A initiates and terminates all bypass operations. The bypass flag,
BYP
B
,
is asserted to inform Port B that a bypass operation is beginning. The bypass
flag state is controlled by the Port A controls, although the
BYP
B
signal is
synchronized to CLK
B
. So,
BYP
B
is asserted on the next rising edge of CLK
B
when A
2
A
1
A
0
=001and CS
A
is LOW. When Port A returns to normal FIFO mode
(A
2
A
1
A
0
=000 or CS
A
is HIGH),
BYP
B
is deasserted on the next CLK
B
rising
edge.
Once the SyncBiFIFO is in bypass mode, all data transfers are controlled
by the standard Port A (R/
W
A
, CLK
A
,
EN
A
,
OE
A
) and Port B (R/
W
B
, CLK
B
,
EN
B
,
OE
B
) interface pins. Each bypass path can be considered as a one word
deep FIFO. Data is held in each input register until it is read. Since the controls
Figure 1. 36- to 36-bit Processor Interface Configuration
NOTES:
1. Upper SyncBiFIFO only is used in 18- to 18-bit configuration.
2. Control A consists of R/
W
A
,
EN
A
,
OE
A
,
CS
A
, A
2
, A
1
, A
0
. Control B consists of R/
W
B
,
EN
B
,
OE
B
.
7
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
Data A
CS
A
R/
W
A
EN
A
OE
A
I/O
Port A Operation
0
0
0
0
I
Data A is written on CLK
A
. This write cycle immediately following low-impedance cycle is prohibited. Note
that even though
OE
A
= 0, a LOW logic level on R/
W
A
, once qualified by a rising edge on CLK
A,
will put Data A into
a high-impedance state.
0
0
0
1
I
Data A is written on CLKA
0
0
1
X
I
Data A is ignored
0
1
0
0
O
Data is read
(1)
from RAM array to output register on CLK
A
, Data A is low-impedance
0
1
0
1
O
Data is read
(1)
from RAM array to output register on CLK
A
, Data A is high-impedance
0
1
1
0
O
Output register does not change
(2)
, Data A is low-impedance
0
1
1
1
O
Output register does not change
(2)
, Data A is high-impedance
1
0
X
X
I
Data A is ignored
(3)
1
1
X
X
O
Data A is high-impedance
(3)
NOTES:
1. When A
2
A
1
A
0
= 000, the next B
A FIFO value is read out of the output register and the read pointer advances. If A
2
A
1
A
0
= 001, the bypass path is selected and bypass
data from the Port B input register is read from the Port A output register. If A
2
A
1
A
0
0 = 1XX, a flag offset register is selected and its offset is read out through Port A output
register.
2. Regardless of the condition of A
2
A
1
A
0
, the data in the Port A output register does not change and the B
A read pointer does not advance.
3. If CS
A#
is HIGH, then BYP
B
is HIGH. No bypass occur under this condition.
TABLE 1
PORT A OPERATION CONTROL SIGNALS
CS
A
A
2
A
1
A
0
Read
Write
0
0
0
0
B
A FIFO
A
B FIFO
0
0
0
1
18-bit Bypass Path
0
1
0
0
A
B FIFO Almost-Empty
Flag Offset
0
1
0
1
A
B FIFO Almost-Full
Flag Offset
0
1
1
0
B
A FIFO Almost-Empty
Flag Offset
0
1
1
1
B
A FIFO Almost-Full
Flag Offset
1
X
X
X
Port A Disabled
TABLE 2
ACCESSING PORT A RE-
SOURCES USING
CS
A
, A
2
, A
1
, AND A
0
of each port operate independently, Port A can be reading bypass data at the
same time Port B is reading bypass data.
When R/
W
A
and
EN
A
is LOW, data on pins D
A0
-D
A17
is written into Port
A input register. Following the rising edge of CLK
A
for this write, the A
B Full
Flag (
FF
AB
) goes LOW. Subsequent writes into Port A are blocked by internal
logic until
FF
AB
goes HIGH again. On the next CLKB rising edge, the A
B
Empty Flag (
EF
AB
) goes HIGH indicating to Port B that data is available. Once
R/
W
B
is HIGH and
EN
B
is LOW, data is read into the Port B output register.
OE
B
still controls whether Port B is in a high-impedance state. When
OE
B
is LOW,
the output register data appears at D
B0
-D
B17
.
EF
AB
goes LOW following the
CLK
B
rising edge for this read. FFAB goes HIGH on the next CLK
A
rising edge,
letting Port A know that another word can be written through the bypass path.
Bypass data transfers from Port B to Port A work in a similar manner with
EFB
A
and
FFB
A
indicating the Port A output register state.
When the Port A address changes from bypass mode (A
2
A
1
A
0
=001) to
FIFO mode (A
2
A
1
A
0
=000) on the rising edge of CLK
A
, the data held in the Port
B output register may be overwritten. Unless Port A monitors the
BYP
B
pin and
waits for Port B to clock out the last bypass word, data from the A
B FIFO will
overwrite data in the Port B output register.
BYP
B
will go HIGH on the rising
edge of CLK
B
signifying that Port B has finished its last bypass operation. Port
B must read any bypass data in the output register on this last CLK
B
clock or
it is lost and the SyncBiFIFO returns to FIFO operations. It is especially important
to monitor
BYP
B
when CLK
B
is much slower than CLK
A
to avoid this condition.
BYP
B
will also go HIGH after
CS
A
is brought HIGH; in this manner the Port B
bypass data may also be lost.
Since the Port A processor controls
CS
A
and the bypass mode, this scenario
can be handled for B
A bypass data. The Port A processor must be set up
to read the last bypass word before leaving bypass mode.
PORT A CONTROL SIGNALS
The Port A control signals pins dictate the various operations shown in Table
2. Port A is accessed when
CS
A
is LOW, and is inactive if
CS
A
is HIGH. R/
W
A
and
EN
A
lines determine when Data A can be written or read. If R/
W
A
and
EN
A
are LOW, data is written into input register on the LOW-to-HIGH transition
of CLK
A
. If R/
W
A
is HIGH and
OE
A
is LOW, data comes out of bus and is read
from output register into three-state buffer. Refer to pin descriptions for more
information.
PROGRAMMABLE FLAGS
The IDT SyncBiFIFO has eight flags: four flags for A
B FIFO (EF
AB
,
PAE
AB
,
PAF
AB
,
FF
AB
), and four flags for B
A FIFO (EF
BA
,
PAE
BA
,
PAF
BA
,
FF
BA
). The Empty and Full flags are fixed, while the Almost-Empty and Almost-
Full offsets can be set to any depth through the Flag Offset Registers (see Table
3). The flags are asserted at the depths shown in the Flag Truth Table (Table
4). After reset, the programmable flag offsets are set to 8. This means the Almost-
Empty flags are asserted at Empty +8 words deep, and the Almost-Full flags are
asserted at Full -8 words deep.
The
PAE
AB
is synchronized to CLK
B
, while
PAE
AB
is synchronized to CLK
A
;
and
PAE
BA
is synchronized to CLK
A
, while
PAE
BA
is synchronized to CLK
B
.
If the minimum time (t
SKEW2
) between a rising CLK
B
and a rising CLK
A
is met,
the flag will change state on the current clock; otherwise, the flag may not change
state until the next clock rising edge. For the specific flag timings, refer to Figures
12-15.
PORT B CONTROL SIGNALS
The Port B control signal pins dictate the various operations shown in Table
5. Port B is independent of
CS
A
. R/
W
B
and
EN
B
lines determine when Data
8
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
can be written or read in Port B. If R/
W
B
and
EN
B
are LOW, data is written into
input register, and on LOW-to-HIGH transition of CLK
B
data is written into input
register and the FIFO memory. If R/
W
B
is HIGH and
OE
B
is LOW, data comes
out of bus and is read from output register into three-state buffer. In bypass mode,
if R/
W
B
is LOW, bypass messages are transferred into B
A output register.
If R/
W
A
is HIGH, bypass messages are transferred into A
B output register.
Refer to pin descriptions for more information.
TABLE 3
FLAG OFFSET REGISTER FORMAT
NOTE:
1. Bit 8 must be set to 0 for the IDT72605 (256 x 18) Synchronous BiFIFO.
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAE
AB
Register
X
X
X
X
X
X
X
X
X
A
B FIFO Almost-Empty Flag Offset
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAF
AB
Register
X
X
X
X
X
X
X
X
X
A
B FIFO Almost-Full Flag Offset
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAE
BA
Register
X
X
X
X
X
X
X
X
X
B
A FIFO Almost-Empty Flag Offset
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
PAF
BA
Register
X
X
X
X
X
X
X
X
X
B
A FIFO Almost-Full Flag Offset
TABLE 4
INTERNAL FLAG TRUTH TABLE
Number of Words
in FIFO
From
To
EF
PAE
PAF
FF
0
0
LOW
LOW
HIGH
HIGH
1
n
HIGH
LOW
HIGH
HIGH
n+1
D-(m+1)
HIGH
HIGH
HIGH
HIGH
D-m
D-1
HIGH
HIGH
LOW
HIGH
D
D
HIGH
HIGH
LOW
LOW
NOTE:
1. n = Programmable Empty Offset (
PAE
AB
Register or
PAE
BA
Register)
m = Programmable Full Offset (
PAF
AB
Register or
PAF
BA
Register)
D = FIFO Depth (IDT72605 = 256 words, IDT72615= 512 words)
TABLE 5
PORT B OPERATION CONTROL SIGNALS
Data B
R/
W
B
EN
B
OE
B
I/O
Port B Operation
0
0
0
I
Data B is written on CLKB
. This write cycle immediately following output low-impedance cycle is prohibited. Note
that even though
OE
B
= 0, a LOW logic level on R/
W
B
, once qualified by a rising edge on CLK
B,
will put Data B into a high-
impedance state.
0
0
1
I
Data B is written on CLKB
.
0
1
X
I
Data B is ignored
1
0
0
O
Data is read
(1)
from RAM array to output register on CLKB
Data B is low-impedance
1
0
1
O
Data is read
(1)
from RAM array to output register on CLKB
, Data B is high- impedance
1
1
0
O
Output register does not change
(2)
, Data B is low-impedance
1
1
1
O
Output register does not change
(2)
, Data B is high-impedance
NOTES:
1. When A
2
A
1
A
0
= 000 or 1XX, the next A
B FIFO value is read out of the output register and the read pointer advances. If A
2
A
1
A
0
= 001, the bypass path is selected and
bypass data is read from the Port B output register.
2. Regardless of the condition of A
2
A
1
A
0
, the data in the Port B output register does not change and the A
B read pointer does not advance.
9
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
RS
t
RSF
t
RS
t
RSF
t
RSR
EF
AB,
PAE
AB,
EF
BA,
PAE
BA
CS
A,
EN
A
,
EN
B
t
RSS
2704 drw 06
EF
AB,
PAE
AB,
EF
BA,
PAE
BA
CLK
A
EN
A
CS
A
A
0
, A
1,
A
2
R/
W
A
FF
AB
t
DS
D
A0-
D
A17
CLK
B
READ
NO READ OPERATION
DATA IN VALID
NO OPERATION
t
FF
t
FF
t
SKEW1
t
DH
t
CH
t
CS
t
CLKL
t
CLK
t
CLKH
2704 drw 07
Figure 4. Port A (A
B) Write Timing
Figure 3. Reset Timing
10
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
t
CS
NO OPERATION
CLK
A
EN
A
CS
A
A
0
, A
1,
A
2
R/
W
A
EF
BA
D
A0-
D
A17
CLK
B
OE
A
t
CLK
t
CLKH
t
CLKL
t
CH
t
EF
t
A
t
OLZ
t
OE
t
OHZ
t
SKEW1
t
EF
NO WRITE
WRITE
VALID DATA
2704 drw 08
t
DS
DATA IN VALID
t
SKEW1
READ
NO READ OPERATION
CLK
B
EN
B
R/
W
B
FF
BA
D
B0-
D
B17
CLK
A
NO OPERATION
t
DH
t
FF
t
FF
t
CS
t
CH
t
CLKL
t
CLKH
t
CLK
2704 drw 09
Figure 6. Port B (B
A) Write Timing
Figure 5. Port A (B
A) Read Timing
11
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
VALID DATA
t
SKEW1
NO WRITE OPERATION
CLK
B
EN
B
R/
W
B
EF
BA
D
B0-
D
B17
CLK
A
NO OPERATION
t
EF
t
EF
t
CS
t
CH
t
CLKL
t
CLKH
t
CLK
OE
B
t
A
WRITE
t
OE
t
OLZ
t
OHZ
2704 drw 10
(First Valid Write)
(1)
t
SKEW1
CLK
A
EN
B
R/
W
A
EF
AB
D
B0-
D
B17
CLK
B
t
EF
t
CS
OE
B
t
A
t
OE
t
OLZ
R/
W
B
D
A0-
D
A17
CS
A
,
EN
A
A
0
, A
1
, A
2
t
A
t
FRL
t
CS
D
0
D
1
D
1
D
2
D
3
D
0
t
DS
2704 drw 11
Figure 7. Port B (A
B) Read Timing
NOTE:
1. When t
SKEW1
minimum specification, t
FRL
(Max.) = t
CLK
+ t
SKEW1
t
SKEW1
< minimum specification, t
FRL
(Max.) = 2t
CLK
+ t
SKEW1 or
t
CLK
+ t
SKEW1
The Latency Timing applies only at the Empty Boundary (
EF = LOW).
Figure 8. A
B First Data Word Latency after Reset for Simultaneous Read and Write
12
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
(First valid write)
(1)
t
SKEW1
CLK
B
EN
B
R/
W
B
EF
BA
D
A0-
D
A17
CLK
A
t
EF
t
CS
OE
A
t
A
t
OE
t
OLZ
R/
W
A
D
B0-
D
B17
CS
A
,
EN
A
A
0
, A
1
, A
2
t
A
t
FRL
t
CS
D
0
D
1
D
1
D
2
D
3
D
0
t
DS
2704 drw 12
NOTE:
1. When t
SKEW1
minimum specification, t
FRL
(Max.) = t
CLK
+ t
SKEW1
t
SKEW1
< minimum specification, t
FRL
(Max.) = 2t
CLK
+ t
SKEW1
The Latency Timing apply only at the Empty Boundary (
EF = LOW).
Figure 9. B
A First Data Word Latency after Reset for Simultaneous Read and Write
13
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
DATA INPUT
BYPASS FLAG
t
SKEW1
CLK
B
EN
B
R/
W
B
FF
AB
D
A0-
D
A17
CLK
A
t
CS
OE
B
t
A
t
OE
t
OLZ
R/
W
A
D
B0-
D
B17
EN
A
A
0
, A
1
, A
2
t
DS
2704 drw 13
CS
A
EF
AB
BYP
B
A
2
, A
1
, A
0
= 001
t
FF
t
CH
t
CS
t
CS
t
FF
t
FF
t
EF
t
EF
t
EF
t
OHZ
DATA OUTPUT
FIFO FLAG
BYPASS FLAG
FIFO FLAG
FIFO FLAG
t
SKEW1
t
SKEW1
t
CH
NOTES:
1. When
CS
A
is brought HIGH, A
B Bypass mode will switch to FIFO mode on the following CLK
A
LOW-to-HIGH transition.
2. After the bypass operation is completed, the
BYP
B
goes from LOW-to-HIGH; this will reset all bypass flags. The bypass path becomes available for the next bypass
operation.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO
mode.
Figure 10. A
B Bypass Timing
14
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
DATA INPUT
BYPASS FLAG
DATA OUTPUT
BYPASS FLAG
CLK
A
EN
B
R/
W
B
EF
BA
D
B0-
D
B17
CLK
B
OE
A
t
A
t
OE
t
OLZ
R/
W
A
D
A0-
D
A17
EN
A
A
0
, A
1
, A
2
2704 drw 14
CS
A
FF
BA
BYP
B
A
2
, A
1
, A
0
= 001
t
FF
t
EF
t
OHZ
FIFO FLAG
t
SKEW1
FIFO FLAG
FIFO FLAG
t
FF
t
FF
t
FF
t
CH
t
DS
t
SKEW1
t
CS
t
SKEW1
t
SKEW1
t
CS
t
CS
t
CS
t
EF
t
EF
t
EF
t
CS
NOTES:
1. When
CS
A
is brought HIGH, A
B Bypass mode will switch to FIFO mode on the following CLK
A
going LOW-to-HIGH.
2. After the bypass operation is completed, the
BYP
B
goes from LOW-to-HIGH; this will reset all bypass flags.
3. When A-side changed from bypass mode into FIFO mode, B-side only has one cycle to read the bypass data. On the next cycle, B-side will be forced back to FIFO
mode.
Figure 11. B
A Bypass Timing
15
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
INDUSTRIAL TEMPERATURE RANGE
(1)
WRITE
READ
n words in FIFO
n+1 words in FIFO
t
CLKL
2704 drw 15
CLK
A
EN
A
(R/
W
A
= 0)
PAE
AB
CLK
B
EN
A
(R/
W
B
= 1)
t
CLKH
t
CS
t
CH
t
SKEW2
t
PAE
t
CS
t
CH
t
PAE
(2)
WRITE
READ
(2)
Full - (m+1) words in FIFO
Full - m words in FIFO
t
CLKL
2704 drw 16
CLK
A
EN
A
(R/
W
A
= 0)
PAF
AB
CLK
B
EN
B
(R/
W
B
= 1)
t
CLKH
t
CS
t
CH
t
PAF
t
CS
t
CH
t
PAF
NOTES:
1. t
SKEW2
the minimum time between a rising CLK
A
edge and a rising CLK
B
edge for
PAE
AB
to change during that clock cycle. If the time between the rising edge of CLK
A
and
the rising edge of CLK
B
is less than t
SKEW
, then
PAE
AB
may not go HIGH until the next CLKB rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n + 1) words in the FIFO when
PAE goes LOW.
Figure 12. A
B Programmable Almost-Empty Flag Timing
NOTES:
1. t
SKEW2
is the minimum time between a rising CLK
B
edge and a rising CLK
A
edge for
PAF
AB
to change during that clock cycle. If the time between the rising edge of CLK
B
and the rising edge of CLK
A
is less than t
SKEW2
, then
PAF
AB
may not go HIGH until the next CLK
A
rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when
PAF goes LOW.
Figure 13. A
B Programmable Almost-Full Flag Timing
16
INDUSTRIAL TEMPERATURE RANGE
IDT72605/72615 CMOS SYNCBiFIFOTM
256 x 18x 2 and 512 x 18 x 2
Full - m words in FIFO
WRITE
(2)
Full - (m+1) words in FIFO
t
CLKL
2704 drw 18
CLK
B
EN
B
(R/
W
A
= 0)
PAF
BA
CLK
A
EN
A
(R/
W
A
= 1)
t
CLKH
t
CS
t
CH
t
PAF
t
CS
t
CH
t
SKEW2
(1)
t
PAF
READ
NOTES:
1. t
SKEW2
is the minimum time between a rising CLK
B
edge and a rising CLK
A
edge for
PAF
BA
to change during that clock cycle. If the time between the rising edge of CLK
B
and the rising edge of CLK
A
is less than t
SKEW2
, then
PAF
BA
may not go HIGH until the next CLK
A
rising edge.
2. If a write is performed on this rising edge of the write clock, there will be Full - (m + 1) words in the FIFO when
PAF goes LOW.
Figure 15. B
A Programmable Almost-Full Flag Timing
(1)
WRITE
READ
n words in FIFO
n+1 words in FIFO
t
CLKL
2704 drw 17
CLK
B
EN
B
(R/
W
A
= 0)
PAE
BA
CLK
A
EN
A
(R/
W
A
= 1)
t
CLKH
t
CS
t
CH
t
PAE
t
CS
t
CH
t
SKEW2
t
PAE
(2)
Figure 14. B
A Programmable Almost-Empty Flag Timing
NOTES:
1. t
SKEW2
is the minimum time between a rising CLK
B
edge and a rising CLK
A
edge for
PAE
BA
to change during that clock cycle. If the time between the rising edge of CLK
B
and the rising edge of CLK
A
is less than t
SKEW2
, then
PAE
BA
may not go HIGH until the next CLK
A
rising edge.
2. If a read is performed on this rising edge of the read clock, there will be Empty + (n - 1) words in the FIFO when
PAE goes LOW.
17
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ORDERING INFORMATION
DATASHEET DOCUMENT HISTORY
11/02/2000
pgs. 1, 2, 3, 4, 16
04/08/2003
pg. 17.
IDT
XXXXX
X
XX
X
X
Device Type Power
Speed
Package
Process/
Temperature
Range
Blank
J
PF
20
25
35
50
L
72605
72615
Industrial (-40
C to +85C)
Plastic Leaded Chip Carrier (PLCC, J68-1)
Thin Quad Flat Pack (TQFP, PN64-1)
Low Power
256 x 18
Parallel SyncBiFIFO
512 x 18
Parallel SyncBiFIFO
2704 drw19
Clock Cycle Time (t
CLK
)
in Nanoseconds