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Электронный компонент: 72T3685

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1
MARCH 2003
DSC-5907/16
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
2.5 VOLT HIGH-SPEED TeraSync
TM
FIFO 36-BIT CONFIGURATIONS
1,024 x 36, 2,048 x 36, 4,096 x 36,
8,192 x 36, 16,384 x 36, 32,768 x 36,
65,536 x 36, 131,072 x 36 and 262,144 x 36
IDT72T3645, IDT72T3655, IDT72T3665,
IDT72T3675, IDT72T3685, IDT72T3695,
IDT72T36105, IDT72T36115, IDT72T36125
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc. The TeraSync FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FEATURES:




Choose among the following memory organizations:
IDT72T3645
1,024 x 36
IDT72T3655
2,048 x 36
IDT72T3665
4,096 x 36
IDT72T3675
8,192 x 36
IDT72T3685
16,384 x 36
IDT72T3695
32,768 x 36
IDT72T36105
65,536 x 36
IDT72T36115
131,072 x 36
IDT72T36125
262,144 x 36




Up to 225 MHz Operation of Clocks




User selectable HSTL/LVTTL Input and/or Output




2.5V LVTTL or 1.8V, 1.5V HSTL Port Selectable Input/Ouput voltage




3.3V Input tolerant




Read Enable & Read Clock Echo outputs aid high speed operation




User selectable Asynchronous read and/or write port timing




Mark & Retransmit, resets read pointer to user marked position




Write Chip Select (
WCS) input enables/disables Write operations




Read Chip Select (
RCS) synchronous to RCLK




Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets




Program programmable flags by either serial or parallel means




Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags




Separate SCLK input for Serial programming of flag offsets




User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out




Big-Endian/Little-Endian user selectable byte representation




Auto power down minimizes standby power consumption




Master Reset clears entire FIFO




Partial Reset clears data, but retains programmable settings




Empty, Full and Half-Full flags signal FIFO status




Select IDT Standard timing (using
EF and FF flags) or First Word
Fall Through timing (using
OR and IR flags)




Output enable puts data outputs into high impedance state




JTAG port, provided for Boundary Scan function




Available in 208-pin (17mm x 17mm) or 240-pin (19mm x 19mm)
Plastic Ball Grid Array (PBGA)




Easily expandable in depth and width




Independent Read and Write Clocks (permit reading and writing
simultaneously)




High-performance submicron CMOS technology




Industrial temperature range (40


C to +85C) is available
INPUT REGISTER
OUTPUT REGISTER
RAM ARRAY
1,024 x 36, 2,048 x 36
4,096 x 36, 8,192 x 36
16,384 x 36, 32,768 x 36
65,536 x 36, 131,072 x36
262,144 x 36
FLAG
LOGIC
FF/IR
PAF
EF/OR
PAE
HF
READ POINTER
READ
CONTROL
LOGIC
WRITE CONTROL
LOGIC
WRITE POINTER
RESET
LOGIC
WEN WCLK/WR
D
0
-D
n
(x36, x18 or x9)
LD
MRS
REN
RCLK/RD
OE
Q
0
-Q
n
(x36, x18 or x9)
OFFSET REGISTER
PRS
FWFT/SI
SEN
RT
5907 drw01
BUS
CONFIGURATION
BM
CONTROL
LOGIC
BE
OW
IP
PFM
FSEL0
FSEL1
IW
MARK
SCLK
RCS
JTAG CONTROL
(BOUNDARY SCAN)
TCK
TMS
TDO
TDI
TRST
ASYR
WCS
ERCLK
EREN
HSTL I/0
CONTROL
Vref
WHSTL
RHSTL
ASYW
SHSTL
FUNCTIONAL BLOCK DIAGRAM
2
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN CONFIGURATION
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
WCS
SCLK
VREF
SEN
D33
D31
D29
D14
D11
D9
D10
D8
PRS
TCK
FWFT/SI
ASYR
SHSTL
BE
TDI
RHSTL
RT
TMS
EF
D3
PAE
WCLK
TRST
MRS
D0
D5
V
CC
D7
REN
RCLK
RCS
Q32
Q30
Q28
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A1 BALL PAD CORNER
V
DDQ
V
CC
V
CC
V
CC
V
CC
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
HF
LD
V
CC
V
CC
V
CC
V
CC
V
CC
D13
IP
BM
V
DDQ
V
CC
D27
D24
D22
D20
D18
D16
IW
D34
D32
D30
D28
D26
D23
D25
D21
D19
D17
D15
D12
D1
Q12
Q10
Q8
Q26
Q24
Q21
Q19
Q17
Q15
ERCLK
Q1
Q3
Q9
Q7
Q5
PFM
MARK
EREN
V
CC
V
CC
V
CC
V
CC
V
CC
ASYW
WHSTL
FF
V
CC
V
CC
V
CC
V
CC
V
DDQ
V
CC
V
DDQ
V
DDQ
Q35
V
DDQ
V
DDQ
V
DDQ
GND
V
CC
GND
V
CC
GND
GND
GND
GND
Q33
V
CC
V
DDQ
V
DDQ
GND
GND
GND
V
CC
V
DDQ
V
DDQ
Q4
V
CC
GND
GND
GND
D6
D2
D4
TDO
Q2
Q0
Q6
Q11
Q23
Q22
Q20
Q18
Q16
Q13
Q31
Q29
Q27
Q25
V
CC
GND
GND
GND
GND
GND
V
CC
GND
GND
V
CC
GND
V
CC
GND
GND
GND
GND
V
CC
V
CC
V
CC
V
CC
V
CC
V
DDQ
V
CC
V
DDQ
V
DDQ
V
DDQ
Q14
V
DDQ
WEN
OE
Q34
D35
OW
FSI
PAF
FSO
V
CC
5907 drw02
IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695 Only
PBGA: 1mm pitch, 17mm x 17mm (BB208-1, order code: BB)
TOP VIEW
3
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
IDT72T36105/72T36115/72T36125 Only
PBGA: 1mm pitch, 19mm x 19mm (BB240-1, order code: BB)
TOP VIEW
PIN CONFIGURATION (CONTINUED)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
D21
D19
D20
D13
GND
TDO
GND
D4
TMS
GND
D5
D10
D23
D22
D1
Q24
Q14
GND
Q0
Q2
Q11
Q8
Q3
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
V
CC
D24
V
CC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
V
CC
REN
GND
PAF
EREN
V
DDQ
OE
RCLK
V
CC
V
CC
V
CC
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
A1 BALL PAD CORNER
MRS
V
CC
V
CC
D35
D32
D29
D26
FF
EF
V
CC
V
CC
V
CC
D33
D30
D27
V
CC
V
CC
V
CC
V
CC
SEN
V
CC
V
CC
V
CC
D34
D31
D28
D25
Q27
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q33
Q30
RCS
V
DDQ
V
DDQ
V
CC
V
CC
V
CC
SCLK
V
CC
V
CC
V
CC
V
CC
WCS
V
CC
V
CC
V
CC
PAE
LD
HF
GND
V
DDQ
MARK
V
DDQ
RT
SHSTL
FWFT/SI
FS0
OW
IP
FS1
BE
GND
PFM
BM
ASYR
RHSTL
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
WHSTL
ASYW
VREF
IW
GND
GND
GND
GND
V
CC
V
DDQ
V
DDQ
V
CC
WEN
GND
WCLK
PRS
V
CC
5907 drw02A
U
V
D18
V
CC
D16
D15
TDI
TCK
TRST
D6
D0
D2
D9
D12
D14
D17
D3
Q15
Q16
GND
ERCLK
Q4
Q13
Q10
Q7
Q5
D11
D8
D7
GND
Q6
Q1
Q9
Q12
17
18
Q22
Q20
Q21
Q23
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q25
V
DDQ
V
DDQ
V
DDQ
Q34
Q31
Q28
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q35
Q32
Q29
Q26
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
V
DDQ
Q19
V
DDQ
Q17
Q18
4
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DESCRIPTION:
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are exceptionally deep, extrememly high
speed, CMOS First-In-First-Out (FIFO) memories with clocked read and write
controls and a flexible Bus-Matching x36/x18/x9 data flow. These FIFOs offer
several key user benefits:
Flexible x36/x18/x9 Bus-Matching on both read and write ports
A user selectable MARK location for retransmit
User selectable I/O structure for HSTL or LVTTL
Asynchronous/Synchronous translation on the read or write ports
The first word data latency period, from the time the first word is written to an
empty FIFO to the time it can be read, is fixed and short.
High density offerings up to 9 Mbit
Bus-Matching TeraSync FIFOs are particularly appropriate for network,
video, telecommunications, data communications and other applications that
need to buffer large amounts of data and match busses of unequal sizes.
Each FIFO has a data input port (D
n
) and a data output port (Q
n
), both of
which can assume either a 36-bit, 18-bit or a 9-bit width as determined by the
state of external control pins Input Width (IW), Output Width (OW), and Bus-
Matching (BM) pin during the Master Reset cycle.
The input port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the input port is
controlled by a Write Clock (WCLK) input and a Write Enable (
WEN) input. Data
present on the Dn data inputs is written into the FIFO on every rising edge of
WCLK when
WEN is asserted. During Asynchronous operation only the WR
input is used to write data into the FIFO. Data is written on a rising edge of WR,
the
WEN input should be tied to its active state, (LOW).
The output port can be selected as either a Synchronous (clocked) interface,
or Asynchronous interface. During Synchronous operation the output port is
controlled by a Read Clock (RCLK) input and Read Enable (
REN) input. Data
is read from the FIFO on every rising edge of RCLK when
REN is asserted.
During Asynchronous operation only the RD input is used to read data from the
FIFO. Data is read on a rising edge of RD, the
REN input should be tied to its
active state, LOW. When Asynchronous operation is selected on the output port
the FIFO must be configured for Standard IDT mode, also the
RCS should be
tied LOW and the
OE input used to provide three-state control of the outputs, Qn.
The output port can be selected for either 2.5V LVTTL or HSTL operation,
this operation is selected by the state of the RHSTL input during a master reset.
An Output Enable (
OE) input is provided for three-state control of the outputs.
A Read Chip Select (
RCS) input is also provided, the RCS input is synchronized
to the read clock, and also provides three-state control of the Qn data outputs.
When
RCS is disabled, the data outputs will be high impedance. During
Asynchronous operation of the output port,
RCS should be enabled, held LOW.
Echo Read Enable,
EREN and Echo Read Clock, ERCLK outputs are
provided. These are outputs from the read port of the FIFO that are required
for high speed data communication, to provide tighter synchronization between
the data being transmitted from the Qn outputs and the data being received by
the input device. Data read from the read port is available on the output bus with
respect to
EREN and ERCLK, this is very useful when data is being read at
high speed. The ERCLK and
EREN outputs are non-functional when the Read
port is setup for Asynchronous mode.
The frequencies of both the RCLK and the WCLK signals may vary from 0
to f
MAX
with complete independence. There are no restrictions on the frequency
of the one clock input with respect to the other.
There are two possible timing modes of operation with these devices: IDT
Standard mode and First Word Fall Through (FWFT) mode.
In IDT Standard mode, the first word written to an empty FIFO will not appear
on the data output lines unless a specific read operation is performed. A read
operation, which consists of activating
REN and enabling a rising RCLK edge,
will shift the word from internal memory to the data output lines.
In FWFT mode, the first word written to an empty FIFO is clocked directly
to the data output lines after three transitions of the RCLK signal. A
REN does
not have to be asserted for accessing the first word. However, subsequent
words written to the FIFO do require a LOW on
REN for access. The state of
the FWFT/SI input during Master Reset determines the timing mode in use.
For applications requiring more data storage capacity than a single FIFO
can provide, the FWFT timing mode permits depth expansion by chaining FIFOs
in series (i.e. the data outputs of one FIFO are connected to the corresponding
data inputs of the next). No external logic is required.
These FIFOs have five flag pins,
EF/OR (Empty Flag or Output Ready),
FF/IR (Full Flag or Input Ready), HF (Half-full Flag), PAE (Programmable
Almost-Empty flag) and
PAF (Programmable Almost-Full flag). The EF and FF
functions are selected in IDT Standard mode. The
IR and OR functions are
selected in FWFT mode.
HF, PAE and PAF are always available for use,
irrespective of timing mode.
PAE and PAF can be programmed independently to switch at any point in
memory. Programmable offsets determine the flag switching threshold and can
be loaded by two methods: parallel or serial. Eight default offset settings are also
provided, so that
PAE can be set to switch at a predefined number of locations
from the empty boundary and the
PAF threshold can also be set at similar
predefined values from the full boundary. The default offset values are set during
Master Reset by the state of the FSEL0, FSEL1, and
LD pins.
For serial programming,
SEN together with LD on each rising edge of
SCLK, are used to load the offset registers via the Serial Input (SI). For parallel
programming,
WEN together with LD on each rising edge of WCLK, are used
to load the offset registers via D
n
.
REN together with LD on each rising edge
of RCLK can be used to read the offsets in parallel from Q
n
regardless of whether
serial or parallel offset loading has been selected.
During Master Reset (
MRS) the following events occur: the read and write
pointers are set to the first location of the FIFO. The FWFT pin selects IDT
Standard mode or FWFT mode.
The Partial Reset (
PRS) also sets the read and write pointers to the first
location of the memory. However, the timing mode, programmable flag
programming method, and default or programmed offset settings existing before
Partial Reset remain unchanged. The flags are updated according to the timing
mode and offsets in effect.
PRS is useful for resetting a device in mid-operation,
when reprogramming programmable flags would be undesirable.
It is also possible to select the timing mode of the
PAE (Programmable Almost-
Empty flag) and
PAF (Programmable Almost-Full flag) outputs. The timing
modes can be set to be either asynchronous or synchronous for the
PAE and
PAF flags.
If asynchronous
PAE/PAF configuration is selected, the PAE is asserted
LOW on the LOW-to-HIGH transition of RCLK.
PAE is reset to HIGH on the LOW-
to-HIGH transition of WCLK. Similarly, the
PAF is asserted LOW on the LOW-
to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH
transition of RCLK.
If synchronous
PAE/PAF configuration is selected , the PAE is asserted and
updated on the rising edge of RCLK only and not WCLK. Similarly,
PAF is
asserted and updated on the rising edge of WCLK only and not RCLK. The mode
desired is configured during MasterReset by the state of the Programmable Flag
Mode (PFM) pin.
5
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DESCRIPTION (CONTINUED)
This device includes a Retransmit from Mark feature that utilizes two control
inputs, MARK and ,
RT (Retransmit). If the MARK input is enabled with respect
to the RCLK, the memory location being read at that point will be marked. Any
subsequent retransmit operation,
RT goes LOW, will reset the read pointer to
this `marked' location.
The device can be configured with different input and output bus widths as
shown in Table 1.
A Big-Endian/Little-Endian data word format is provided. This function is
useful when data is written into the FIFO in long word format (x36/x18) and read
out of the FIFO in small word (x18/x9) format. If Big-Endian mode is selected,
then the most significant byte (word) of the long word written into the FIFO will
be read out of the FIFO first, followed by the least significant byte. If Little-Endian
format is selected, then the least significant byte of the long word written into the
FIFO will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (
BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
The Interspersed/Non-Interspersed Parity (IP) bit function allows the user
to select the parity bit in the word loaded into the parallel port (D
0
-Dn) when
programming the flag offsets. If Interspersed Parity mode is selected, then the
FIFO will assume that the parity bit is located in bit positions D8, D17, D26 and
D35 during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D8, D17 and D26 are assumed to be valid bits
and D32, D33, D34 and D35 are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
If, at any time, the FIFO is not actively performing an operation, the chip will
automatically power down. Once in the power down state, the standby supply
current consumption is minimized. Initiating any operation (by activating control
inputs) will immediately take the device out of the power down state.
Both an Asynchronous Output Enable pin (
OE) and Synchronous Read
Chip Select pin (
RCS) are provided on the FIFO. The Synchronous Read Chip
Select is synchronized to the RCLK. Both the output enable and read chip select
control the output buffer of the FIFO, causing the buffer to be either HIGH
impedance or LOW impedance.
A JTAG test port is provided, here the FIFO has fully functional Boundary
Scan feature, compliant with IEEE 1449.1 Standard Test Access Port and
Boundary Scan Architecture.
The TeraSync FIFO has the capability of operating its ports (write and/or
read) in either LVTTL or HSTL mode, each ports selection independent of the
other. The write port selection is made via WHSTL and the read port selection
via RHSTL. An additional input SHSTL is also provided, this allows the user
to select HSTL operation for other pins on the device (not associated with the
write or read ports).
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 are fabricated using IDT's high speed sub-
micron CMOS technology.
6
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
BM
I W
OW
Write Port Width
Read Port Width
L
L
L
x36
x36
H
L
L
x36
x18
H
L
H
x36
x9
H
H
L
x18
x36
H
H
H
x9
x36
TABLE 1 -- BUS-MATCHING CONFIGURATION MODES
NOTE:
1. Pin status during Master Reset.
Figure 1. Single Device Configuration Signal Flow Diagram
(x36, x18, x9) DATA OUT (Q
0
- Q
n
)
(x36, x18, x9) DATA IN (D
0
- D
n
)
MASTER RESET (
MRS)
READ CLOCK (RCLK/RD)
READ ENABLE (
REN)
OUTPUT ENABLE (
OE)
EMPTY FLAG/OUTPUT READY (
EF/OR)
PROGRAMMABLE ALMOST-EMPTY (
PAE)
WRITE CLOCK (WCLK/WR)
WRITE ENABLE (
WEN)
LOAD (
LD)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE ALMOST-FULL (
PAF)
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
PARTIAL RESET (
PRS)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
RT)
5907 drw03
HALF-FULL FLAG (
HF)
SERIAL ENABLE(
SEN)
INPUT WIDTH (IW)
OUTPUT WIDTH (OW)
BIG-ENDIAN/LITTLE-ENDIAN (
BE)
INTERSPERSED/
NON-INTERSPERSED PARITY (IP)
BUS-
MATCHING
(BM)
SERIAL CLOCK (SCLK)
MARK
READ CHIP SELECT (
RCS)
RCLK ECHO, ERCLK
REN ECHO, EREN
WRITE CHIP SELECT (
WCS)
7
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN DESCRIPTION
ASYR
(1)
Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous read operation for the output port. A LOW
Read Port
INPUT
will select Asynchronous operation. If Asynchronous is selected the FIFO must operate in IDT Standard mode.
ASYW
(1)
Asynchronous
LVTTL
A HIGH on this input during Master Reset will select Synchronous write operation for the input port. A LOW
Write Port
INPUT
will select Asynchronous operation.
BE
(1)
Big-Endian/
LVTTL
During Master Reset, a LOW on
BE will select Big-Endian operation. A HIGH on BE during Master Reset
Little-Endian
INPUT
will select Little-Endian format.
BM
(1)
Bus-Matching
LVTTL
BM works with IW and OW to select the bus sizes for both write and read ports. See Table 1 for bus size
INPUT
configuration.
D
0
D
35
Data Inputs
HSTL-LVTTL Data inputs for a 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, the unused input pins should be tied to GND.
INPUT
EF/OR
Empty Flag/
HSTL-LVTTL In the IDT Standard mode, the
EF function is selected. EF indicates whether or not the FIFO memory is empty.
Output Ready
OUTPUT
In FWFT mode, the
OR function is selected. OR indicates whether or not there is valid data available at the
outputs.
ERCLK RCLK Echo
HSTL-LVTTL Read clock Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
EREN
Read Enable Echo HSTL-LVTTL Read Enable Echo output, only available when the Read is setup for Synchronous mode.
OUTPUT
FF/IR
Full Flag/
HSTL-LVTTL In the IDT Standard mode, the
FF function is selected. FF indicates whether or not the FIFO memory is
Input Ready
OUTPUT
full. In the FWFT mode, the
IR function is selected. IR indicates whether or not there is space available for
writing to the FIFO memory.
FSEL0
(1)
Flag Select Bit 0
LVTTL
During Master Reset, this input along with FSEL1 and the
LD pin, will select the default offset values for the
INPUT
programmable flags
PAE and PAF. There are up to eight possible settings available.
FSEL1
(1)
Flag Select Bit 1
LVTTL
During Master Reset, this input along with FSEL0 and the
LD pin will select the default offset values for the
INPUT
programmable flags
PAE and PAF. There are up to eight possible settings available.
FWFT/
First Word Fall
HSTL-LVTTL During Master Reset, selects First Word Fall Through or IDT Standard mode. After Master Reset, this pin
SI
Through/Serial In
INPUT
functions as a serial input for loading offset registers. If Asynchronous operation of the read port has been
selected then the FIFO must be set-up in IDT Standard mode.
HF
Half-Full Flag
HSTL-LVTTL
HF indicates whether the FIFO memory is more or less than half-full.
OUTPUT
IP
(1)
Interspersed Parity
LVTTL
During Master Reset, a LOW on IP will select Non-Interspersed Parity mode. A HIGH will select Interspersed
INPUT
Parity mode.
IW
(1)
Input Width
LVTTL
This pin, along with OW and BM, selects the bus width of the write port. See Table 1 for bus size configuration.
INPUT
LD
Load
HSTL-LVTTL This is a dual purpose pin. During Master Reset, the state of the
LD input along with FSEL0 and FSEL1,
INPUT
determines one of eight default offset values for the
PAE and PAF flags, along with the method by which these
offset registers can be programmed, parallel or serial (see Table 2). After Master Reset, this pin enables writing
to and reading from the offset registers.
MARK
Mark for Retransmit HSTL-LVTTL When this pin is asserted the current location of the read pointer will be marked. Any subsequent Retransmit
INPUT
operation will reset the read pointer to this position.
MRS
Master Reset
HSTL-LVTTL
MRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Master
INPUT
Reset, the FIFO is configured for either FWFT or IDT Standard mode, Bus-Matching configurations,
Synchronous/Asynchronous operation of the read or write port, one of eight programmable flag default settings,
serial or parallel programming of the offset settings, Big-Endian/Little-Endian format, zero latency timing mode,
interspersed parity, and synchronous versus asynchronous programmable flag timing modes.
OE
Output Enable
HSTL-LVTTL
OE provides Asynchronous three-state control of the data outputs, Q
n.
During a Master or Partial Reset the
INPUT
OE input is the only input that provide High-Impedance control of the data outputs.
OW
(1)
Output Width
LVTTL
This pin, along with IW and BM, selects the bus width of the read port. See Table 1 for bus size configuration.
INPUT
PAE
Programmable
HSTL-LVTTL
PAE goes LOW if the number of words in the FIFO memory is less than offset n, which is stored in the Empty
Almost-Empty Flag
OUTPUT
Offset register.
PAE goes HIGH if the number of words in the FIFO memory is greater than or equal to offset n.
PAF
Programmable
HSTL-LVTTL
PAF goes HIGH if the number of free locations in the FIFO memory is more than offset m, which is stored in
Almost-Full Flag
OUTPUT
the Full Offset register.
PAF goes LOW if the number of free locations in the FIFO memory is less than or equal
to m.
PFM
(1)
Programmable
LVTTL
During Master Reset, a LOW on PFM will select Asynchronous Programmable flag timing mode. A HIGH on
Flag Mode
INPUT
PFM will select Synchronous Programmable flag timing mode.
Symbol
Name
I/O TYPE
Description
8
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
PRS
Partial Reset
HSTL-LVTTL
PRS initializes the read and write pointers to zero and sets the output register to all zeroes. During Partial Reset,
INPUT
the existing mode (IDT or FWFT), programming method (serial or parallel), and programmable flag settings
are all retained.
Q
0
Q
35
Data Outputs
HSTL-LVTTL Data outputs for an 36-, 18- or 9-bit bus. When in 18- or 9-bit mode, any unused output pins should not
OUTPUT
be connected. Outputs are not 5V tolerant regardless of the state of
OE and RCS.
RCLK/
Read Clock/
HSTL-LVTTL If Synchronous operation of the read port has been selected, when enabled by
REN, the rising edge of RCLK
RD
Read Stobe
INPUT
reads data from the FIFO memory and offsets from the programmable registers. If
LD is LOW, the values
loaded into the offset registers is output on a rising edge of RCLK.If Asynchronous operation of the read
port has been selected, a rising edge on RD reads data from the FIFO in an Asynchronous manner.
REN
should be tied LOW.
RCS
Read Chip Select
HSTL-LVTTL
RCS provides synchronous control of the read port and output impedance of Qn, synchronous to RCLK. During
INPUT
a Master Reset or Partial Reset the
RCS input is don't care, if OE is LOW the data outputs will be Low-Impedance
regardless of
RCS.
REN
Read Enable
HSTL-LVTTL If Synchronous operation of the read port has been selected,
REN enablesRCLK for reading data from the
INPUT
FIFO memory and offset registers. If Asynchronous operation of the read port has been selected, the
REN
input should be tied LOW.
RHSTL
(1)
Read Port HSTL
LVTTL
This pin is used to select HSTL or 2.5v LVTTL outputs for the FIFO. If HSTL or eHSTL outputs are
Select
INPUT
required, this input must be tied HIGH. Otherwise it should be tied LOW.
RT
Retransmit
HSTL-LVTTL
RT asserted on the rising edge of RCLK initializes the READ pointer to zero, sets the EF flag to LOW (OR to
INPUT
HIGH in FWFT mode) and doesn't disturb the write pointer, programming method, existing timing mode
or programmable flag settings. If a mark has been set via the MARK input pin, then the read pointer will jump
to the `mark' location.
SCLK
Serial Clock
HSTL-LVTTL A rising edge on SCLK will clock the serial data present on the SI input into the offset registers providing that
INPUT
SEN is enabled.
SEN
Serial Enable
HSTL-LVTTL
SEN enables serial loading of programmable flag offsets.
INPUT
SHSTL
System HSTL
LVTTL
All inputs not associated with the write or read port can be selected for HSTL operation via the SHSTL input.
Select
INPUT
TCK
(2)
JTAG Clock
HSTL-LVTTL Clock input for JTAG function. One of four terminals required by IEEE Standard 1149.1-1990. Test operations
INPUT
of the device are synchronous to TCK. Data from TMS and TDI are sampled on the rising edge of TCK and
outputs change on the falling edge of TCK. If the JTAG function is not used this signal needs to be tied to GND.
TDI
(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Input
INPUT
test data serially loaded via the TDI on the rising edge of TCK to either the Instruction Register, ID Register
and Bypass Register. An internal pull-up resistor forces TDI HIGH if left unconnected.
TDO
(2)
JTAG Test Data
HSTL-LVTTL One of four terminals required by IEEE Standard 1149.1-1990. During the JTAG boundary scan operation,
Output
OUTPUT
test data serially loaded output via the TDO on the falling edge of TCK from either the Instruction Register, ID
Register and Bypass Register. This output is high impedance except when shifting, while in SHIFT-DR and
SHIFT-IR controller states.
TMS
(2)
JTAG Mode
HSTL-LVTTL TMS is a serial input pin. One of four terminals required by IEEE Standard 1149.1-1990. TMS directs the
Select
INPUT
the device through its TAP controller states. An internal pull-up resistor forces TMS HIGH if left unconnected.
TRST
(2)
JTAG Reset
HSTL-LVTTL
TRST is an asynchronous reset pin for the JTAG controller. The JTAG TAP controller does not automatically
INPUT
reset upon power-up, thus it must be reset by either this signal or by setting TMS= HIGH for five TCK cycles.
If the TAP controller is not properly reset then the FIFO outputs will always be in high-impedance. If the JTAG
function is used but the user does not want to use
TRST, then TRST can be tied with MRS to ensure proper
FIFO operation. If the JTAG function is not used then this signal needs to be tied to GND.
WEN
Write Enable
HSTL-LVTTL When Synchronous operation of the write port has been selected,
WEN enables WCLK for writing data into
INPUT
theFIFO memory and offset registers. If Asynchronous operation of the write port has been selected, the
WEN input should be tied LOW.
WCS
Write Chip Select
HSTL-LVTTL The
WCS pin can be regarded as a second WEN input, enabling/disabling write operations.
INPUT
WCLK/
Write Clock/
HSTL-LVTTL If Synchronous operation of the write port has been selected, when enabled by
WEN, the rising edge of WCLK
WR
Write Strobe
INPUT
writes data into the FIFO. If Asynchronous operation of the write port has been selected, WR writes data into
the FIFO on a rising edge in an Asynchronous manner, (
WEN should be tied to its active state).
9
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
NOTES:
1. Inputs should not change state after Master Reset.
2. These pins are for the JTAG port. Please refer to pages 31-34 and Figures 6-8.
WHSTL
(1)
Write Port HSTL
LVTTL
This pin is used to select HSTL or 2.5V LVTTL inputs for the FIFO. If HSTL inputs are required, this input must
Select
INPUT
be tied HIGH. Otherwise it should be tied LOW.
Vcc
+2.5v Supply
I
These are Vcc supply inputs and must be connected to the 2.5V supply rail.
GND
Ground Pin
I
These are Ground pins an dmust be connected to the GND rail.
Vref
Reference
I
This is a Voltage Reference input and must be connected to a voltage level determined from the table,
Voltage
"Recommended DC Operating Conditions". This provides the reference voltage when using HSTL class
inputs. If HSTL class inputs are not being used, this pin should be tied LOW.
V
DDQ
O/P Rail Voltage
I
This pin should be tied to the desired voltage rail for providing power to the output drivers.
PIN DESCRIPTION (CONTINUED)
Symbol
Name
I/O TYPE
Description
10
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Symbol
Rating
Commercial
Unit
V
TERM
Terminal Voltage
0.5 to +3.6
(2)
V
with respect to GND
T
STG
Storage Temperature
55 to +125
C
I
OUT
DC Output Current
50 to +50 mA
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage
2.375
2.5
2.625
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage
LVTTL
1.7
--
3.45
V
eHSTL
V
REF
+0.2
--
V
DDQ
+0.3
V
HSTL
V
REF
+0.2
--
V
DDQ
+0.3
V
V
IL
Input Low Voltage
LVTTL
-0.3
--
0.7
V
eHSTL
-0.3
--
V
REF
-0.2
V
HSTL
-0.3
--
V
REF
-0.2
V
V
REF
(1)
Voltage Reference Input
eHSTL
0.8
0.9
1.0
V
HSTL
0.68
0.75
0.9
V
T
A
Operating Temperature Commercial
0
--
70
C
T
A
Operating Temperature Industrial
-40
--
85
C
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED DC OPERATING CONDITIONS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. Compliant with JEDEC JESD8-5. V
CC
terminal only.
NOTE:
1. V
REF
is only required for HSTL or eHSTL inputs. V
REF
should be tied LOW for LVTTL operation.
2. Outputs are not 3.3V tolerant.
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
(2,3)
Input
V
IN
= 0V
10
(3)
pF
Capacitance
C
OUT
(1,2)
Output
V
OUT
= 0V
10
pF
Capacitance
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
NOTES:
1. With output deselected, (
OE
V
IH
).
2. Characterized values, not currently tested.
3. C
IN
for Vref is 20pF.
11
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DC ELECTRICAL CHARACTERISTICS
(Commercial: V
CC
= 2.5V 0.125V, T
A
= 0
C to +70C;Industrial: V
CC
= 2.5V 0.125V, T
A
= -40
C to +85C)
Symbol
Parameter
Min.
Max.
Unit
I
LI
Input Leakage Current
10
10
A
I
LO
Output Leakage Current
10
10
A
V
OH
(5)
Output Logic "1" Voltage,
I
OH
= 8 mA @V
DDQ
= 2.5V
0.125V (LVTTL)
V
DDQ
-0.4
--
V
I
OH
= 8 mA @V
DDQ
= 1.8V
0.1V (eHSTL)
V
DDQ
-0.4
--
V
I
OH
= 8 mA @V
DDQ
= 1.5V
0.1V (HSTL)
V
DDQ
-0.4
--
V
V
OL
Output Logic "0" Voltage,
I
OL
= 8 mA
@V
DDQ
= 2.5V
0.125V (LVTTL)
--
0.4V
V
I
OL
= 8 mA
@V
DDQ
= 1.8V
0.1V (eHSTL)
--
0.4V
V
I
OL
= 8 mA
@V
DDQ
= 1.5V
0.1V (HSTL)
--
0.4V
V
IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695
I
CC1
(1,2)
Active V
CC
Current (V
CC
= 2.5V)
I/O = LVTTL
--
40
mA
I/O = HSTL
--
70
mA
I/O = eHSTL
--
70
mA
I
CC2
(1)
Standby V
CC
Current (V
CC
= 2.5V)
I/O = LVTTL
--
10
mA
I/O = HSTL
--
50
mA
I/O = eHSTL
--
50
mA
IDT72T36105/72T36115/72T36125
I
CC1
(1,2)
Active V
CC
Current (V
CC
= 2.5V)
I/O = LVTTL
--
60
mA
I/O = HSTL
--
90
mA
I/O = eHSTL
--
90
mA
I
CC2
(1)
Standby V
CC
Current (V
CC
= 2.5V)
I/O = LVTTL
--
20
mA
I/O = HSTL
--
70
mA
I/O = eHSTL
--
70
mA
NOTES:
1. Both WCLK and RCLK toggling at 20MHz. Data inputs toggling at 10MHz.
WCS = HIGH, REN or RCS = HIGH.
2. For the IDT72T36105/72T36115/72T36125, typical I
CC1
calculation (with data outputs in Low-Impedance)
:
for LVTTL I/O I
CC1
(mA) = 1.3 x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O I
CC1
(mA) = 30 + (1.3 x fs), fs = WCLK = RCLK frequency (in MHz)
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695, typical I
CC1
calculation (with data outputs in Low-Impedance)
:
for LVTTL I/O I
CC1
(mA) = 0.7mA x fs, fs = WCLK = RCLK frequency (in MHz)
for HSTL or eHSTL I/O I
CC1
(mA) = 30 + (0.7 x fs), fs = WCLK = RCLK frequency (in MHz).
3. For all devices, typical I
DDQ
calculation:
with data outputs in High-Impedance: I
DDQ
(mA) = 0.15 x fs, fs = WCLK = RCLK frequency (in MHz)
with data outputs in Low-Impedance: I
DDQ
(mA) = (C
L
x V
DDQ
x fs
x N)/2000
fs = WCLK = RCLK frequency (in MHz), V
DDQ
= 2.5V for LVTTL; 1.5V for HSTL; 1.8V for eHSTL, C
L
= capacitive load (pf), t
A
= 25C,
N = Number of outputs switching.
4. Total Power consumed: PT = (V
CC
x I
CC
) + V
DDQ
x I
DDQ
).
5. Outputs are not 3.3V tolerant.
12
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
AC ELECTRICAL CHARACTERISTICS
(1)
-- SYNCHRONOUS TIMING
(Commercial: V
CC
= 2.5V
5%, T
A
= 0
C to +70C;Industrial: V
CC
= 2.5V
5%, T
A
= -40
C to +85C)
NOTES:
1. All AC timings apply to both Standard IDT mode and First Word Fall Through mode.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
4. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
Commercial
Com'l & Ind'l
Commercial
IDT72T3645L4-4
IDT72T3645L5
IDT72T3645L6-7
IDT72T3645L10
IDT72T3655L4-4
IDT72T3655L5
IDT72T3655L6-7
IDT72T3655L10
IDT72T3665L4-4
IDT72T3665L5
IDT72T3665L6-7
IDT72T3665L10
IDT72T3675L4-4
IDT72T3675L5
IDT72T3675L6-7
IDT72T3675L10
IDT72T3685L4-4
IDT72T3685L5
IDT72T3685L6-7
IDT72T3685L10
IDT72T3695L4-4
IDT72T3695L5
IDT72T3695L6-7
IDT72T3695L10
IDT72T36105L4-4
IDT72T36105L5
IDT72T36105L6-7
IDT72T36105L10
IDT72T36115L4-4
IDT72T36115L5
IDT72T36115L6-7
IDT72T36115L10
IDT72T36125L4-4
IDT72T36125L5
IDT72T36125L6-7
IDT72T36125L10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
C
Clock Cycle Frequency (Synchronous)
--
225
--
200
--
150
100
MHz
t
A
Data Access Time
0.6
3.4
0.6
3.6
0.6
3.8
0.6
4.5
ns
t
CLK
Clock Cycle Time
4.44
--
5
--
6.7
--
10
--
ns
t
CLKH
Clock High Time
2.0
--
2.3
--
2.8
--
4.5
--
ns
t
CLKL
Clock Low Time
2.0
--
2.3
--
2.8
--
4.5
--
ns
t
DS
Data Setup Time
1.2
--
1.5
--
2.0
--
3.0
--
ns
t
DH
Data Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
ENS
Enable Setup Time
1.2
--
1.5
--
2.0
--
3.0
--
ns
t
ENH
Enable Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
LDS
Load Setup Time
1.2
--
1.5
--
2.0
--
3.0
--
ns
t
LDH
Load Hold Time
0.5
--
0.5
--
0.5
--
0.5
--
ns
t
WCSS
WCS setup time
1.2
--
1.5
--
2.0
--
3.0
--
ns
t
WCSH
WCS hold time
0.5
--
0.5
--
0.5
--
0.5
--
ns
f
S
Clock Cycle Frequency (SCLK)
--
10
--
10
--
10
--
10
MHz
t
SCLK
Serial Clock Cycle
100
--
100
--
100
--
100
--
ns
t
SCKH
Serial Clock High
45
--
45
--
45
--
45
--
ns
t
SCKL
Serial Clock Low
45
--
45
--
45
--
45
--
ns
t
SDS
Serial Data In Setup
15
--
15
--
15
--
15
--
ns
t
SDH
Serial Data In Hold
5
--
5
--
5
--
5
--
ns
t
SENS
Serial Enable Setup
5
--
5
--
5
--
5
--
ns
t
SENH
Serial Enable Hold
5
--
5
--
5
--
5
--
ns
t
RS
Reset Pulse Width
(2)
30
--
30
--
30
--
30
--
ns
t
RSS
Reset Setup Time
15
--
15
--
15
--
15
--
ns
t
HRSS
HSTL Reset Setup Time
4
--
4
--
4
--
4
--
s
t
RSR
Reset Recovery Time
10
--
10
--
10
--
10
--
ns
t
RSF
Reset to Flag and Output Time
--
10
--
12
--
15
--
15
ns
t
WFF
Write Clock to
FF or IR
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
REF
Read Clock to
EF or OR
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
PAFS
Write Clock to Synchronous Programmable Almost-Full Flag
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
PAES
Read Clock to Synchronous Programmable Almost-Empty Flag
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
ERCLK
RCLK to Echo RCLK output
--
3.8
--
4
--
4.3
--
5
ns
t
CLKEN
RCLK to Echo
REN output
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
RCSLZ
RCLK to Active from High-Z
(3)
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
RCSHZ
RCLK to High-Z
(3)
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
SKEW1
Skew time between RCLK and WCLK for
EF/OR and FF/IR
3.5
--
4
--
5
--
7
--
ns
t
SKEW2
Skew time between RCLK and WCLK for
PAE and PAF
4
--
5
--
6
--
8
--
ns
13
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
AC ELECTRICAL CHARACTERISTICS -- ASYNCHRONOUS TIMING
(Commercial: V
CC
= 2.5V
5%, T
A
= 0
C to +70C;Industrial: V
CC
= 2.5V
5%, T
A
= -40
C to +85C)
Commercial
Com'l & Ind'l
Commercial
IDT72T3645L4-4
IDT72T3645L5
IDT72T3645L6-7
IDT72T3645L10
IDT72T3655L4-4
IDT72T3655L5
IDT72T3655L6-7
IDT72T3655L10
IDT72T3665L4-4
IDT72T3665L5
IDT72T3665L6-7
IDT72T3665L10
IDT72T3675L4-4
IDT72T3675L5
IDT72T3675L6-7
IDT72T3675L10
IDT72T3685L4-4
IDT72T3685L5
IDT72T3685L6-7
IDT72T3685L10
IDT72T3695L4-4
IDT72T3695L5
IDT72T3695L6-7
IDT72T3695L10
IDT72T36105L4-4
IDT72T36105L5
IDT72T36105L6-7
IDT72T36105L10
IDT72T36115L4-4
IDT72T36115L5
IDT72T36115L6-7
IDT72T36115L10
IDT72T36125L4-4
IDT72T36125L5
IDT72T36125L6-7
IDT72T36125L10
Symbol
Parameter
Min.
Max.
Min.
Max.
Min.
Max.
Min.
Max.
Unit
f
A
Cycle Frequency (Asynchronous)
--
100
--
83
--
66
--
50
MHz
t
AA
Data Access Time
0.6
8
0.6
10
0.6
12
0.6
14
ns
t
CYC
Cycle Time
10
--
12
--
15
--
20
--
ns
t
CYH
Cycle HIGH Time
4.5
--
5
--
7
--
8
--
ns
t
CYL
Cycle LOW Time
4.5
--
5
--
7
--
8
--
ns
t
RPE
Read Pulse after
EF HIGH
8
--
10
--
12
--
14
--
ns
t
FFA
Clock to Asynchronous
FF
--
8
--
10
--
12
--
14
ns
t
EFA
Clock to Asynchronous
EF
--
8
--
10
--
12
--
14
ns
t
PAFA
Clock to Asynchronous Programmable Almost-Full Flag
--
8
--
10
--
12
--
14
ns
t
PAEA
Clock to Asynchronous Programmable Almost-Empty Flag
--
8
--
10
--
12
--
14
ns
t
OLZ
Output Enable to Output in Low Z
(1)
0
--
0
--
0
--
0
--
ns
t
OE
Output Enable to Output Valid
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
OHZ
Output Enable to Output in High Z
(1)
--
3.4
--
3.6
--
3.8
--
4.5
ns
t
HF
Clock to
HF
--
8
--
10
--
12
--
14
ns
NOTES:
1. Values guaranteed by design, not currently tested.
2. Industrial temperature range product for the 5ns speed grade is available as a standard device. All other speed grades are available by special order.
14
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Input Pulse Levels
0.25 to 1.25V
Input Rise/Fall Times
0.4ns
Input Timing Reference Levels
0.75
Output Reference Levels
V
DDQ
/2
HSTL
1.5V AC TEST CONDITIONS
Figure 2b. Lumped Capacitive Load, Typical Derating
AC TEST LOADS
Figure 2a. AC Test Load
Input Pulse Levels
0.4 to 1.4V
Input Rise/Fall Times
0.4ns
Input Timing Reference Levels
0.9
Output Reference Levels
V
DDQ
/2
EXTENDED HSTL
1.8V AC TEST CONDITIONS
Input Pulse Levels
GND to 2.5V
Input Rise/Fall Times
1ns
Input Timing Reference Levels
V
CC
/2
Output Reference Levels
V
DDQ
/2
2.5V LVTTL
2.5V AC TEST CONDITIONS
5907 drw04
50
V
DDQ
/2
I/O
Z
0
= 50
5907 drw04a
6
5
4
3
2
1
20 30 50
80 100
200
Capacitance (pF)
t
CD
(Typical, ns)
NOTE:
1. V
DDQ
= 1.5V.
NOTE:
1. V
DDQ
= 1.8V.
NOTE:
1. For LVTTL V
CC
= V
DDQ
.
15
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
OUTPUT ENABLE & DISABLE TIMING
V
IH
OE
V
IL
t
OE &
t
OLZ
V
CC
2
V
CC
2
100mV
100mV
t
OHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
V
CC
2
5907 drw04b
Output
Enable
Output
Disable
READ CHIP SELECT ENABLE & DISABLE TIMING
V
IH
RCS
V
IL
t
ENS
t
ENH
t
RCSLZ
RCLK
V
CC
2
V
CC
2
100mV
100mV
t
RCSHZ
100mV
100mV
Output
Normally
LOW
Output
Normally
HIGH
V
OL
V
OH
V
CC
2
V
CC
2
5907 drw04c
NOTES:
1.
REN is HIGH.
2.
RCS is LOW.
NOTES:
1.
REN is HIGH.
2.
OE is LOW.
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
FUNCTIONAL DESCRIPTION
TIMING MODES: IDT STANDARD vs FIRST WORD FALL THROUGH
(FWFT) MODE
The IDT72T3645/55/65/75/85/95/105/115/125 support two different tim-
ing modes of operation: IDT Standard mode or First Word Fall Through
(FWFT) mode. The selection of which mode will operate is determined during
Master Reset, by the state of the FWFT/SI input.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or not
there are any words present in the FIFO. It also uses the Full Flag function (
FF)
to indicate whether or not the FIFO has any free space for writing. In IDT
Standard mode, every word read from the FIFO, including the first, must be
requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR) to indicate whether or not there
is valid data at the data outputs (Q
n)
. It also uses Input Ready (
IR) to indicate
whether or not the FIFO has any free space for writing. In the FWFT mode, the
first word written to an empty FIFO goes directly to Q
n
after three RCLK rising
edges,
REN = LOW is not necessary. Subsequent words must be accessed
using the Read Enable (
REN) and RCLK.
Various signals, both input and output signals operate differently depending
on which timing mode is in effect.
IDT STANDARD MODE
In this mode, the status flags,
FF, PAF, HF, PAE, and EF operate in the
manner outlined in Table 3. To write data into to the FIFO, Write Enable (
WEN)
must be LOW. Data presented to the DATA IN lines will be clocked into the FIFO
on subsequent transitions of the Write Clock (WCLK). After the first write is
performed, the Empty Flag (
EF) will go HIGH. Subsequent writes will continue
to fill up the FIFO. The Programmable Almost-Empty flag (
PAE) will go HIGH
after n + 1 words have been loaded into the FIFO, where n is the empty offset
value. The default setting for these values are stated in the footnote of Table 2.
This parameter is also user programmable. See section on Programmable Flag
Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full flag (
HF) would toggle to LOW once
the 513rd word for IDT72T3645, 1,025th word for IDT72T3655, 2,049th word
for IDT72T3665, 4,097th word for IDT72T3675, 8,193th word for the
IDT72T3685, 16,385th word for the IDT72T3695, 32,769th word for the
IDT72T36105, 65,537th word for the IDT72T36115 and 131,073rd word for
the IDT72T36125, respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the Programmable Almost-Full flag (
PAF) to go
LOW. Again, if no reads are performed, the
PAF will go LOW after (1,024-m)
writes for the IDT72T3645, (2,048-m) writes for the IDT72T3655, (4,096-m)
writes for the IDT72T3665, (8,192-m) writes for the IDT72T3675, (16,384-m)
writes for the IDT72T3685, (32,768-m) writes for the IDT72T3695, (65,536-m)
writes for the IDT72T36105, (131,072-m) writes for the IDT72T36115 and
(262,144-m) writes for the IDT72T36125. The offset "m" is the full offset value.
The default setting for these values are stated in the footnote of Table 2. This
parameter is also user programmable. See section on Programmable Flag
Offset Loading.
When the FIFO is full, the Full Flag (
FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset,
FF will go LOW after D writes
to the FIFO. D = 1,024 writes for the IDT72T3645, 2,048 writes for the
IDT72T3655, 4,096 writes for the IDT72T3665, 8,192 writes for the IDT72T3675,
16,384 writes for the IDT72T3685, 32,768 writes for the IDT72T3695, 65,536
writes for the IDT72T36105, 131,072 writes for the IDT72T36115 and 262,144
writes for the IDT72T36125, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause
PAF and HF to go HIGH at the conditions
described in Table 3. If further read operations occur, without write operations,
PAE will go LOW when there are n words in the FIFO, where n is the empty
offset value. Continuing read operations will cause the FIFO to become empty.
When the last word has been read from the FIFO, the
EF will go LOW inhibiting
further read operations.
REN is ignored when the FIFO is empty.
When configured in IDT Standard mode, the
EF and FF outputs are double
register-buffered outputs.
Relevant timing diagrams for IDT Standard mode can be found in Figure
11, 12, 13 and 18.
FIRST WORD FALL THROUGH MODE (FWFT)
In this mode, the status flags,
IR, PAF, HF, PAE, and OR operate in the
manner outlined in Table 4. To write data into to the FIFO,
WEN must be LOW.
Data presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of WCLK. After the first write is performed, the Output Ready (
OR)
flag will go LOW. Subsequent writes will continue to fill up the FIFO.
PAE will go
HIGH after n + 2 words have been loaded into the FIFO, where n is the empty
offset value. The default setting for these values are stated in the footnote of
Table 2. This parameter is also user programmable. See section on Program-
mable Flag Offset Loading.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the
HF would toggle to LOW once the 514th word
for the IDT72T3645, 1,026th word for the IDT72T3655, 2,050th word for the
IDT72T3665, 4,098th word for the IDT72T3675, 8,194th word for the
IDT72T3685, 16,386th word for the IDT72T3695, 32,770th word for the
IDT72T36105, 65,538th word for the IDT72T36115 and 131,074th word for
the IDT72T36125, respectively was written into the FIFO. Continuing to write
data into the FIFO will cause the
PAF to go LOW. Again, if no reads are
performed, the
PAF will goLOW after (1,025-m) writes for the IDT72T3645,
(2,049-m) writes for the IDT72T3655, (4,097-m) writes for the IDT72T3665
and (8,193-m) writes for the IDT72T3675, (16,385-m) writes for the IDT72T3685,
(32,769-m) writes for the IDT72T3695, (65,537-m) writes for the IDT72T36105,
(131,073-m) writes for the IDT72T36115 and (262,145-m) writes for the
IDT72T36125, where m is the full offset value. The default setting for these values
are stated in the footnote of Table 2.
When the FIFO is full, the Input Ready (
IR) flag will go HIGH, inhibiting further
write operations. If no reads are performed after a reset,
IR will go HIGH after
D writes to the FIFO. D = 1,025 writes for the IDT72T3645, 2,049 writes for
the IDT72T3655, 4,097 writes for the IDT72T3665 and 8,193 writes for the
IDT72T3675,16,385 writes for the IDT72T3685, 32,769 writes for the
IDT72T3695, 65,537 writes for the IDT72T36105, 131,073 writes for the
IDT72T36115 and 262,145 writes for the IDT72T36125, respectively. Note
that the additional word in FWFT mode is due to the capacity of the memory plus
output register.
If the FIFO is full, the first read operation will cause the
IR flag to go LOW.
Subsequent read operations will cause the
PAF and HF to go HIGH at the
conditions described in Table 4. If further read operations occur, without write
operations, the
PAE will go LOW when there are n + 1 words in the FIFO, where
n is the empty offset value. Continuing read operations will cause the FIFO to
become empty. When the last word has been read from the FIFO,
OR will go
HIGH inhibiting further read operations.
REN is ignored when the FIFO is empty.
When configured in FWFT mode, the
OR flag output is triple register-
buffered, and the
IR flag output is double register-buffered.
Relevant timing diagrams for FWFT mode can be found in Figure 14, 15,
16 and 19.
17
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
PROGRAMMING FLAG OFFSETS
Full and Empty Flag offset values are user programmable. The IDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 have internal registers for these offsets. There are eight default offset
values selectable during Master Reset. These offset values are shown in Table
2. Offset values can also be programmed into the FIFO in one of two ways; serial
or parallel loading method. The selection of the loading method is done using
the
LD (Load) pin. During Master Reset, the state of the LD input determines
whether serial or parallel flag offset programming is enabled. A HIGH on
LD
during Master Reset selects serial loading of offset values. A LOW on
LD during
Master Reset selects parallel loading of offset values.
In addition to loading offset values into the FIFO, it is also possible to read
the current offset values. Offset values can be read via the parallel output port
Q
0
-Qn, regardless of the programming mode selected (serial or parallel). It is
not possible to read the offset values in serial fashion.
Figure 3, Programmable Flag Offset Programming Sequence, summaries
the control pins and sequence for both serial and parallel programming modes.
For a more detailed description, see discussion that follows.
The offset registers may be programmed (and reprogrammed) any time
after Master Reset, regardless of whether serial or parallel programming has
been selected. Valid programming ranges are from 0 to D-1.
SYNCHRONOUS vs ASYNCHRONOUS PROGRAMMABLE FLAG
TIMING SELECTION
The IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 can be configured during the Master Reset
cycle with either synchronous or asynchronous timing for
PAF and PAE flags
by use of the PFM pin.
If synchronous
PAF/PAE configuration is selected (PFM, HIGH during
MRS), the PAF is asserted and updated on the rising edge of WCLK only and
not RCLK. Similarly,
PAE is asserted and updated on the rising edge of RCLK
only and not WCLK. For detail timing diagrams, see Figure 23 for synchronous
PAF timing and Figure 24 for synchronous PAE timing.
If asynchronous
PAF/PAE configuration is selected (PFM, LOW during
MRS), the PAF is asserted LOW on the LOW-to-HIGH transition of WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK. Similarly, PAE
is asserted LOW on the LOW-to-HIGH transition of RCLK.
PAE is reset to HIGH
on the LOW-to-HIGH transition of WCLK. For detail timing diagrams, see
Figure 25 for asynchronous
PAF timing and Figure 26 for asynchronous PAE
timing.
IDT72T3645, 72T3655
LD
FSEL1
FSEL0
Offsets n,m
L
H
L
511
L
L
H
255
L
L
L
127
L
H
H
63
H
L
L
31
H
H
L
15
H
L
H
7
H
H
H
3
LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial
(3)
L
X
X
Parallel
(4)
IDT72T3665,72T3675,72T3685,72T3695, 72T36105,
72T36115, 72T36125
LD
FSEL1
FSEL0
Offsets n,m
H
L
L
1,023
L
H
L
511
L
L
H
255
L
L
L
127
L
H
H
63
H
H
L
31
H
L
H
15
H
H
H
7
LD
FSEL1
FSEL0
Program Mode
H
X
X
Serial
(3)
L
X
X
Parallel
(4)
TABLE 2 -- DEFAULT PROGRAMMABLE
FLAG OFFSETS
NOTES:
1. n = empty offset for
PAE.
2. m = full offset for
PAF.
3. As well as selecting serial programming mode, one of the default values will also
be loaded depending on the state of FSEL0 & FSEL1.
4. As well as selecting parallel programming mode, one of the default values will
also be loaded depending on the state of FSEL0 & FSEL1.
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
IDT72T3645
IDT72T3655
0
1 to n
(1)
(n+1) to 1,024
1,025 to (2048-(m+1))
(2048-m) to 2,047
2,048
0
1 to n
(1)
(n+1) to 512
513 to (1,024-(m+1))
(1024-m) to 1,023
1,024
IDT72T3665
0
1 to n
(1)
(n+1) to 2,048
2,049 to (4,096-(m+1))
(4,096-m) to 4,095
4,096
TABLE 3
STATUS FLAGS FOR IDT STANDARD MODE
IDT72T3645
IDT72T3655
0
0
0
1 to n+1
1 to n+1
1 to n+1
(n+2) to 1,025
(n+2) to 2,049
(n+2) to 4,097
1,026 to (2,049-(m+1))
2,050 to (4,097-(m+1))
4,098 to (8,193-(m+1))
(2,049-m) to 2,048
(4,097-m)
to 4,096
(8,193-m)
to 8,192
2,049
4,097
8,193
IDT72T3665
IDT72T3675
0
1 to n+1
(n+2) to 513
514 to (1,025-(m+1))
(1,025-m) to 1,024
1,025
IR
PAF HF PAE OR
L
H
H
L
H
L
H
H
L
L
L
H
H
H
L
L
H
L
H
L
L
L
L
H
L
H
L
L
H
L
Number of
Words in
FIFO
TABLE 4
STATUS FLAGS FOR FWFT MODE
FF PAF HF PAE EF
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
L
L
H
H
5907 drw05
0
1 to n+1
(n+2) to 8,193
8,194 to (16,385-(m+1))
(16,385-m) to 16,384
16,385
IDT72T3685
IDT72T3675
0
1 to n
(1)
(n+1) to 4,096
4,097 to (8,192-(m+1))
(8,192-m) to 8,191
8,192
0
1 to n
(
1)
(n+1) to 8,192
8,193 to (16,384-(m+1))
(16,384-m) to 16,383
16,384
IDT72T3685
Number of
Words in
FIFO
IDT72T36105
0
1 to n
(1)
(n+1) to 32,768
32,769 to (65,536-(m+1))
(65,536-m) to 65,535
65,536
IDT72T36115
0
1 to n
(1)
(n+1) to 65,536
65,537 to (131,072-(m+1))
(131,072-m) to 131,071
131,072
FF PAF HF PAE EF
H
H
H
L
L
H
H
H
L
H
H
H
H
H
H
H
H
L
H
H
H
L
L
H
H
L
L
L
H
H
IDT72T36125
0
1 to n
(1)
(n+1) to 131,072
131,073 to (262,144-(m+1))
262,144
Number of
Words in
FIFO
0
1 to n
(1)
(n+1) to 16,384
16,385 to (32,768-(m+1))
(32,768-m) to 32,767
32,768
IDT72T3695
(262,144-m) to 262,143
0
0
0
1 to n+1
1 to n+1
1 to n+1
IR
PAF HF PAE OR
L
H
H
L
H
L
H
H
L
L
L
H
H
H
L
L
H
L
H
L
L
L
L
H
L
H
L
L
H
L
0
1 to n+1
(n+2) to 16,385
16,386 to (32,769-(m+1))
(32,769-m) to 32,768
32,769
IDT72T3695
Number of
Words in
FIFO
(n+2) to 32,769
32,770 to (65,537-(m+1))
(65,537-m) to 65,536
65,537
(n+2) to 65,537
65,538 to (131,073-(m+1))
(131,073-m) to 131,072
131,073
(n+2) to 131,073
131,074 to (262,145-(m+1))
262,145
(262,145-m) to 262,144
IDT72T36105
IDT72T36115
IDT72T36125
NOTE:
1. See table 2 for values for n, m.
NOTE:
1. See table 2 for values for n, m.
19
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 3. Programmable Flag Offset Programming Sequence
NOTES:
1. The programming method can only be selected at Master Reset.
2. Parallel reading of the offset registers is always permitted regardless of which programming method has been selected.
3. The programming sequence applies to both IDT Standard and FWFT modes.
WCLK
RCLK
X
X
X
X
X
X
X
X
LD
0
0
X
1
1
1
0
WEN
0
1
1
0
X
1
1
REN
1
0
1
X
0
1
1
X
SEN
1
1
1
X
X
X
0
No Operation
Write Memory
Read Memory
No Operation
Parallel write to registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
IDT72T3645, IDT72T3655
IDT72T3665, IDT72T3675
IDT72T3685, IDT72T3695
IDT72T36105, IDT72T36115
IDT72T36125
Parallel read from registers:
Empty Offset (LSB)
Empty Offset (MSB)
Full Offset (LSB)
Full Offset (MSB)
Serial shift into registers:
Ending with Full Offset (MSB)
20 bits for the IDT72T3645
22 bits for the IDT72T3655
24 bits for the IDT72T3665
26 bits for the IDT72T3675
28 bits for the IDT72T3685
30 bits for the IDT72T3695
32 bits for the IDT72T36105
34 bits for the IDT72T36115
36 bits for the IDT72T36125
1 bit for each rising SCLK edge
Starting with Empty Offset (LSB)
5907 drw06
SCLK
X
X
X
X
X
X
X
20
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 3. Programmable Flag Offset Programming Sequence (Continued)
# of Bits Used:
10 bits for the IDT72T3645
11 bits for the IDT72T3655
12 bits for the IDT72T3665
13 bits for the IDT72T3675
14 bits for the IDT72T3685
15 bits for the IDT72T3695
16 bits for the IDT72T36105
17 bits for the IDT72T36115
18 bits for the IDT72T36125
Note: All unused bits of the
LSB & MSB are don't care
5907 drw07
D/Q17
D/Q0
D/Q8
EMPTY OFFSET REGISTER (
PAE)
# of Bits Used
2
3
4
5
6
7
9
10
11
12
13
14
15
16
1st Parallel Offset Write/Read Cycle
2
3
4
5
6
7
8
12
13
14
15
16
17
11
Interspersed
Parity
17
10
1
1
8
D/Q35 D/Q19
9
D/Q17
D/Q0
D/Q8
FULL OFFSET REGISTER (
PAF)
# of Bits Used
2
3
4
5
6
7
9
10
11
12
13
14
15
16
2nd Parallel Offset Write/Read Cycle
2
3
4
5
6
7
8
12
13
14
15
16
17
11
Interspersed
Parity
17
10
1
1
8
9
IDT72T3645/55/65/75/85/95/105/115/125
x36 Bus Width
Non-Interspersed
Parity
Non-Interspersed
Parity
D/Q35 D/Q19
D/Q17
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (
PAE)
Data Inputs/Outputs
# of Bits Used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1st Parallel Offset Write/Read Cycle
Data Inputs/Outputs
2nd Parallel Offset Write/Read Cycle
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET (LSB) REGISTER (
PAF)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q8
D/Q8
16
16
D/Q17
D/Q16
IDT72T3645/55/65/75/85/95/105
x18 Bus Width
D/Q17
D/Q0
D/Q16
EMPTY OFFSET (LSB) REGISTER (
PAE)
Data Inputs/Outputs
# of Bits Used
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
EMPTY OFFSET (MSB) REGISTER (
PAE)
Data Inputs/Outputs
17
16
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
Data Inputs/Outputs
Data Inputs/Outputs
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET (LSB) REGISTER (
PAF)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
1
2
3
4
5
6
7
8
10
11
12
13
14
15
9
FULL OFFSET (MSB) REGISTER (
PAF)
17
Non-Interspersed
Parity
Interspersed
Parity
D/Q0
D/Q0
D/Q0
D/Q8
D/Q8
16
16
17
17
D/Q17 D/Q16
D/Q17
D/Q16
D/Q17 D/Q16
IDT72T36115/72T36125
x18 Bus Width
18
18
18
18
18
18
18
18
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE)
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE)
9
10
11
12
13
14
15
16
D/Q8
D/Q0
FULL OFFSET REGISTER (
PAF)
1
2
3
4
5
6
7
8
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE)
17
5th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER (
PAF)
9
10
11
12
13
14
15
16
6th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
17
FULL OFFSET REGISTER (
PAF)
IDT72T36115/72T36125
x9 Bus Width
18
18
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE)
1
2
3
4
5
6
7
8
1st Parallel Offset Write/Read Cycle
2nd Parallel Offset Write/Read Cycle
3rd Parallel Offset Write/Read Cycle
D/Q8
D/Q0
EMPTY OFFSET REGISTER (
PAE)
9
10
11
12
13
14
15
16
D/Q8
D/Q0
FULL OFFSET REGISTER (
PAF)
1
2
3
4
5
6
7
8
4th Parallel Offset Write/Read Cycle
D/Q8
D/Q0
FULL OFFSET REGISTER (
PAF)
9
10
11
12
13
14
15
16
IDT72T3645/55/65/75/85/95/105
x9 Bus Width
NOTE:
1. Consecutive reads of the offset registers is not permitted. The read operation must be disabled for a minimum of one RCLK cycle in between offset register accesses. (Please
refer to Figure 22, Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes) for more details).
21
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
SERIAL PROGRAMMING MODE
If Serial Programming mode has been selected, as described above, then
programming of
PAE and PAF values can be achieved by using a combination
of the
LD, SEN, SCLK and SI input pins. Programming PAE and PAF proceeds
as follows: when
LD and SEN are set LOW, data on the SI input are written, one
bit for each SCLK rising edge, starting with the Empty Offset LSB and ending
with the Full Offset MSB. A total of 20 bits for the IDT72T3645, 22 bits for the
IDT72T3655, 24 bits for the IDT72T3665, 26 bits for the IDT72T3675, 28 bits
for the IDT72T3685, 30 bits for the IDT72T3695, 32 bits for the IDT72T36105,
34 bits for the IDT72T36115 and 36 bits for the IDT72T36125. See Figure 20,
Serial Loading of Programmable Flag Registers, for the timing diagram for this
mode.
Using the serial method, individual registers cannot be programmed
selectively.
PAE and PAF can show a valid status only after the complete set
of bits (for all offset registers) has been entered. The registers can be
reprogrammed as long as the complete set of new offset bits is entered. When
LD is LOW and SEN is HIGH, no serial write to the registers can occur.
Write operations to the FIFO are allowed before and during the serial
programming sequence. In this case, the programming of all offset bits does not
have to occur at once. A select number of bits can be written to the SI input and
then, by bringing
LD and SEN HIGH, data can be written to FIFO memory via
D
n
by toggling
WEN. When WEN is brought HIGH with LD and SEN restored
to a LOW, the next offset bit in sequence is written to the registers via SI. If an
interruption of serial programming is desired, it is sufficient either to set
LD LOW
and deactivate
SEN or to set SEN LOW and deactivate LD. Once LD and SEN
are both restored to a LOW level, serial offset programming continues.
From the time serial programming has begun, neither programmable flag
will be valid until the full set of bits required to fill all the offset registers has been
written. Measuring from the rising SCLK edge that achieves the above criteria;
PAF will be valid after three more rising WCLK edges plus t
PAF
,
PAE will be valid
after the next three rising RCLK edges plus t
PAE
.
It is only possible to read the flag offset values via the parallel output port Qn.
PARALLEL MODE
If Parallel Programming mode has been selected, as described above, then
programming of
PAE and PAF values can be achieved by using a combination
of the
LD, WCLK , WEN and D
n
input pins. Programming
PAE and PAF
proceeds as follows:
LD and WEN must be set LOW. When programming the
Offset Registers of the TeraSync FIFO's the number of programming cycles will
be based on the bus width, the following rules apply:
When a 36 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, 2 enabled write cycles are required to
program the offset registers, (1 per offset). Data on the inputs Dn are written into
the Empty Offset Register on the first LOW-to-HIGH transition of WCLK. Upon
the second LOW-to-HIGH transition of WCLK, data are written into the Full Offset
Register. The third transition of WCLK writes, once again, to the Empty Offset
Register.
When an 18 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 2 enabled write cycles are required to program the offset registers,
(1 per offset). Data on the inputs Dn are written into the Empty Offset Register
on the first LOW-to-HIGH transition of WCLK. Upon the second LOW-to-HIGH
transition of WCLK, data are written into the Full Offset Register. The third
transition of WCLK writes, once again, to the Empty Offset Register.
For the IDT72T36115/72T36125, 4 enabled write cycles are required to
load the offset registers, (2 per offset). Data on the inputs Dn are written into the
Empty Offset Register LSB on the first LOW-to-HIGH transition of WCLK. Upon
the 2
nd
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into
the Empty Offset Register MSB. Upon the 3
rd
LOW-to-HIGH transition of WCLK
data on the inputs Dn are written into the Full Offset Register LSB. Upon the 4
th
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into the Full
Offset Register MSB. The 5
th
LOW-to-HIGH transition of WCLK data on the inputs
Dn are once again written into the Empty Offset Register LSB.
When a 9 bit input bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 4 enabled write cycles are required to load the offset registers, (2
per offset). Data on the inputs Dn are written into the Empty Offset Register LSB
on the first LOW-to-HIGH transition of WCLK. Upon the 2
nd
LOW-to-HIGH
transition of WCLK data on the inputs Dn are written into the Empty Offset Register
MSB. Upon the 3
rd
LOW-to-HIGH transition of WCLK data on the inputs Dn are
written into the Full Offset Register LSB. Upon the 4
th
LOW-to-HIGH transition
of WCLK data on the inputs Dn are written into the Full Offset Register MSB. The
5
th
LOW-to-HIGH transition of WCLK data on the inputs Dn are once again written
into the Empty Offset Register LSB.
For the IDT72T36115/72T36125, 6 enabled write cycles are required to
load the offset registers, (3 per offset). Data on the inputs Dn are written into the
Empty Offset Register LSB on the first LOW-to-HIGH transition of WCLK. Upon
the 3
rd
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into
the Empty Offset Register MSB. Upon the 4
th
LOW-to-HIGH transition of WCLK
data on the inputs Dn are written into the Full Offset Register LSB. Upon the 6
th
LOW-to-HIGH transition of WCLK data on the inputs Dn are written into the Full
Offset Register MSB. The 7
th
LOW-to-HIGH transition of WCLK data on the inputs
Dn are once again written into the Empty Offset Register LSB. See Figure 3,
Programmable Flag Offset Programming Sequence. See Figure 21, Parallel
Loading of Programmable Flag Registers
, for the timing diagram for this mode.
The act of writing offsets in parallel employs a dedicated write offset register
pointer. The act of reading offsets employs a dedicated read offset register
pointer. The two pointers operate independently; however, a read and a write
should not be performed simultaneously to the offset registers. A Master Reset
initializes both pointers to the Empty Offset (LSB) register. A Partial Reset has
no effect on the position of these pointers.
Write operations to the FIFO are allowed before and during the parallel
programming sequence. In this case, the programming of all offset registers does
not have to occur at one time. One, two or more offset registers can be written
and then by bringing
LD HIGH, write operations can be redirected to the FIFO
memory. When
LD is set LOW again, and WEN is LOW, the next offset register
in sequence is written to. As an alternative to holding
WEN LOW and toggling
LD, parallel programming can also be interrupted by setting LD LOW and
toggling
WEN.
Note that the status of a programmable flag (
PAE or PAF) output is invalid
during the programming process. From the time parallel programming has
begun, a programmable flag output will not be valid until the appropriate offset
word has been written to the register(s) pertaining to that flag. Measuring from
the rising WCLK edge that achieves the above criteria;
PAF will be valid after
two more rising WCLK edges plus t
PAF
,
PAE will be valid after the next two rising
RCLK edges plus t
PAE
plus t
SKEW2
.
The act of reading the offset registers employs a dedicated read offset
register pointer. The contents of the offset registers can be read on the Q
0
-Q
n
pins when
LD is set LOW and REN is set LOW. It is important to note that
consecutive reads of the offset registers is not permitted. The read operation must
be disabled for a minimum of one RCLK cycle in between offset register
accesses. When reading the Offset Registers of the TeraSync FIFO's the
number of reading cycles will be based on the bus width, the following rules
apply:
22
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
When a 36 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, 2 enabled read cycles are required to read
the offset registers, (1 per offset). Data on the outputs Qn are read from the Empty
Offset Register on the first LOW-to-HIGH transition of RCLK. Upon the second
LOW-to-HIGH transition of RCLK, data are read from the Full Offset Register.
The third transition of RCLK reads, once again, from the Empty Offset Register.
When an 18 bit output bus width is used:
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105, 2 enabled read cycles are required to read the offset registers, (1
per offset). Data on the outputs Qn are read from the Empty Offset Register on
the first LOW-to-HIGH transition of RCLK. Upon the second LOW-to-HIGH
transition of RCLK, data are read from the Full Offset Register. The third transition
of RCLK reads, once again, from the Empty Offset Register.
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 2
nd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
from the Empty Offset Register MSB. Upon the 3
rd
LOW-to-HIGH transition of
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 4
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
the Full Offset Register MSB. The 5
th
LOW-to-HIGH transition of RCLK data on
the outputs Qn are once again read from the Empty Offset Register LSB.
When a 9 bit output bus width is used:
For the IDT72T36115/72T36125, 4 enabled read cycles are required to
read the offset registers, (2 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 2
nd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
from the Empty Offset Register MSB. Upon the 3
rd
LOW-to-HIGH transition of
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 4
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
the Full Offset Register MSB. The 5
th
LOW-to-HIGH transition of RCLK data on
the outputs Qn are once again read from the Empty Offset Register LSB.
For the IDT72T36115/72T36125, 6 enabled read cycles are required to
read the offset registers, (3 per offset). Data on the outputs Qn are read from
the Empty Offset Register LSB on the first LOW-to-HIGH transition of RCLK.
Upon the 3
rd
LOW-to-HIGH transition of RCLK data on the outputs Qn are read
from the Empty Offset Register MSB. Upon the 4
th
LOW-to-HIGH transition of
RCLK data on the outputs Qn are read from the Full Offset Register LSB. Upon
the 6
th
LOW-to-HIGH transition of RCLK data on the outputs Qn are read from
the Full Offset Register MSB. The 7
th
LOW-to-HIGH transition of RCLK data on
the outputs Qn are once again read from the Empty Offset Register LSB. See
Figure 3, Programmable Flag Offset Programming Sequence. See Figure
22, Parallel Read of Programmable Flag Registers, for the timing diagram for
this mode.
It is permissible to interrupt the offset register read sequence with reads or
writes to the FIFO. The interruption is accomplished by deasserting
REN, LD,
or both together. When
REN and LD are restored to a LOW level, reading of
the offset registers continues where it left off. It should be noted, and care should
be taken from the fact that when a parallel read of the flag offsets is performed,
the data word that was present on the output lines Qn will be overwritten.
Parallel reading of the offset registers is always permitted regardless of
which timing mode (IDT Standard or FWFT modes) has been selected.
RETRANSMIT FROM MARK OPERATION
The Retransmit from Mark feature allows FIFO data to be read repeatedly
starting at a user-selected position. The FIFO is first put into retransmit mode that
will `mark' a beginning word and also set a pointer that will prevent ongoing FIFO
write operations from over-writing retransmit data. The retransmit data can be
read repeatedly any number of times from the `marked' position. The FIFO can
be taken out of retransmit mode at any time to allow normal device operation.
The `mark' position can be selected any number of times, each selection over-
writing the previous mark location. Retransmit operation is available in both IDT
standard and FWFT modes.
During IDT standard mode the FIFO is put into retransmit mode by a Low-
to-High transition on RCLK when the `MARK' input is HIGH and
EF is HIGH.
The rising RCLK edge `marks' the data present in the FIFO output register as
the first retransmit data. The FIFO remains in retransmit mode until a rising edge
on RCLK occurs while MARK is LOW.
Once a `marked' location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising edge on RCLK
while the retransmit input (
RT) is LOW. REN must be HIGH (reads disabled)
before bringing
RT LOW. The device indicates the start of retransmit setup by
setting
EF LOW, also preventing reads. When EF goes HIGH, retransmit setup
is complete and read operations may begin starting with the first data at the MARK
location. Since IDT standard mode is selected, every word read including the
first `marked' word following a retransmit setup requires a LOW on
REN (read
enabled).
Note, write operations may continue as normal during all retransmit
functions, however write operations to the `marked' location will be prevented.
See Figure 18, Retransmit from Mark (IDT standard mode), for the relevant
timing diagram.
During FWFT mode the FIFO is put into retransmit mode by a rising RCLK
edge when the `MARK' input is HIGH and
OR is LOW. The rising RCLK edge
`marks' the data present in the FIFO output register as the first retransmit data.
The FIFO remains in retransmit mode until a rising RCLK edge occurs while
MARK is LOW.
Once a marked location has been set (and the device is still in retransmit
mode, MARK is HIGH), a retransmit can be initiated by a rising RCLK edge while
the retransmit input (
RT) is LOW. REN must be HIGH (reads disabled) before
bringing
RT LOW. The device indicates the start of retransmit setup by setting
OR HIGH.
When
OR goes LOW, retransmit setup is complete and on the next rising
RCLK edge after retransmit setup is complete, (
RT goes HIGH), the contents
of the first retransmit location are loaded onto the output register. Since FWFT
mode is selected, the first word appears on the outputs regardless of
REN, a
LOW on
REN is not required for the first word. Reading all subsequent words
requires a LOW on
REN to enable the rising RCLK edge. See Figure 19,
Retransmit from Mark timing (FWFT mode), for the relevant timing diagram.
Note, there must be a minimum of 32 bytes of data between the write pointer
and read pointer when the MARK is asserted. (32 bytes = 16 word = 8 long
words). Also, once the MARK is set, the write pointer will not increment past the
"marked" location until the MARK is deasserted. This prevents "overwriting"
of retransmit data.
HSTL/LVTTL I/O
Both the write port and read port are user selectable between HSTL or
LVTTL I/O, via two select pins, WHSTL and RHSTL respectively. All other
control pins are selectable via SHSTL, see Table 5 for details of groupings.
Note, that when the write port is selected for HSTL mode, the user can reduce
the power consumption (in stand-by mode by utilizing the
WCS input).
All "Static Pins" must be tied to V
CC
or GND. These pins are LVTTL only,
and are purely device configuration pins.
23
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
WHSTL SELECT
RHSTL SELECT
SHSTL SELECT
STATIC PINS
WHSTL: HIGH = HSTL
RHSTL: HIGH = HSTL
SHSTL: HIGH = HSTL
LVTTL ONLY
LOW = LVTTL
LOW = LVTTL
LOW = LVTTL
Dn (I/P)
RCLK/RD (I/P)
EF/OR (O/P)
SCLK (I/P)
PRS (I/P)
IW (I/P)
OW (I/P)
WCLK/WR (I/P)
RCS (I/P)
PAF (O/P)
LD (I/P)
TRST (I/P)
BM (I/P)
ASYW (I/P)
WEN (I/P)
MARK (I/P)
EREN (O/P)
MRS (I/P)
TDI (I/P)
ASYR (I/P)
BE (I/P)
WCS (I/P)
REN (I/P)
PAE (O/P)
TCK (I/P)
IP (I/P)
FSEL0 (I/P)
OE (I/P)
FF/IR (O/P)
TMS (I/P)
FSEL1 (I/P)
PFM (I/P)
RT (I/P)
HF (O/P)
SEN (I/P)
SHSTL (I/P)
WHSTL (I/P)
Qn (O/P)
ERCLK (O/P)
FWFT/SI (I/P)
RHSTL (I/P)
TDO (O/P)
TABLE 5 -- I/O CONFIGURATION
24
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
SIGNAL DESCRIPTION
INPUTS:
DATA IN (D
0
- D
n
)
Data inputs for 36-bit wide data (D
0
- D
35
), data inputs for 18-bit wide data
(D
0
- D
17
) or data inputs for 9-bit wide data (D
0
- D
8
).
CONTROLS:
MASTER RESET (
MRS )
A Master Reset is accomplished whenever the
MRS input is taken to a LOW
state. This operation sets the internal read and write pointers to the first location
of the RAM array.
PAE will go LOW, PAF will go HIGH, and HF will go HIGH.
If FWFT/SI is LOW during Master Reset then the IDT Standard mode,
along with
EF and FF are selected. EF will go LOW and FF will go HIGH. If
FWFT/SI is HIGH, then the First Word Fall Through mode (FWFT), along with
IR and OR, are selected. OR will go HIGH and IR will go LOW.
All control settings such as OW, IW, BM,
BE, RM, PFM and IP are defined
during the Master Reset cycle.
During a Master Reset, the output register is initialized to all zeroes. A Master
Reset is required after power up, before a write operation can take place.
MRS
is asynchronous.
See Figure 9, Master Reset Timing, for the relevant timing diagram.
PARTIAL RESET (
PRS)
A Partial Reset is accomplished whenever the
PRS input is taken to a LOW
state. As in the case of the Master Reset, the internal read and write pointers
are set to the first location of the RAM array,
PAE goes LOW, PAF goes HIGH,
and
HF goes HIGH.
Whichever mode is active at the time of Partial Reset, IDT Standard mode
or First Word Fall Through, that mode will remain selected. If the IDT Standard
mode is active, then
FF will go HIGH and EF will go LOW. If the First Word
Fall Through mode is active, then
OR will go HIGH, and IR will go LOW.
Following Partial Reset, all values held in the offset registers remain
unchanged. The programming method (parallel or serial) currently active at
the time of Partial Reset is also retained. The output register is initialized to all
zeroes.
PRS is asynchronous.
A Partial Reset is useful for resetting the device during the course of
operation, when reprogramming programmable flag offset settings may not be
convenient.
See Figure 10, Partial Reset Timing, for the relevant timing diagram.
ASYNCHRONOUS WRITE (
ASYW)
The write port can be configured for either Synchronous or Asynchronous
mode of operation. If during Master Reset the
ASYW input is LOW, then
Asynchronous operation of the write port will be selected. During Asynchro-
nous operation of the write port the WCLK input becomes WR input, this is the
Asynchronous write strobe input. A rising edge on WR will write data present
on the Dn inputs into the FIFO. (
WEN must be tied LOW when using the write
port in Asynchronous mode).
When the write port is configured for Asynchronous operation the full flag
(
FF) operates in an asynchronous manner, that is, the full flag will be updated
based in both a write operation and read operation. Note, if Asynchronous
mode is selected, FWFT is not permissable. Refer to Figures 30, 31, 34 and
35 for relevant timing and operational waveforms.
ASYNCHRONOUS READ (
ASYR)
The read port can be configured for either Synchronous or Asynchronous
mode of operation. If during a Master Reset the
ASYR input is LOW, then
Asynchronous operation of the read port will be selected. During Asynchro-
nous operation of the read port the RCLK input becomes RD input, this is the
Asynchronous read strobe input. A rising edge on RD will read data from the
FIFO via the output register and Qn port. (
REN must be tied LOW during
Asynchronous operation of the read port).
The
OE input provides three-state control of the Qn output bus, in an
asynchronous manner. (
RCS, provides three-state control of the read port in
Synchronous mode).
When the read port is configured for Asynchronous operation the device
must be operating on IDT standard mode, FWFT mode is not permissible if the
read port is Asynchronous. The Empty Flag (
EF) operates in an Asynchronous
manner, that is, the empty flag will be updated based on both a read operation
and a write operation. Refer to figures 32, 33, 34 and 35 for relevant timing and
operational waveforms.
RETRANSMIT (
RT)
The Retransmit (
RT) input is used in conjunction with the MARK input,
together they provide a means by which data previously read out of the FIFO
can be reread any number of times. If retransmit operation has been selected
(i.e. the MARK input is HIGH), a rising edge on RCLK while
RT is LOW will reset
the read pointer back to the memory location set by the user via the MARK input.
If IDT standard mode has been selected the
EF flag will go LOW and remain
LOW for the time that
RT is held LOW. RT can be held LOW for any number
of RCLK cycles, the read pointer being reset to the marked location. The next
rising edge of RCLK after
RT has returned HIGH, will cause EF to go HIGH,
allowing read operations to be performed on the FIFO. The next read operation
will access data from the `marked' memory location.
Subsequent retransmit operations may be performed, each time the read
pointer returning to the `marked' location. See Figure 18, Retransmit from Mark
(IDT Standard mode)
for the relevant timing diagram.
If FWFT mode has been selected the
OR flag will go HIGH and remain HIGH
for the time that
RT is held LOW. RT can be held LOW for any number of RCLK
cycles, the read pointer being reset to the `marked' location. The next RCLK
rising edge after
RT has returned HIGH, will cause OR to go LOW and due to
FWFT operation, the contents of the marked memory location will be loaded onto
the output register, a read operation being required for all subsequent data
reads.
Subsequent retransmit operations may be performed each time the read
pointer returning to the `marked' location. See Figure 19, Retransmit from Mark
(FWFT mode)
for the relevant timing diagram.
MARK
The MARK input is used to select Retransmit mode of operation. An RCLK
rising edge while MARK is HIGH will mark the memory location of the data
currently present on the output register, the device will also be placed into
retransmit mode. Note, for the IDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695 there must be a minimum of 32 bytes of data between the
write pointer and read pointer when the MARK is asserted. For the IDT72T36105/
72T36115 there must be a minimum of 128 bytes, for the IDT72T36125 a
minimum of 256 bytes. Remember, 4 (x9) bytes = 2 (x18) words = 1 (x36) word.
Also, once the MARK is set, the write pointer will not increment past the "marked"
location until the MARK is deasserted. This prevents "overwriting" of retransmit
data.
The MARK input must remain HIGH during the whole period of retransmit
mode, a falling edge of RCLK while MARK is LOW will take the device out of
retransmit mode and into normal mode. Any number of MARK locations can be
set during FIFO operation, only the last marked location taking effect. Once a
mark location has been set the write pointer cannot be incremented past this
25
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
marked location. During retransmit mode write operations to the device may
continue without hindrance.
FIRST WORD FALL THROUGH/SERIAL IN (FWFT/SI)
This is a dual purpose pin. During Master Reset, the state of the FWFT/
SI input determines whether the device will operate in IDT Standard mode or
First Word Fall Through (FWFT) mode.
If, at the time of Master Reset, FWFT/SI is LOW, then IDT Standard mode
will be selected. This mode uses the Empty Flag (
EF) to indicate whether or
not there are any words present in the FIFO memory. It also uses the Full Flag
function (
FF) to indicate whether or not the FIFO memory has any free space
for writing. In IDT Standard mode, every word read from the FIFO, including
the first, must be requested using the Read Enable (
REN) and RCLK.
If, at the time of Master Reset, FWFT/SI is HIGH, then FWFT mode will be
selected. This mode uses Output Ready (
OR) to indicate whether or not there
is valid data at the data outputs (Q
n)
. It also uses Input Ready (
IR) to indicate
whether or not the FIFO memory has any free space for writing. In the FWFT
mode, the first word written to an empty FIFO goes directly to Q
n
after three RCLK
rising edges,
REN = LOW is not necessary. Subsequent words must be
accessed using the Read Enable (
REN) and RCLK.
After Master Reset, FWFT/SI acts as a serial input for loading
PAE and PAF
offsets into the programmable registers. The serial input function can only be
used when the serial loading method has been selected during Master Reset.
Serial programming using the FWFT/SI pin functions the same way in both IDT
Standard and FWFT modes.
WRITE STROBE & WRITE CLOCK (WR/WCLK)
If Synchronous operation of the write port has been selected via
ASYW, this
input behaves as WCLK.
A write cycle is initiated on the rising edge of the WCLK input. Data setup
and hold times must be met with respect to the LOW-to-HIGH transition of the
WCLK. It is permissible to stop the WCLK. Note that while WCLK is idle, the
FF/
IR, PAF and HF flags will not be updated. (Note that WCLK is only capable of
updating
HF flag to LOW). The Write and Read Clocks can either be
independent or coincident.
If Asynchronous operation has been selected this input is WR (write strobe).
Data is Asynchronously written into the FIFO via the Dn inputs whenever there
is a rising edge on WR. In this mode the WEN input must be tied LOW.
WRITE ENABLE (
WEN)
When the
WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When
WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow in the IDT Standard mode,
FF will go LOW,
inhibiting further write operations. Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to occur. The FF is updated by two WCLK
cycles + t
SKEW
after the RCLK cycle.
To prevent data overflow in the FWFT mode,
IR will go HIGH, inhibiting
further write operations. Upon the completion of a valid read cycle,
IR will go
LOW allowing a write to occur. The
IR flag is updated by two WCLK cycles +
t
SKEW
after the valid RCLK cycle.
WEN is ignored when the FIFO is full in either FWFT or IDT Standard mode.
If Asynchronous operation of the write port has been selected, then WEN
must be held active, (tied LOW).
READ STROBE & READ CLOCK (RD/RCLK)
If Synchronous operation of the read port has been selected via
ASYR, this
input behaves as RCLK. A read cycle is initiated on the rising edge of the RCLK
input. Data can be read on the outputs, on the rising edge of the RCLK input.
It is permissible to stop the RCLK. Note that while RCLK is idle, the
EF/OR, PAE
and
HF flags will not be updated. (Note that RCLK is only capable of updating
the
HF flag to HIGH). The Write and Read Clocks can be independent or
coincident.
If Asynchronous operation has been selected this input is RD (Read
Strobe) . Data is Asynchronously read from the FIFO via the output register
whenever there is a rising edge on RD. In this mode the
REN and RCS inputs
must be tied LOW. The
OE input is used to provide Asynchronous control of the
three-state Qn outputs.
WRITE CHIP SELECT (
WCS)
The
WCS disables all Write Port inputs (data only) if it is held HIGH. To
perform normal operations on the write port, the
WCS must be enabled, held
LOW.
READ ENABLE (
REN)
When Read Enable is LOW, data is loaded from the RAM array into the
output register on the rising edge of every RCLK cycle if the device is not empty.
When the
REN input is HIGH, the output register holds the previous data
and no new data is loaded into the output register. The data outputs Q
0
-Q
n
maintain the previous data value.
In the IDT Standard mode, every word accessed at Q
n
, including the first
word written to an empty FIFO, must be requested using
REN provided that
RCS is LOW. When the last word has been read from the FIFO, the Empty Flag
(
EF) will go LOW, inhibiting further read operations. REN is ignored when the
FIFO is empty. Once a write is performed,
EF will go HIGH allowing a read to
occur. The
EF flag is updated by two RCLK cycles + t
SKEW
after the valid WCLK
cycle. Both
RCS and REN must be active, LOW for data to be read out on the
rising edge of RCLK.
In the FWFT mode, the first word written to an empty FIFO automatically goes
to the outputs Q
n
, on the third valid LOW-to-HIGH transition of RCLK + t
SKEW
after the first write.
REN and RCS do not need to be asserted LOW for the First
Word to fall through to the output register. In order to access all other words,
a read must be executed using
REN and RCS. The RCLK LOW-to-HIGH
transition after the last word has been read from the FIFO, Output Ready (
OR)
will go HIGH with a true read (RCLK with
REN = LOW;RCS = LOW), inhibiting
further read operations.
REN is ignored when the FIFO is empty.
If Asynchronous operation of the Read port has been selected, then
REN
must be held active, (tied LOW).
SERIAL ENABLE (
SEN )
The
SEN input is an enable used only for serial programming of the offset
registers. The serial programming method must be selected during Master
Reset.
SEN is always used in conjunction with LD. When these lines are both
LOW, data at the SI input can be loaded into the program register one bit for each
LOW-to-HIGH transition of SCLK.
When
SEN is HIGH, the programmable registers retains the previous
settings and no offsets are loaded.
SEN functions the same way in both IDT
Standard and FWFT modes.
OUTPUT ENABLE (
OE )
When Output Enable is enabled (LOW), the parallel output buffers receive
data from the output register. When
OE is HIGH, the output data bus (Q
n
) goes
26
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
into a high impedance state. During Master or a Partial Reset the
OE is the only
input that can place the output bus Qn, into High-Impedance. During Reset the
RCS input can be HIGH or LOW, it has no effect on the Qn outputs.
READ CHIP SELECT (
RCS )
The Read Chip Select input provides synchronous control of the Read
output port. When
RCS goes LOW, the next rising edge of RCLK causes the
Qn outputs to go to the Low-Impedance state. When
RCS goes HIGH, the next
RCLK rising edge causes the Qn outputs to return to HIGH Z. During a Master
or Partial Reset the
RCS input has no effect on the Qn output bus, OE is the only
input that provides High-Impedance control of the Qn outputs. If
OE is LOW the
Qn data outputs will be Low-Impedance regardless of
RCS until the first rising
edge of RCLK after a Reset is complete. Then if
RCS is HIGH the data outputs
will go to High-Impedance.
The
RCS input does not effect the operation of the flags. For example, when
the first word is written to an empty FIFO, the
EF will still go from LOW to HIGH
based on a rising edge of RCLK
, regardless of the state of the RCS input.
Also, when operating the FIFO in FWFT mode the first word written to an
empty FIFO will still be clocked through to the output register based on RCLK,
regardless of the state of
RCS. For this reason the user must take care when
a data word is written to an empty FIFO in FWFT mode. If
RCS is disabled when
an empty FIFO is written into, the first word will fall through to the output register,
but will not be available on the Qn outputs which are in HIGH-Z. The user must
take
RCS active LOW to access this first word, place the output bus in LOW-Z.
REN must remain disabled HIGH for at least one cycle after RCS has gone LOW.
A rising edge of RCLK with
RCS and REN active LOW, will read out the next
word. Care must be taken so as not to lose the first word written to an empty
FIFO when
RCS is HIGH. Refer to Figure 17,
RCS
and
REN
Read Operation
(FWFT Mode). The
RCS pin must also be active (LOW) in order to perform
a Retransmit. See Figure 13 for Read Cycle and Read Chip Select Timing (IDT
Standard Mode).
See Figure 16 for Read Cycle and Read Chip Select Timing
(First Word Fall Through Mode).
If Asynchronous operation of the Read port has been selected, then
RCS
must be held active, (tied LOW).
OE provides three-state control of Qn.
WRITE PORT HSTL SELECT (WHSTL)
The control inputs, data inputs and flag outputs associated with the write port
can be setup to be either HSTL or LVTTL. If WHSTL is HIGH during the Master
Reset, then HSTL operation of the write port will be selected. If WHSTL is LOW
at Master Reset, then LVTTL will be selected.
The inputs and outputs associated with the write port are listed in Table 5.
READ PORT HSTL SELECT (RHSTL)
The control inputs, data inputs and flag outputs associated with the read port
can be setup to be either HSTL or LVTTL. If RHSTL is HIGH during the Master
Reset, then HSTL operation of the read port will be selected. If RHSTL is LOW
at Master Reset, then LVTTL will be selected for the read port, then echo clock
and echo read enable will not be provided.
The inputs and outputs associated with the read port are listed in Table 5.
SYSTEM HSTL SELECT (SHSTL)
All inputs not associated with the write and read port can be setup to be either
HSTL or LVTTL. If SHSTL is HIGH during Master Reset, then HSTL operation
of all the inputs not associated with the write and read port will be selected. If
SHSTL is LOW at Master Reset, then LVTTL will be selected. The inputs
associated with SHSTL are listed in Table 5.
LOAD (
LD)
This is a dual purpose pin. During Master Reset, the state of the
LD input,
along with FSEL0 and FSEL1, determines one of eight default offset values for
the
PAE and PAF flags, along with the method by which these offset registers
can be programmed, parallel or serial (see Table 2). After Master Reset,
LD
enables write operations to and read operations from the offset registers. Only
the offset loading method currently selected can be used to write to the registers.
Offset registers can be read only in parallel.
After Master Reset, the
LD pin is used to activate the programming process
of the flag offset values
PAE and PAF. Pulling LD LOW will begin a serial loading
or parallel load or read of these offset values.
BUS-MATCHING (BM, IW, OW)
The pins BM, IW and OW are used to define the input and output bus widths.
During Master Reset, the state of these pins is used to configure the device bus
sizes. See Table 1 for control settings. All flags will operate on the word/byte
size boundary as defined by the selection of bus width. See Figure 5 for Bus-
Matching Byte Arrangement
.
BIG-ENDIAN/LITTLE-ENDIAN (
BE )
During Master Reset, a LOW on
BE will select Big-Endian operation. A
HIGH on
BE during Master Reset will select Little-Endian format. This function
is useful when the following input to output bus widths are implemented: x36 to
x18, x36 to x9, x18 to x36 and x9 to x36. If Big-Endian mode is selected, then
the most significant byte (word) of the long word written into the FIFO will be read
out of the FIFO first, followed by the least significant byte. If Little-Endian format
is selected, then the least significant byte of the long word written into the FIFO
will be read out first, followed by the most significant byte. The mode desired
is configured during master reset by the state of the Big-Endian (
BE) pin. See
Figure 5 for Bus-Matching Byte Arrangement.
PROGRAMMABLE FLAG MODE (PFM)
During Master Reset, a LOW on PFM will select Asynchronous Program-
mable flag timing mode. A HIGH on PFM will select Synchronous Program-
mable flag timing mode. If asynchronous
PAF/PAE configuration is selected
(PFM, LOW during
MRS), the PAE is asserted LOW on the LOW-to-HIGH
transition of RCLK.
PAE is reset to HIGH on the LOW-to-HIGH transition of
WCLK. Similarly, the
PAF is asserted LOW on the LOW-to-HIGH transition of
WCLK and
PAF is reset to HIGH on the LOW-to-HIGH transition of RCLK.
If synchronous
PAE/PAF configuration is selected (PFM, HIGH during
MRS) , the
PAE is asserted and updated on the rising edge of RCLK only and
not WCLK. Similarly,
PAF is asserted and updated on the rising edge of WCLK
only and not RCLK. The mode desired is configured during master reset by
the state of the Programmable Flag Mode (PFM) pin.
INTERSPERSED PARITY (IP)
During Master Reset, a LOW on IP will select Non-Interspersed Parity
mode. A HIGH will select Interspersed Parity mode. The IP bit function allows
the user to select the parity bit in the word loaded into the parallel port (D
0
-Dn)
when programming the flag offsets. If Interspersed Parity mode is selected, then
the FIFO will assume that the parity bits are located in bit position D
8
, D
17
, D
26
and D
35
during the parallel programming of the flag offsets. If Non-Interspersed
Parity mode is selected, then D
8
, D
17
and D
28
are is assumed to be valid bits
and D
32
, D
33
, D
34
and D
35
are ignored. IP mode is selected during Master
Reset by the state of the IP input pin.
27
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
OUTPUTS:
FULL FLAG (
FF/IR )
This is a dual purpose pin. In IDT Standard mode, the Full Flag (
FF) function
is selected. When the FIFO is full,
FF will go LOW, inhibiting further write
operations. When
FF is HIGH, the FIFO is not full. If no reads are performed
after a reset (either
MRS or PRS), FF will go LOW after D writes to the FIFO
(D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the
IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115
and 262,144 for the IDT72T36125). See Figure 11, Write Cycle and Full Flag
Timing (IDT Standard Mode)
, for the relevant timing information.
In FWFT mode, the Input Ready (
IR) function is selected. IR goes LOW
when memory space is available for writing in data. When there is no longer
any free space left,
IR goes HIGH, inhibiting further write operations. If no reads
are performed after a reset (either
MRS or PRS), IR will go HIGH after D writes
to the FIFO (D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097
for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685,
32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the
IDT72T36115 and 262,145 for the IDT72T36125). See Figure 14, Write
Timing (FWFT Mode)
, for the relevant timing information.
The
IR status not only measures the contents of the FIFO memory, but also
counts the presence of a word in the output register. Thus, in FWFT mode, the
total number of writes necessary to deassert
IR is one greater than needed to
assert
FF in IDT Standard mode.
FF/IR is synchronous and updated on the rising edge of WCLK. FF/IR are
double register-buffered outputs.
Note, when the device is in Retransmit mode, this flag is a comparison of the
write pointer to the `marked' location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
EMPTY FLAG (
EF/OR )
This is a dual purpose pin. In the IDT Standard mode, the Empty Flag (
EF)
function is selected. When the FIFO is empty,
EF will go LOW, inhibiting further
read operations. When
EF is HIGH, the FIFO is not empty. See Figure 12, Read
Cycle, Empty Flag and First Word Latency Timing (IDT Standard Mode), for
the relevant timing information.
In FWFT mode, the Output Ready (
OR) function is selected. OR goes LOW
at the same time that the first word written to an empty FIFO appears valid on
the outputs.
OR stays LOW after the RCLK LOW to HIGH transition that shifts
the last word from the FIFO memory to the outputs.
OR goes HIGH only with
a true read (RCLK with
REN = LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited until
OR goes
LOW again. See Figure 15, Read Timing (FWFT Mode), for the relevant timing
information.
EF/OR is synchronous and updated on the rising edge of RCLK.
In IDT Standard mode,
EF is a double register-buffered output. In FWFT
mode,
OR is a triple register-buffered output.
PROGRAMMABLE ALMOST-FULL FLAG (
PAF )
The Programmable Almost-Full flag (
PAF) will go LOW when the FIFO
reaches the almost-full condition. In IDT Standard mode, if no reads are
performed after reset (
MRS), PAF will go LOW after (D - m) words are written
to the FIFO. The
PAF will go LOW after (1,024-m) writes for the IDT72T3645,
(2,048-m) writes for the IDT72T3655, (4,096-m) writes for the IDT72T3665,
(8,192-m) writes for the IDT72T3675, (16,384-m) writes for the IDT72T3685,
(32,768-m) writes for the IDT72T3695, (65,536-m) writes for the IDT72T36105,
(131,072-m) writes for the IDT72T36115 and (262,144-m) writes for the
IDT72T36125. The offset "m" is the full offset value. The default setting for this
value is stated in the footnote of Table 3.
In FWFT mode, the
PAF will go LOW after (1,025-m) writes for the
IDT72T3645, (2,049-m) writes for the IDT72T3655, (4,097-m) writes for the
IDT72T3665 and (8,193-m) writes for the IDT72T3675, (16,385-m) writes for
the IDT72T3685, (32,769-m) writes for the IDT72T3695, (65,537-m) writes for
the IDT72T36105, (131,073-m) writes for the IDT72T36115 and (262,145-m)
writes for the IDT72T36125, where m is the full offset value. The default setting
for this value is stated in Table 4.
See Figure 23, Synchronous Programmable Almost-Full Flag Timing (IDT
Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAF configuration is selected, the PAF is asserted LOW
on the LOW-to-HIGH transition of the Write Clock (WCLK).
PAF is reset to HIGH
on the LOW-to-HIGH transition of the Read Clock (RCLK). If synchronous
PAF
configuration is selected, the
PAF is updated on the rising edge of WCLK. See
Figure 25, Asynchronous Almost-Full Flag Timing (IDT Standard and FWFT
Mode)
.
Note, when the device is in Retransmit mode, this flag is a comparison of the
write pointer to the `marked' location. This differs from normal mode where this
flag is a comparison of the write pointer to the read pointer.
PROGRAMMABLE ALMOST-EMPTY FLAG (
PAE )
The Programmable Almost-Empty flag (
PAE) will go LOW when the FIFO
reaches the almost-empty condition. In IDT Standard mode,
PAE will go LOW
when there are n words or less in the FIFO. The offset "n" is the empty offset
value. The default setting for this value is stated in the footnote of Table 1.
In FWFT mode, the
PAE will go LOW when there are n+1 words or less
in the FIFO. The default setting for this value is stated in Table 2.
See Figure 24, Synchronous Programmable Almost-Empty Flag Timing
(IDT Standard and FWFT Mode), for the relevant timing information.
If asynchronous
PAE configuration is selected, the PAE is asserted LOW
on the LOW-to-HIGH transition of the Read Clock (RCLK).
PAE is reset to HIGH
on the LOW-to-HIGH transition of the Write Clock (WCLK). If synchronous
PAE
configuration is selected, the
PAE is updated on the rising edge of RCLK. See
Figure 26, Asynchronous Programmable Almost-Empty Flag Timing (IDT
Standard and FWFT Mode)
.
HALF-FULL FLAG (
HF )
This output indicates a half-full FIFO. The rising WCLK edge that fills the FIFO
beyond half-full sets
HF LOW. The flag remains LOW until the difference between
the write and read pointers becomes less than or equal to half of the total depth
of the device; the rising RCLK edge that accomplishes this condition sets
HF
HIGH.
In IDT Standard mode, if no reads are performed after reset (
MRS or PRS),
HF will go LOW after (D/2 + 1) writes to the FIFO, where D = 1,024 for the
IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192
for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the IDT72T3695,
65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for
the IDT72T36125.
In FWFT mode, if no reads are performed after reset (
MRS or PRS), HF
will go LOW after (D-1/2 + 2) writes to the FIFO, where D = 1,025 for the
IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for
the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
See Figure 27, Half-Full Flag Timing (IDT Standard and FWFT Modes),
for the relevant timing information. Because
HF is updated by both RCLK and
WCLK, it is considered asynchronous.
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
ECHO READ CLOCK (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL mode,
selectable via RHSTL. The ERCLK is a free-running clock output, it will always
follow the RCLK input regardless of
REN and RCS.
The ERCLK output follows the RCLK input with an associated delay. This
delay provides the user with a more effective read clock source when reading
data from the Qn outputs. This is especially helpful at high speeds when
variables within the device may cause changes in the data access times. These
variations in access time maybe caused by ambient temperature, supply
voltage, device characteristics. The ERCLK output also compensates for any
trace length delays between the Qn data outputs and receiving devices inputs.
Any variations effecting the data access time will also have a corresponding
effect on the ERCLK output produced by the FIFO device, therefore the ERCLK
output level transitions should always be at the same position in time relative to
the data outputs. Note, that ERCLK is guaranteed by design to be slower than
the slowest Qn, data output. Refer to Figure 4, Echo Read Clock and Data
Output Relationship
, Figure 28, Echo Read Clock & Read Enable Operation
and Figure 29, Echo RCLK & Echo
REN
Operation for timing information.
ECHO READ ENABLE (
EREN)
The Echo Read Enable output is provided in both HSTL and LVTTL mode,
selectable via RHSTL.
The
EREN output is provided to be used in conjunction with the ERCLK
output and provides the reading device with a more effective scheme for reading
data from the Qn output port at high speeds. The
EREN output is controlled by
internal logic that behaves as follows: The
EREN output is active LOW for the
RCLK cycle that a new word is read out of the FIFO. That is, a rising edge of
RCLK will cause
EREN to go active, LOW if both REN and RCS are active, LOW
and the FIFO is NOT empty.
SERIAL CLOCK (SCLK)
During serial loading of the programming flag offset registers, a rising edge
on the SCLK input is used to load serial data present on the SI input provided
that the
SEN input is LOW.
DATA OUTPUTS (Q
0
-Q
n
)
(Q
0
-Q
35
) are data outputs for 36-bit wide data, (Q
0
- Q
17
) are data outputs
for 18-bit wide data or (Q
0
-Q
8
) are data outputs for 9-bit wide data.
Figure 4. Echo Read Clock and Data Output Relationship
NOTES:
1.
REN is LOW.
2. t
ERCLK
> t
A
, guaranteed by design.
3. Qslowest is the data output with the slowest access time, t
A
.
4. Time, t
D
is greater than zero, guaranteed by design.
5907 drw08
ERCLK
t
A
t
D
Q
SLOWEST
(3)
RCLK
t
ERCLK
t
ERCLK
29
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
D35-D27
A
A
A
D
A
C
B
B
B
C
B
D
C
C
C
A
D
D
D
B
(a) x36 INPUT to x36 OUTPUT
(b) x36 INPUT to x18 OUTPUT - BIG-ENDIAN
(c) x36 INPUT to x18 OUTPUT - LITTLE-ENDIAN
(d) x36 INPUT to x9 OUTPUT - BIG-ENDIAN
Write to FIFO
Read from FIFO
1st: Read from FIFO
BE
BYTE ORDER ON INPUT PORT:
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
1st: Read from FIFO
1st: Read from FIFO
2nd: Read from FIFO
2nd: Read from FIFO
D
C
(e) x36 INPUT to x9 OUTPUT - LITTLE-ENDIAN
1st: Read from FIFO
A
B
2nd: Read from FIFO
3rd: Read from FIFO
4th: Read from FIFO
5907 drw09
BYTE ORDER ON OUTPUT PORT:
X
Q35-Q27
BM
IW
OW
BE BM
IW
OW
L
L
L
L
H
L
L
BE BM
IW
OW
H
H
L
L
BE BM
IW
OW
L
H
L
H
BE BM
IW
OW
H
H
L
H
D8-D0
D17-D9
D26-D18
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Figure 5. Bus-Matching Byte Arrangement
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 5. Bus-Matching Byte Arrangement (Continued)
A
A
D
A
C
B
B
C
B
D
C
D
(a) x18 INPUT to x36 OUTPUT - BIG-ENDIAN
Read from FIFO
1st: Write to FIFO
BYTE ORDER ON INPUT PORT:
2nd: Write to FIFO
3rd: Write to FIFO
4th: Write to FIFO
1st: Write to FIFO
2nd: Write to FIFO
5907 drw10
BYTE ORDER ON OUTPUT PORT:
C
D
A
B
(b) x18 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Read from FIFO
BYTE ORDER ON INPUT PORT:
A
B
C
D
(a) x9 INPUT to x36 OUTPUT - BIG-ENDIAN
Read from FIFO
BYTE ORDER ON OUTPUT PORT:
D
C
B
A
(b) x9 INPUT to x36 OUTPUT - LITTLE-ENDIAN
Read from FIFO
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
BE
L
BM
IW
OW
H
H
L
BE
H
BM
IW
OW
H
H
L
BE
L
BM
IW
OW
H
H
H
BE
H
BM
IW
OW
H
H
H
D35-D27
D26-D18
D17-D9
D8-D0
D35-D27
D26-D18
D17-D9
D8-D0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
D35-D27
D26-D18
D17-D9
D8-D0
D35-D27
D26-D18
D17-D9
D8-D0
D35-D27
D26-D18
D17-D9
D8-D0
D35-D27
D26-D18
D17-D9
D8-D0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
Q35-Q27
Q26-Q18
Q17-Q9
Q8-Q0
31
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 6. Standard JTAG Timing
SYSTEM INTERFACE PARAMETERS
Parameter
Symbol
Test
Conditions
Min.
Max. Units
JTAG Clock Input Period t
TCK
-
100
-
ns
JTAG Clock HIGH
t
TCKHIGH
-
40
-
ns
JTAG Clock Low
t
TCKLOW
-
40
-
ns
JTAG Clock Rise Time
t
TCKRISE
-
-
5
(1)
ns
JTAG Clock Fall Time
t
TCKFALL
-
-
5
(1)
ns
JTAG Reset
t
RST
-
50
-
ns
JTAG Reset Recovery
t
RSR
-
50
-
ns
JTAG
AC ELECTRICAL CHARACTERISTICS
(v
cc = 2.5V
5%; Tcase = 0C to +85C)
IDT72T3645
IDT72T3655
IDT72T3665
IDT72T3675
IDT72T3685
IDT72T3695
IDT72T36105
IDT72T36115
IDT72T36125
Parameter
Symbol
Test Conditions
Min.
Max.
Units
Data Output
t
DO
(1)
-
20
ns
Data Output Hold
t
DOH
(1)
0
-
ns
Data Input
t
DS
t
rise=3ns
10
-
ns
t
DH
t
fall=3ns
10
-
NOTE:
1. 50pf loading on external output signals.
JTAG TIMING SPECIFICATION
NOTE:
1. Guaranteed by design.
t
4
t
3
TDO
TDO
TDI/
TMS
TCK
TRST
t
DO
Notes to diagram:
t1 =
t
TCKLOW
t2 =
t
TCKHIGH
t3 =
t
TCKFALL
t4 = t
TCKRISE
t5 =
tRST
(reset pulse width)
t6 = tRSR (reset recovery)
5907 drw11
t
5
t
6
t
1
t
2
t
TCK
t
DH
t
DS
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
JTAG INTERFACE
Five additional pins (TDI, TDO, TMS, TCK and
TRST) are provided to
support the JTAG boundary scan interface. The IDT72T3645/72T3655/
72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/72T36125 in-
corporates the necessary tap controller and modified pad cells to implement the
JTAG facility.
Note that IDT provides appropriate Boundary Scan Description Language
program files for these devices.
The Standard JTAG interface consists of four basic elements:
Test Access Port (TAP)
TAP controller
Instruction Register (IR)
Data Register Port (DR)
The following sections provide a brief description of each element. For a
complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
The Figure below shows the standard Boundary-Scan Architecture
Figure 7. Boundary Scan Architecture
TEST ACCESS PORT (TAP)
The Tap interface is a general-purpose port that provides access to the
internal of the processor. It consists of four input ports (TCLK, TMS, TDI,
TRST)
and one output port (TDO).
THE TAP CONTROLLER
The Tap controller is a synchronous finite state machine that responds to
TMS and TCLK signals to generate clock and control signals to the Instruction
and Data Registers for capture and update of data.
T
A
P
TAP
Cont-
roller
Mux
DeviceID Reg.
Boundary Scan Reg.
Bypass Reg.
clkDR, ShiftDR
UpdateDR
TDO
TDI
TMS
TCLK
TRST
clklR, ShiftlR
UpdatelR
Instruction Register
Instruction Decode
Control Signals
5907 drw12
33
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 8. TAP Controller State Diagram
Test-Logic
Reset
Run-Test/
Idle
1
0
0
Select-
DR-Scan
Select-
IR-Scan
1
1
1
Capture-IR
0
Capture-DR
0
0
EXit1-DR
1
Pause-DR
0
Exit2-DR
1
Update-DR
1
Exit1-IR
1
Exit2-IR
1
Update-IR
1
1
0
1
1
1
5907 drw13
0
Shift-DR
0
0
0
Shift-IR
0
0
Pause-IR
0
1
Input = TMS
0
0
1
Refer to the IEEE Standard Test Access Port Specification (IEEE Std.
1149.1) for the full state diagram
All state transitions within the TAP controller occur at the rising edge of the
TCLK pulse. The TMS signal level (0 or 1) determines the state progression
that occurs on each TCLK rising edge. The TAP controller takes precedence
over the FIFO memory and must be reset after power up of the device. See
TRST description for more details on TAP controller reset.
Test-Logic-Reset All test logic is disabled in this controller state enabling the
normal operation of the IC. The TAP controller state machine is designed in such
a way that, no matter what the initial state of the controller is, the Test-Logic-Reset
state can be entered by holding TMS at high and pulsing TCK five times. This
is the reason why the Test Reset (
TRST) pin is optional.
Run-Test-Idle In this controller state, the test logic in the IC is active only if
certain instructions are present. For example, if an instruction activates the self
test, then it will be executed when the controller enters this state. The test logic
in the IC is idles otherwise.
Select-DR-Scan This is a controller state where the decision to enter the
Data Path or the Select-IR-Scan state is made.
Select-IR-Scan This is a controller state where the decision to enter the
Instruction Path is made. The Controller can return to the Test-Logic-Reset state
other wise.
Capture-IR In this controller state, the shift register bank in the Instruction
Register parallel loads a pattern of fixed values on the rising edge of TCK. The
last two significant bits are always required to be "01".
Shift-IR In this controller state, the instruction register gets connected
between TDI and TDO, and the captured pattern gets shifted on each rising edge
of TCK. The instruction available on the TDI pin is also shifted in to the instruction
register.
Exit1-IR This is a controller state where a decision to enter either the Pause-
IR state or Update-IR state is made.
Pause-IR This state is provided in order to allow the shifting of instruction
register to be temporarily halted.
Exit2-DR This is a controller state where a decision to enter either the Shift-
IR state or Update-IR state is made.
Update-IR In this controller state, the instruction in the instruction register is
latched in to the latch bank of the Instruction Register on every falling edge of
TCK. This instruction also becomes the current instruction once it is latched.
Capture-DR In this controller state, the data is parallel loaded in to the data
registers selected by the current instruction on the rising edge of TCK.
Shift-DR, Exit1-DR, Pause-DR, Exit2-DR and Update-DR These
controller states are similar to the Shift-IR, Exit1-IR, Pause-IR, Exit2-IR and
Update-IR states in the Instruction path.
NOTES:
1. Five consecutive TCK cycles with TMS = 1 will reset the TAP.
2. TAP controller does not automatically reset upon power-up. The user must provide a reset to the TAP controller (either by
TRST or TMS).
3. TAP controller must be reset before normal FIFO operations can begin.
34
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
THE INSTRUCTION REGISTER
The Instruction register allows an instruction to be shifted in serially into the
processor at the rising edge of TCLK.
The Instruction is used to select the test to be performed, or the test data
register to be accessed, or both. The instruction shifted into the register is latched
at the completion of the shifting process when the TAP controller is at Update-
IR state.
The instruction register must contain 4 bit instruction register-based cells
which can hold instruction data. These mandatory cells are located nearest the
serial outputs they are the least significant bits.
TEST DATA REGISTER
The Test Data register contains three test data registers: the Bypass, the
Boundary Scan register and Device ID register.
These registers are connected in parallel between a common serial input
and a common serial data output.
The following sections provide a brief description of each element. For a
complete description, refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
TEST BYPASS REGISTER
The register is used to allow test data to flow through the device from TDI
to TDO. It contains a single stage shift register for a minimum length in serial path.
When the bypass register is selected by an instruction, the shift register stage
is set to a logic zero on the rising edge of TCLK when the TAP controller is in
the Capture-DR state.
The operation of the bypass register should not have any effect on the
operation of the device in response to the BYPASS instruction.
THE BOUNDARY-SCAN REGISTER
The Boundary Scan Register allows serial data TDI be loaded in to or read
out of the processor input/output ports. The Boundary Scan Register is a part
of the IEEE 1149.1-1990 Standard JTAG Implementation.
THE DEVICE IDENTIFICATION REGISTER
The Device Identification Register is a Read Only 32-bit register used to
specify the manufacturer, part number and version of the processor to be
determined through the TAP in response to the IDCODE instruction.
IDT JEDEC ID number is 0xB3. This translates to 0x33 when the parity
is dropped in the 11-bit Manufacturer ID field.
For the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125, the Part Number field contains the following
values:
IDT72T3645/55/65/75/85/95/105/115/125 JTAG Device Identification Register
31(MSB)
28 27
12 11
1 0(LSB)
Version (4 bits)
Part Number (16-bit) Manufacturer ID (11-bit)
0X0
0X33
1
JTAG INSTRUCTION REGISTER
The Instruction register allows instruction to be serially input into the device
when the TAP controller is in the Shift-IR state. The instruction is decoded to
perform the following:
Select test data registers that may operate while the instruction is
current. The other test data registers should not interfere with chip
operation and the selected data register.
Define the serial test data register path that is used to shift data between
TDI and TDO during data register scanning.
The Instruction Register is a 4 bit field (i.e.IR3, IR2, IR1, IR0) to decode 16
different possible instructions. Instructions are decoded as follows.
Hex
Instruction
Function
Value
0x00
EXTEST
Select Boundary Scan Register
0x02
IDCODE
Select Chip Identification data register
0x01
SAMPLE/PRELOAD
Select Boundary Scan Register
0x03
HIGH-IMPEDANCE
JTAG
0x0F
BYPASS
Select Bypass Register
JTAG Instruction Register Decoding
The following sections provide a brief description of each instruction. For
a complete description refer to the IEEE Standard Test Access Port Specification
(IEEE Std. 1149.1-1990).
EXTEST
The required EXTEST instruction places the IC into an external boundary-
test mode and selects the boundary-scan register to be connected between TDI
and TDO. During this instruction, the boundary-scan register is accessed to
drive test data off-chip via the boundary outputs and receive test data off-chip
via the boundary inputs. As such, the EXTEST instruction is the workhorse of
IEEE. Std 1149.1, providing for probe-less testing of solder-joint opens/shorts
and of logic cluster function.
IDCODE
The optional IDCODE instruction allows the IC to remain in its functional mode
and selects the optional device identification register to be connected between
TDI and TDO. The device identification register is a 32-bit shift register containing
information regarding the IC manufacturer, device type, and version code.
Accessing the device identification register does not interfere with the operation
of the IC. Also, access to the device identification register should be immediately
available, via a TAP data-scan operation, after power-up of the IC or after the
TAP has been reset using the optional
TRST pin or by otherwise moving to the
Test-Logic-Reset state.
SAMPLE/PRELOAD
The required SAMPLE/PRELOAD instruction allows the IC to remain in a
normal functional mode and selects the boundary-scan register to be connected
between TDI and TDO. During this instruction, the boundary-scan register can
be accessed via a date scan operation, to take a sample of the functional data
entering and leaving the IC. This instruction is also used to preload test data into
the boundary-scan register before loading an EXTEST instruction.
Device
Part# Field
IDT72T3645
0405
IDT72T3655
0404
IDT72T3665
0403
IDT72T3675
0402
IDT72T3685
0401
IDT72T3695
0400
IDT72T36105
0416
IDT72T36115
0415
IDT72T36125
0414
35
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
HIGH-IMPEDANCE
The optional High-Impedance instruction sets all outputs (including two-state
as well as three-state types) of an IC to a disabled (high-impedance) state and
selects the one-bit bypass register to be connected between TDI and TDO.
During this instruction, data can be shifted through the bypass register from TDI
to TDO without affecting the condition of the IC outputs.
BYPASS
The required BYPASS instruction allows the IC to remain in a normal
functional mode and selects the one-bit bypass register to be connected
between TDI and TDO. The BYPASS instruction allows serial data to be
transferred through the IC from TDI to TDO without affecting the operation of
the IC.
36
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 9. Master Reset Timing
5907 drw14
RT
SEN
t
RSF
t
RSF
OE = HIGH
OE = LOW
PAE
PAF, HF
Q
0
- Q
n
t
RSF
EF/OR
FF/IR
t
RSF
t
RSF
If FWFT = HIGH,
OR = HIGH
If FWFT = LOW,
EF = LOW
If FWFT = LOW,
FF = HIGH
If FWFT = HIGH,
IR = LOW
t
RSS
t
RSS
PFM
t
HRSS
IP
t
RS
MRS
t
RSR
REN
t
RSS
FWFT/SI
t
RSR
t
RSR
WEN
FSEL0,
FSEL1
OW,
IW, BM
BE
LD
t
RSR
t
RSS
WHSTL
RHSTL
SHSTL
t
RSS
t
RSS
t
RSS
t
RSS
t
RSS
t
RSS
t
RSS
t
HRSS
t
HRSS
NOTE:
1. During Master Reset the High-Impedance control of the Qn data outputs is provided by
OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
37
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 10. Partial Reset Timing
t
RS
PRS
t
RSR
REN
t
RSS
5907 drw15
t
RSR
WEN
RT
SEN
t
RSF
t
RSF
OE = HIGH
OE = LOW
PAE
PAF, HF
Q
0
- Q
n
t
RSF
EF/OR
FF/IR
t
RSF
t
RSF
If FWFT = HIGH,
OR = HIGH
If FWFT = LOW,
EF = LOW
If FWFT = LOW,
FF = HIGH
If FWFT = HIGH,
IR = LOW
t
RSS
t
RSS
t
RSS
NOTE:
1. During Partial Reset the High-Impedance control of the Qn data outputs is provided by
OE only, RCS can be HIGH or LOW until the first rising edge of RCLK after Master Reset
is complete.
38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 11. Write Cycle and Full Flag Timing (IDT Standard Mode)
D
0
- D
n
WEN
RCLK
REN
t
ENH
t
ENH
Q
0
- Q
n
DATA READ
NEXT DATA READ
t
SKEW1
(1)
5907 drw16
WCLK
NO WRITE
1
2
1
2
NO WRITE
t
WFF
t
A
t
ENS
t
ENS
(1)
t
DS
t
A
D
X
t
DH
t
CLK
t
CLKH
FF
RCS
t
ENS
t
RCSLZ
t
WFF
t
SKEW1
t
CLKL
D
X+1
t
WFF
t
WFF
t
DS
t
DH
Figure 12. Read Cycle, Output Enable, Empty Flag and First Data Word Latency (IDT Standard Mode)
5907 drw17
D0 - Dn
t
DS
t
DH
D
0
D
1
t
DS
t
DH
NO OPERATION
RCLK
REN
EF
t
CLK
t
CLKH
t
CLKL
t
ENH
t
REF
t
A
t
OLZ
Q0 - Qn
OE
WCLK
(1)
t
SKEW1
WEN
t
ENS
t
ENS
t
ENH
1
2
t
OLZ
NO OPERATION
LAST WORD
D
0
D
1
t
ENS
t
ENH
t
OHZ
LAST WORD
t
REF
t
ENH
t
ENS
t
A
t
A
t
REF
t
ENS
t
ENH
WCS
t
OE
t
WCSS
t
WCSH
NOTES:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH (after one RCLK cycle plus t
REF
). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
, then
EF deassertion may be delayed one extra RCLK cycle.
2.
LD = HIGH.
3. First data word latency = t
SKEW1
+ 1*T
RCLK
+ t
REF.
4.
RCS is LOW.
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH (after one WCLK cycle pus t
WFF
). If the time between the
rising edge of the RCLK and the rising edge of the WCLK is less than t
SKEW1
, then the
FF deassertion may be delayed one extra WCLK cycle.
2.
LD = HIGH, OE = LOW, EF = HIGH.
3.
WCS = LOW.
39
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 13. Read Cycle and Read Chip Select (IDT Standard Mode)
RCLK
REN
1
2
5907 drw 18
RCS
Q0 - Qn
WCLK
WEN
Dn
t
ENS
LAST DATA
D
x
t
ENS
t
ENS
t
ENS
EF
t
A
t
REF
t
REF
t
RCSLZ
LAST DATA-1
t
RCSHZ
t
RCSLZ
t
A
t
RCSHZ
t
SKEW1
(1)
t
ENH
t
ENS
t
DH
t
DS
t
ENH
NOTES:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH (after one RCLK cycle plus t
REF
). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW1
, then
EF deassertion may be delayed one extra RCLK cycle.
2.
LD = HIGH.
3. First data word latency = t
SKEW1
+ 1*T
RCLK
+ t
REF.
4.
OE is LOW.
40
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 14. Write Timing (First Word Fall Through Mode)
NOTES:
1.
t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
OR
will go LOW after two RCLK cycles plus t
REF
. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW1
, then
OR
assertion may be delayed one extra RCLK cycle.
2.
t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE
will go HIGH after one RCLK cycle plus t
PAES
. If the time between the rising edge of WCLK and the rising edge of RCLK
is less than t
SKEW2
, then the
PAE
deassertion may be delayed one extra RCLK cycle.
3.
LD
= HIGH,
OE
= LOW
4
.
n =
PAE
offset, m =
PAF
offset and D = maximum FIFO depth.
5. D = 1,025 for IDT72T3645, 2,049 for IDT72T3655, 4,097 for IDT72T3665, 8,193 for IDT72T3675, 16,385 for IDT72T3685, 32,769 f
or the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
6
.
First data word latency = t
SKEW1
+ 2*T
RCLK
+ t
REF.
W
1
W
2
W
4
W
[n +2]
W
[D-m-1]
W
[D-m-2]
W
[D-1]
W
D
W
[n+3]
W
[n+4]
W
[D-m]
W
[D-m+1]
WCLK
WEN
D0 - Dn
RCLK
t
DH
t
DS
t
SKEW1
(1)
REN
Q0 - Qn
PAF
HF
PAE
IR
t
DS
t
DS
t
DS
t
SKEW2
t
A
t
REF
OR
t
PAES
t
HF
t
PAFS
t
WFF
W
[D-m+2]
W
1
t
ENH
5907 drw 19
PREVIOUS DATA IN OUTPUT REGISTER
(2)
W
3
1
2
3
1
D-1
]
[
W
D-1
]
[
W
D-1
]
[
W
1
2
t
ENS
RCS
t
RCSLZ
t
ENS
41
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 15. Read Timing (First Word Fall Through Mode)
WCLK
12
WEN
D0 - Dn
RCLK
t
ENS
REN
Q0 - Qn
PAF
HF
PAE
IR
OR
W
1
W
1
W
2
W
3
W
m+2
W
[m+3]
t
OHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
OE
t
A
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
OE
t
SKEW2
W
D
5907 drw20
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
t
HF
t
REF
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
t
ENS
D-1
]
[
W
D-1
]
[
W
1
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
IR
will go LOW after one WCLK cycle plus t
WFF
. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW1
, then the
IR
assertion may be delayed one extra WCLK cycle.
2.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF
will go HIGH after one WCLK cycle plus t
PAFS
. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2
, then the
PAF
deassertion may be delayed one extra WCLK cycle.
3.
LD
= HIGH.
4.
n
=

PAE
Offset, m =
PAF
offset and D = maximum FIFO depth.
5
.
D = 1,025 for IDT72T3645, 2,049 for IDT72T3655, 4,097 for IDT72T3665, 8,193 for IDT72T3675, 16,385 for IDT72T3685, 32,769 for
the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
6.
RCS
= LOW.
42
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 16. Read Cycle and Read Chip Select Timing (First Word Fall Through Mode)
WCLK
12
WEN
D0 - Dn
RCLK
REN
Q0 - Qn
PAF
HF
PAE
IR
OR
W
1
W
2
W
3
W
m+2
W
[m+3]
t
RCSHZ
t
SKEW1
t
ENH
t
DS
t
DH
t
A
t
A
t
PAFS
t
WFF
t
WFF
t
ENS
RCS
t
SKEW2
W
D
5907 drw21
t
PAES
W
[D-n]
W
[D-n-1]
t
A
t
A
W
[D-1]
W
D
t
A
W
[D-n+1]
W
[m+4]
W
[D-n+2]
(1)
(2)
t
ENS
1
t
ENS
t
RCSLZ
t
ENS
t
HF
t
REF
D-1
]
[
W
D-1
]
[
W
t
ENH
NOTES:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
IR
will go LOW after one WCLK cycle plus t
WFF
. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW1
, then the
IR
assertion may be delayed one extra WCLK cycle.
2.
t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF
will go HIGH after one WCLK cycle plus t
PAFS
. If the time between the rising edge of RCLK and the rising edge of WCLK
is less than t
SKEW2
, then the
PAF
deassertion may be delayed one extra WCLK cycle.
3.
LD
= HIGH.
4.
n
=

PAE
Offset, m =
PAF
offset and D = maximum FIFO depth.
5
.
D = 1,025 for IDT72T3645, 2,049 for IDT72T3655, 4,097 for IDT72T3665, 8,193 for IDT72T3675, 16,385 for IDT72T3685, 32,769 for
the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for
the IDT72T36125.
6.
OE
= LOW.
43
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
WCLK
RCLK
REN
Qn
12
WEN
3
t
ENS
t
ENH
t
ENS
t
ENS
t
ENS
t
ENH
t
ENS
t
REF
t
REF
RCS
OR
t
RCSLZ
W1
W2
t
RCSHZ
t
RCSLZ
t
A
W2
t
SKEW
t
ENS
t
ENH
W2
Dn
t
DH
t
DS
t
DH
t
DS
W1
1st Word falls through to
O/P register on this cycle
5907 drw22
HIGH-Z
Figure 17 .
RCS
and
REN
Read Operation (FWFT Mode)
NOTES:
1
.
It is very important that the
REN
be held HIGH for at least one cycle after
RCS
has gone LOW. If
REN
goes LOW on the same cycle as
RCS
or earlier, then Word, W1 will be lost, Word, W2 will be read on the output when the
bus goes to LOW-Z.
2
.
The 1st Word will fall through to the output register regardless of
REN
and
RCS
. However, subsequent reads require that both
REN
and
RCS
be active, LOW.
44
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
t
REF
t
ENS
t
ENH
5907 drw23
t
ENS
W
MK-1
WCLK
RCLK
REN
RT
EF
PAF
HF
PAE
Q
n
12
1
t
PAFS
t
REF
2
WEN
t
ENS
t
A
t
ENS
W
MK
W
MK+1
t
A
t
A
W
MK+n
t
A
W
MK
W
MK+1
t
A
t
ENS
MARK
t
ENH
t
ENS
t
PAES
(6)
t
A
t
SKEW2
t
HF
3
Figure 18. Retransmit from Mark (IDT Standard Mode)
NOTES:
1
.
Retransmit setup is complete when
EF
returns HIGH.
2.
OE
= LOW;
RCS
= LOW.
3.
RT
must be HIGH when reading from FIFO.
4
.
Once MARK is set, the write pointer will not increment past the `marked' location, preventing overwrites of Retransmit data.
5
.
Before a "MARK" can be set there must be at least x number of bytes of data between the Write Pointer and Read Pointer locati
ons. x = 32 for the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695, x = 128 for the
IDT72T36105/72T36115, x = 256 for the IDT72T36125. Remember, 4 (x9) bytes = 2 (x18) words = 1 (x36) long word.
6
.
A transition in the
PAE
flag may occur one RCLK cycle earlier than shown, (on cycle 2).
45
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 19. Retransmit from Mark (First Word Fall Through Mode)
t
REF
t
ENS
t
ENH
5907 drw24
t
ENS
W
MK-1
WCLK
RCLK
REN
RT
OR
PAF
HF
PAE
Q
n
12
1
t
PAFS
t
REF
2
WEN
t
ENS
t
A
t
ENS
W
MK
W
MK+1
t
A
t
A
W
MK+n
t
A
W
MK+1
W
MK+2
t
A
t
ENS
MARK
t
ENH
t
ENS
t
PAES
(6)
t
A
t
SKEW2
W
MK
t
A
t
HF
3
NOTES:
1
.
Retransmit setup is complete when
OR
returns LOW.
2.
OE
= LOW;
RCS
= LOW.
3.
RT
must be HIGH when reading from FIFO.
4
.
Once MARK is set, the write pointer will not increment past the `marked' location, preventing overwrites of Retransmit data.
5
.
Before a "MARK" can be set there must be at least x number of bytes of data between the Write Pointer and Read Pointer locati
ons. x = 32 for the IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695, x = 128 for the
IDT72T36105/72T36115, x = 256 for the IDT72T36125. Remember, 4 (x9) bytes = 2 (x18) words = 1 (x36) long word.
6
.
A transition in the
PAE
flag may occur one RCLK cycle earlier than shown, (on cycle 2).
46
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 20. Serial Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. X = 10 for the IDT72T3645, X = 11 for the IDT72T3655, X = 12 for the IDT72T3665, X = 13 for the IDT72T3675, X = 14 for the IDT72T3685, X = 15 for the IDT72T3695, X = 16
for the IDT72T36105, X = 17 for the IDT72T36115 and X = 18 for the IDT72T36125.
SCLK
SEN
SI
5907 drw25
LD
EMPTY OFFSET
FULL OFFSET
BIT X
(1)
t
SENS
t
LDS
t
SDS
t
SENH
t
LDS
BIT X
(1)
BIT 1
t
ENH
t
LDH
t
SDH
t
SCLK
t
SCKH
t
SCKL
BIT 1
NOTES:
1.
OE = LOW.
2. The timing diagram illustrates reading of offset registers with an output bus width of 36 bits.
3. The offset registers cannot be read on consecutive RCLK cycles. The read must be disabled (
REN = HIGH) for a minimum of one RCLK cycle in between register accesses.
Figure 22. Parallel Read of Programmable Flag Registers (IDT Standard and FWFT Modes)
Figure 21. Parallel Loading of Programmable Flag Registers (IDT Standard and FWFT Modes)
NOTE:
1. This timing diagram illustrates programming with an input bus width of 36 bits.
WCLK
LD
WEN
D
0
- D
n
5907 drw26
PAE
OFFSET
PAF
OFFSET
t
DH
t
LDH
t
ENH
t
DH
t
ENH
t
LDH
t
ENS
t
LDS
t
DS
t
CLK
t
CLKH
t
CLKL
RCLK
LD
REN
Q
0
- Q
n
DATA IN OUTPUT REGISTER
PAE OFFSET VALUE
PAF OFFSET VALUE
5907 drw27
t
LDH
t
ENH
t
CLK
t
CLKL
t
CLKH
t
A
t
LDS
t
LDH
t
LDS
t
LDH
t
LDS
t
ENS
t
ENH
t
ENS
t
ENH
t
ENS
t
A
PAE OFFSET
t
A
47
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO depth.
In IDT Standard mode: D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665 and 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768
for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT mode: D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3. t
SKEW2
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
PAF will go HIGH (after one WCLK cycle plus t
PAFS
). If the time between the
rising edge of RCLK and the rising edge of WCLK is less than t
SKEW2
, then the
PAF deassertion time may be delayed one extra WCLK cycle.
4.
PAF is asserted and updated on the rising edge of WCLK only.
5. Select this mode by setting PFM HIGH during Master Reset.
Figure 23. Synchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
RCLK
REN
5907 drw28
1
2
1
2
D-(m+1) words
in FIFO
(2)
D - m words in FIFO
(2)
D - (m +1) words in FIFO
(2)
t
ENH
t
ENS
t
PAFS
t
ENS
t
ENH
t
CLKL
t
CLKL
t
SKEW2
(3)
t
PAFS
NOTES:
1. n =
PAE offset.
2. For IDT Standard mode
3. For FWFT mode.
4. t
SKEW2
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
PAE will go HIGH (after one RCLK cycle plus t
PAES
). If the time between the
rising edge of WCLK and the rising edge of RCLK is less than t
SKEW2
, then the
PAE deassertion may be delayed one extra RCLK cycle.
5.
PAE is asserted and updated on the rising edge of WCLK only.
6. Select this mode by setting PFM HIGH during Master Reset.
7.
RCS = LOW.
Figure 24. Synchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAE
RCLK
1
2
1
2
REN
5907 drw29
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
ENS
t
SKEW2
(4)
t
ENH
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
PAES
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
t
ENS
t
ENH
t
CLKH
t
CLKL
48
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
NOTES:
1. m =
PAF offset.
2. D = maximum FIFO Depth.
In IDT Standard Mode: D=1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
In FWFT Mode: D=1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the IDT72T3685, 32,769 for the IDT72T3695,
65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3.
PAF is asserted to LOW on WCLK transition and reset to HIGH on RCLK transition.
4. Select this mode by setting PFM LOW during Master Reset.
5.
RCS = LOW.
Figure 25. Asynchronous Programmable Almost-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAF
D - (m + 1) words
in FIFO
RCLK
t
PAFA
REN
5907 drw30
D - m words
in FIFO
D - (m + 1) words in FIFO
t
ENS
t
PAFA
t
ENH
t
ENS
t
CLKL
t
CLKH
NOTES:
1. n =
PAE offset.
2. For IDT Standard Mode.
3. For FWFT Mode.
4.
PAE is asserted LOW on RCLK transition and reset to HIGH on WCLK transition.
5. Select this mode by setting PFM LOW during Master Reset.
6.
RCS = LOW.
Figure 26. Asynchronous Programmable Almost-Empty Flag Timing (IDT Standard and FWFT Modes)
WCLK
WEN
PAE
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
RCLK
REN
5907 drw31
t
PAEA
n + 1 words in FIFO
(2)
,
n + 2 words in FIFO
(3)
t
PAEA
t
ENS
t
ENS
t
ENH
t
CLKL
t
CLKH
n words in FIFO
(2)
,
n + 1 words in FIFO
(3)
49
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
NOTES:
1. In IDT Standard mode: D = maximum FIFO depth. D = 1,024 for the IDT72T3645, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665, 8,192 for the IDT72T3675, 16,384 for the
IDT72T3685, 32,768 for the IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115 and 262,144 for the IDT72T36125.
2. In FWFT mode: D = maximum FIFO depth. D = 1,025 for the IDT72T3645, 2,049 for the IDT72T3655, 4,097 for the IDT72T3665, 8,193 for the IDT72T3675, 16,385 for the
IDT72T3685, 32,769 for the IDT72T3695, 65,537 for the IDT72T36105, 131,073 for the IDT72T36115 and 262,145 for the IDT72T36125.
3.
RCS = LOW.
Figure 27. Half-Full Flag Timing (IDT Standard and FWFT Modes)
WCLK
t
ENS
t
ENH
WEN
HF
t
ENS
t
HF
RCLK
t
HF
REN
5907 drw32
t
CLKL
t
CLKH
D/2 words in FIFO
(1)
,
[
+ 1
]
words in FIFO
(2)
D-1
2
D/2 + 1 words in FIFO
(1)
,
[
+ 2
]
words in FIFO
(2)
D/2 words in FIFO
(1)
,
[
+ 1
]
words in FIFO
(2)
D-1
2
D-1
2
50
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 28. Echo Read Clock & Read Enable Operation (IDT Standard Mode Only)
t
ENS
t
ENH
t
ENS
RCS
RCLK
REN
Qn
t
ERCLK
t
ENS
5907 drw33
ERCLK
t
ENH
EREN
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
t
REF
EF
W
D-4
t
A
t
OLZ
t
OHZ
t
A
t
OLZ
t
A
t
A
Last Word, W
D
W
D-3
W
D-3
W
D-2
W
D-1
t
CLKEN
t
CLKEN
NOTES:
1
.
The
EREN
output is an "ANDed" function of
RCS
and
REN
and will follow these inputs provided that the FIFO is not empty. If the FIFO is empty,
EREN
will go HIGH, thus preventing any reads.
2
.
The
EREN
output is synchronous to RCLK.
51
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 29. Echo RCLK and Echo
REN
Operation (FWFT Mode Only)
NOTE:
1. The O/P Register is the internal output register. Its contents are available on the Qn output bus only when
RCS and OE are both active, LOW, that is the bus is not in High-
Impedance state.
2.
OE is LOW.
Cycle:
a&b. At this point the FIFO is empty,
OR is HIGH.
RCS and REN are both disabled, the output bus is High-Impedance.
c.
Word Wn+1 falls through to the output register,
OR goes active, LOW.
RCS is HIGH, therefore the Qn outputs are High-Impedance. EREN goes LOW to indicate that a new word has been placed on the output register.
d .
EREN goes HIGH, no new word has been placed on the output register on this cycle.
e.
No Operation.
f.
RCS is LOW on this cycle, therefore the Qn outputs go to Low-Impedance and the contents of the output register (Wn+1) are made available.
NOTE: In FWFT mode is important to take
RCS active LOW at least one cycle ahead of REN, this ensures the word (Wn+1) currently in the output register is made
available for at least one cycle.
g .
REN goes active LOW, this reads out the second word, Wn+2.
EREN goes active LOW to indicate a new word has been placed into the output register.
h .
Word Wn+3 is read out,
EREN remains active, LOW indicating a new word has been read out.
NOTE: Wn+3 is the last word in the FIFO.
i .
This is the next enabled read after the last word, Wn+3 has been read out.
OR flag goes HIGH and EREN goes HIGH to indicate that there is no new word available.
Qn
O/P
Reg.
t
A
t
REF
OR
5907 drw34
t
RCSLZ
REN
t
ENS
t
ENH
RCS
t
ENS
RCLK
a
b
c
d
e
f
g
h
i
W
n+1
WCLK
WEN
D0 - Dn
t
SKEW1
t
ENS
t
DS
t
ENH
W
n+2
W
n+3
ERCLK
EREN
t
CLKEN
t
CLKEN
t
CLKEN
t
CLKEN
W
n+1
W
n+2
W
n+3
t
A
t
REF
W
n+1
W
n+2
W
n+3
t
A
W
n
Last Word
t
A
t
A
t
DH
t
DH
t
DH
t
DS
t
DS
1
2
t
ERCLK
HIGH-Z
52
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 30. Asynchronous Write, Synchronous Read, Full Flag Operation (IDT Standard Mode)
Figure 31. Asynchronous Write, Synchronous Read, Empty Flag Operation (IDT Standard Mode)
RCLK
REN
5907 drw35
FF
Qn
W
0
t
A
W
1
t
ENH
t
ENS
t
FFA
t
FFA
t
FFA
WR
t
CYH
Dn
t
DS
W
D
t
DH
W
D+1
t
CYC
RCLK
REN
5907 drw36
Qn
Last Word
t
A
W
0
t
ENH
t
ENS
t
SKEW
WR
Dn
W
0
t
DH
1
2
t
A
W
1
t
REF
t
REF
EF
t
CYL
t
DS
t
CYH
W
1
t
DH
t
DS
t
CYC
NOTE:
1.
OE = LOW, WEN = LOW and RCS = LOW.
NOTE:
1.
OE = LOW, WEN = LOW and RCS = LOW.
53
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 32. Synchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
Figure 33. Synchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
WCLK
WEN
5907 drw37
Qn
t
SKEW
RD
Dn
D
F
1
2
t
WFF
t
WFF
FF
t
CYL
t
CYH
Last Word
No Write
D
F+1
t
AA
W
X
t
AA
W
X+1
t
CYC
WCLK
WEN
5907 drw38
Qn
Last Word in Output Register
W
0
RD
Dn
t
EFA
EF
t
CYH
t
ENS
t
ENH
W
0
t
DS
t
DH
t
EFA
t
AA
t
RPE
NOTE:
1.
OE = LOW, RCS = LOW and REN = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
NOTE:
1.
OE = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
54
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
Figure 34. Asynchronous Write, Asynchronous Read, Empty Flag Operation (IDT Standard Mode)
Figure 35. Asynchronous Write, Asynchronous Read, Full Flag Operation (IDT Standard Mode)
5907 drw39
Qn
Last Word in O/P Register
t
AA
W
0
t
CYH
WR
Dn
W
0
t
DH
t
AA
W
1
t
EFA
t
EFA
EF
t
CYL
W
1
t
DH
t
DS
RD
t
CYC
t
RPE
5907 drw40
t
CYH
WR
Dn
W
y
t
DH
t
FFA
FF
t
CYL
t
DS
W
y+1
t
DH
t
DS
RD
W
x
t
AA
W
x+1
W
x+2
Qn
t
FFA
t
CYC
t
CYH
t
CYL
t
CYC
t
AA
NOTES:
1.
OE = LOW, WEN = LOW, REN = LOW and RCS = LOW
2. Asynchronous Read is available in IDT Standard Mode only.
NOTES:
1.
OE = LOW, WEN = LOW, REN = LOW and RCS = LOW.
2. Asynchronous Read is available in IDT Standard Mode only.
55
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
OPTIONAL CONFIGURATIONS
WIDTH EXPANSION CONFIGURATION
Word width may be increased simply by connecting together the control
signals of multiple devices. Status flags can be detected from any one device.
The exceptions are the
EF and FF functions in IDT Standard mode and the IR
and
OR functions in FWFT mode. Because of variations in skew between RCLK
and WCLK, it is possible for
EF/FF deassertion and IR/OR assertion to vary
by one cycle between FIFOs. In IDT Standard mode, such problems can be
avoided by creating composite flags, that is, ANDing
EF of every FIFO, and
separately ANDing
FF of every FIFO. In FWFT mode, composite flags can
be created by ORing
OR of every FIFO, and separately ORing IR of every
FIFO.
Figure 36 demonstrates a width expansion using two IDT72T3645/
72T3655/72T3665/72T3675/72T3685/72T3695/72T36105/72T36115/
72T36125 devices. D
0
- D
35
from each device form a 72-bit wide input bus and
Q
0
-Q
35
from each device form a 72-bit wide output bus. Any word width can
be attained by adding additional IDT72T3645/72T3655/72T3665/72T3675/
72T3685/72T3695/72T36105/72T36115/72T36125 devices.
NOTES:
1. Use an AND gate in IDT Standard mode, an OR gate in FWFT mode.
2. Do not connect any output control signals directly together.
3. FIFO #1 and FIFO #2 must be the same depth, but may be different word widths.
Figure 36. Block Diagram of 1,024 x 72, 2,048 x 72, 4,096 x 72, 8,192 x 72, 16,384 x 72, 32,768 x 72, 65,536 x 72, 131,072 x 72 and 262,144 x 72
Width Expansion
WRITE CLOCK (WCLK)
m + n
m
n
MASTER RESET (
MRS)
READ CLOCK (RCLK)
DATA OUT
n
m + n
WRITE ENABLE (
WEN)
FULL FLAG/INPUT READY (
FF/IR)
PROGRAMMABLE (
PAF)
PROGRAMMABLE (
PAE)
EMPTY FLAG/OUTPUT READY (
EF/OR) #2
OUTPUT ENABLE (
OE)
READ ENABLE (
REN)
m
LOAD (
LD)
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
EMPTY FLAG/OUTPUT READY (
EF/OR) #1
PARTIAL RESET (
PRS)
5907 drw41
FULL FLAG/INPUT READY (
FF/IR) #2
HALF-FULL FLAG (
HF)
FIRST WORD FALL THROUGH/
SERIAL INPUT (FWFT/SI)
RETRANSMIT (
RT)
#1
FIFO
#2
GATE
(1)
GATE
(1)
D
0
- D
m
DATA IN
D
m+1
- D
n
Q
0
- Qm
Q
m+1
- Q
n
FIFO
#1
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
READ CHIP SELECT (
RCS)
SERIAL CLOCK (SCLK)
56
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72T3645/55/65/75/85/95/105/115/125 2.5V TeraSync
36-BIT FIFO
1K x 36, 2K x 36, 4K x 36, 8K x 36, 16K x 36, 32K x 36, 64K x 36, 128K x 36 and 256K x 36
DEPTH EXPANSION CONFIGURATION (FWFT MODE ONLY)
The IDT72T3645 can easily be adapted to applications requiring depths
greater than 1,024, 2,048 for the IDT72T3655, 4,096 for the IDT72T3665,
8,192 for the IDT72T3675, 16,384 for the IDT72T3685, 32,768 for the
IDT72T3695, 65,536 for the IDT72T36105, 131,072 for the IDT72T36115
and 262,144 for the IDT72T36125 with an 18-bit bus width. In FWFT mode,
the FIFOs can be connected in series (the data outputs of one FIFO connected
to the data inputs of the next) with no external logic necessary. The resulting
configuration provides a total depth equivalent to the sum of the depths
associated with each single FIFO. Figure 37 shows a depth expansion using
two IDT72T3645/72T3655/72T3665/72T3675/72T3685/72T3695/
72T36105/72T36115/72T36125 devices.
Care should be taken to select FWFT mode during Master Reset for all FIFOs
in the depth expansion configuration. The first word written to an empty
configuration will pass from one FIFO to the next ("ripple down") until it finally
appears at the outputs of the last FIFO in the chain no read operation is
necessary but the RCLK of each FIFO must be free-running. Each time the
data word appears at the outputs of one FIFO, that device's
OR line goes LOW,
enabling a write to the next FIFO in line.
For an empty expansion configuration, the amount of time it takes for
OR of
the last FIFO in the chain to go LOW (i.e. valid data to appear on the last FIFO's
outputs) after a word has been written to the first FIFO is the sum of the delays
for each individual FIFO:
(N 1)*(4*transfer clock) + 3*T
RCLK
where N is the number of FIFOs in the expansion and T
RCLK
is the RCLK
period. Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between WCLK and transfer clock, or RCLK and transfer
clock, for the
OR flag.
The "ripple down" delay is only noticeable for the first word written to an empty
depth expansion configuration. There will be no delay evident for subsequent
words written to the configuration.
The first free location created by reading from a full depth expansion
configuration will "bubble up" from the last FIFO to the previous one until it finally
moves into the first FIFO of the chain. Each time a free location is created in one
FIFO of the chain, that FIFO's
IR line goes LOW, enabling the preceding FIFO
to write a word to fill it.
For a full expansion configuration, the amount of time it takes for
IR of the first
FIFO in the chain to go LOW after a word has been read from the last FIFO is
the sum of the delays for each individual FIFO:
(N 1)*(3*transfer clock) + 2 T
WCLK
where N is the number of FIFOs in the expansion and T
WCLK
is the WCLK
period. Note that extra cycles should be added for the possibility that the t
SKEW1
specification is not met between RCLK and transfer clock, or WCLK and transfer
clock, for the
IR flag.
The Transfer Clock line should be tied to either WCLK or RCLK, whichever
is faster. Both these actions result in data moving, as quickly as possible, to the
end of the chain and free locations to the beginning of the chain.
Figure 37. Block Diagram of 2,048 x 36, 4,096 x 36, 8,192 x 36, 16,384 x 36, 32,768 x 36, 65,536 x 36, 131,072 x 36, 262,144 x 36 and 524,288 x 36
Depth Expansion
Dn
INPUT READY
WRITE ENABLE
WRITE CLOCK
WEN
WCLK
IR
DATA IN
RCLK
READ CLOCK
RCLK
REN
OE
OUTPUT ENABLE
OUTPUT READY
Qn
Dn
IR
GND
WEN
WCLK
OR
REN
OE
Qn
READ ENABLE
OR
DATA OUT
TRANSFER CLOCK
5907 drw42
n
n
n
FWFT/SI
FWFT/SI
FWFT/SI
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
RCS
READ CHIP SELECT
RCS
IDT
72T3645
72T3655
72T3665
72T3675
72T3685
72T3695
72T36105
72T36115
72T36125
57
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
Plastic Ball Grid Array, PBGA BB208-1 (72T3645/55/65/75/85/95 Only)
Plastic Ball Grid Array, PBGA BB240-1 (72T36105/115/125 Only)
Commercial (0
C to +70C)
Industrial (-40
C to +85C)
Low Power
5907 drw43
Commercial Only
Commercial and Industrial
Commercial Only
Commercial Only
4-4
5
6-7
10
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Process /
Temperature
Range
BLANK
I
(1)
72T3645
1,024 x 36
2.5V TeraSync FIFO
72T3655
2,048 x 36
2.5V TeraSync FIFO
72T3665
4,096 x 36
2.5V TeraSync FIFO
72T3675
8,192 x 36
2.5V TeraSync FIFO
72T3685
16,384 x 36
2.5V TeraSync FIFO
72T3695
32,768 x 36
2.5V TeraSync FIFO
72T36105
65,536 x 36
2.5V TeraSync FIFO
72T36115
131,072 x 36
2.5V TeraSync FIFO
72T36125
262,144 x 36
2.5V TeraSync FIFO
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
BB
BB
L
DATASHEET DOCUMENT HISTORY
05/30/2001
pgs. 17, and 18.
07/09/2001
pgs. 1, 7, 8, 19, and 51.
09/07/2001
pgs. 1-53.
09/11/2001
pg. 8.
11/19/2001
pgs. 1, 9, 12, 40, and 41.
11/29/2001
pgs. 1, 40, and 41.
01/15/2002
pg. 42.
03/04/2002
pgs. 9, 10, and 29.
06/05/2002
pgs. 9, 10, and 14.
02/11/2003
pgs. 8, 9, and 33.
03/03/2003
pgs. 1, 11-13, 31, and 33-35.
NOTE:
1. Industrial temperature range product for 5ns speed is available as a standard device. All other speed grades are available by special order.