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Электронный компонент: 72V12081

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1
3.3 VOLT MULTIMEDIA FIFO
256 x 8, 512 x 8,
1,024 x 8, 2,048 x 8,
and 4,096 x 8
PRELIMINARY
IDT72V10081, IDT72V11081
IDT72V12081, IDT72V13081
IDT72V14081
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6161/1
APRIL 2003
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGES
DESCRIPTION:
The IDT72V10081/72V11081/72V12081/72V13081/72V14081 devices
are low-power First-In, First-Out (FIFO) memories with clocked read and write
controls. These devices have a 256, 512, 1,024, 2,048 and 4,096 x 8-bit
memory array, respectively. These FIFOs are applicable for a wide variety of
data buffering needs such as graphics and interprocessor communication.
These FIFOs have 8-bit input and output ports. The input port is
controlled by a free-running clock (WCLK) and Write Enable pin (
WEN).
Data is written into the Multimedia FIFO on every rising clock edge when
the Write Enable pin is asserted. The output port is controlled by another
clock pin (RCLK) and Read Enable pin (
REN). The Read Clock can be
tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual-clock operation. An Output Enable
pin (
OE) is provided on the read port for three-state control of the output.
The Multimedia FIFOs have two fixed flags, Empty (
EF) and Full (FF).
These FIFOs are fabricated using IDT's submicron CMOS technology.
FEATURES:




256 x 8-bit organization array (IDT72V10081)




512 x 8-bit organization array (IDT72V11081)




1,024 x 8-bit organization array (IDT72V12081)




2,048 x 8-bit organization array (IDT72V13081)




4,096 x 8-bit organization array (IDT72V14081)




15 ns read/write cycle time




5V input tolerant




Independent Read and Write clocks




Empty and Full Flags signal FIFO status




Output Enable puts output data bus in high-impedance state




Available in 32-pin plastic Thin Quad FlatPack (TQFP)




Industrial temperature range (40


C to +85C)
FUNCTIONAL BLOCK DIAGRAM
RESET LOGIC
FLAG OUTPUTS
WRITE
CONTROL
READ
CONTROL
FIFO ARRAY
WCLK
WEN
D
0
- D
7
Data In
x8
RS
EF
Q
0
- Q
7
Data Out
x8
RCLK
REN
6161 drw01
FF
OE
2
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
Symbol
Name
I/O
Description
D
0
-D
7
Data Inputs
I
Data inputs for a 8-bit bus.
EF
Empty Flag
O
When
EF
is LOW, the FIFO is empty and further data reads from the output are inhibited. When
EF
is
HIGH, the FIFO is not empty.
EF
is synchronized to RCLK.
FF
Full Flag
O
When
FF
is LOW, the FIFO is full and further data writes into the input are inhibited. When
FF
is HIGH, the FIFO
is not full.
FF
is synchronized to WCLK.
OE
Output Enable
I
When
OE
is LOW, the data output bus is active. If
OE
is HIGH, the output data bus will be in a high-impedance
state.
Q
0
-Q
7
Data Outputs
O
Data outputs for a 8-bit bus.
RCLK
Read Clock
I
Data is read from the FIFO on a LOW-to-HIGH transition of RCLK when
REN
is asserted.
REN
Read Enable
I
When
REN
is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK.
Data will not be read from the FIFO if the
EF
is LOW.
RS
Reset
I
When
RS
is set LOW, internal read and write pointers are set to the first location of the RAM array,
FF
goes HIGH, and
EF
goes LOW. A Reset is required before an initial Write after power-up.
WCLK
Write Clock
I
Data is written into the FIFO on a LOW-to-HIGH transition of WCLK when the Write Enable is asserted.
WEN
Write Enable
I
When
WEN
is LOW, data is written into the FIFO on every LOW-to-HIGH transition WCLK. Data
will not be written into the FIFO if the
FF
is LOW.
V
CC
Power
I
3.3V volt power supply.
GND
Ground
I
Ground pin.
TQFP (PR32-1, order code: PF)
TOP VIEW
PIN CONFIGURATION
PIN DESCRIPTIONS
RS
WEN
WCLK
V
CC
V
CC
Q
1
Q
2
Q
3
5
6
7
8
16
D
6
GND
RCLK
GND
D
7
27 26 25
24
23
22
21
29 28
32 31 30
9 10 11 12 13 14 15
D
5
GND
6161 drw02
Q
4
DNC
(1)
Q
5
Q
6
Q
7
EF
OE
FF
1
2
3
4
20
19
18
17
INDEX
Q
0
REN
D
4
D
3
D
2
D
1
D
0
DNC
(1)
DNC
(1)
NOTE:
1. DNC = Do Not Connect.
3
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
IDT72V10081
IDT72V11081
IDT72V12081
IDT72V13081
IDT72V14081
Industrial
t
CLK
= 15 ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
I
LI
(1)
Input Leakage Current (Any Input)
1
--
1
A
I
LO
(2)
Output Leakage Current
10
--
10
A
V
OH
Output Logic "1" Voltage, I
OH
= 2mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage, I
OL
= 8mA
--
--
0.4
V
I
CC1
(3,4,5)
Active Power Supply Current
--
--
20
mA
I
CC2
(3,6)
Standby Current
--
--
5
mA
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
(2)
Input Capacitance
V
IN
= 0V
10
pF
C
OUT
(1,2)
Output Capacitance
V
OUT
= 0V
10
pF
NOTES:
1. With output deselected (
OE
V
IH
).
2.
Characterized values, not currently tested.
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 3.3V 0.3V, T
A
= -40
C to +85C)
NOTES:
1. Measurements with 0.4
VIN VCC.
2.
OE
V
IH,
0.4
V
OUT
V
CC
.
3. Tested with outputs disabled (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical I
CC1
= 0.17 + 0.48*f
S
+ 0.02*C
L
*f
S
(in mA) with V
CC
= 3.3V, T
A
= 25
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2,
C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
ABSOLUTE MAXIMUM RATINGS
(1)
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminal only.
Symbol
Rating
Industrial
Unit
V
TERM
(2)
Terminal Voltage with
0.5 to +5
V
Respect to GND
T
STG
Storage Temperature
55 to +125
C
I
OUT
DC Output Current
50 to +50
mA
RECOMMENDED OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage Industrial
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage Industrial
2.0
--
5.5
V
V
IL
Input Low Voltage Industrial
-0.5
--
0.8
V
T
A
Operating Temperature
-40
--
85
C
Industrial
4
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
*Includes jig and scope capacitances.
AC TEST CONDITIONS
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
or equivalent circuit
Figure 1. Output Load
AC ELECTRICAL CHARACTERISTICS
(1)
(Industrial: V
CC
= 3.3 0.3V, TA = -40
C to + 85C)
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
Industrial
IDT72V10081L15
IDT72V11081L15
IDT72V12081L15
IDT72V13081L15
IDT72V14081L15
Symbol
Parameter
Min.
Max.
Unit
f
S
Clock Cycle Frequency
--
66.7
MHz
t
A
Data Access Time
2
10
ns
t
CLK
Clock Cycle Time
15
--
ns
t
CLKH
Clock High Time
6
--
ns
t
CLKL
Clock Low Time
6
--
ns
t
DS
Data Setup Time
4
--
ns
t
DH
Data Hold Time
1
--
ns
t
ENS
Enable Setup Time
4
--
ns
t
ENH
Enable Hold Time
1
--
ns
t
RS
Reset Pulse Width
(1)
15
--
ns
t
RSS
Reset Setup Time
10
--
ns
t
RSR
Reset Recovery Time
10
--
ns
t
RSF
Reset to Flag and Output Time
--
15
ns
t
OLZ
Output Enable to Output in Low-Z
(2)
0
--
ns
t
OE
Output Enable to Output Valid
3
8
ns
t
OHZ
Output Enable to Output in High-Z
(2)
3
8
ns
t
WFF
Write Clock to Full Flag
--
10
ns
t
REF
Read Clock to Empty Flag
--
10
ns
t
SKEW1
Skew time between Read Clock & Write
6
--
ns
Clock for Empty Flag &Full Flag
30pF*
330
3.3V
510
D.U.T.
6161 drw03
5
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
SIGNAL DESCRIPTIONS
INPUTS:
DATA IN (D0 - D7)
Data inputs for 8-bit wide data.
CONTROLS:
RESET (
RS)
Reset is accomplished whenever the Reset (
RS) input is taken to a LOW state.
During reset, both internal read and write pointers are set to the first location.
A reset is required after power-up before a write operation can take place. The
Full Flag (
FF) will be reset to HIGH after t
RSF
. The Empty Flag (
EF) will be
reset to LOW after t
RSF
. During reset, the output register is initialized to all zeros.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met in respect to the LOW-to-HIGH
transition of the Write Clock (WCLK). The Full Flag (FF) is synchronized with
respect to the LOW-to-HIGH transition of the Write Clock (WCLK).
The Write and Read clocks can be asynchronous or coincident.
WRITE ENABLE (
WEN)
When Write Enable (
WEN) is low, data can be loaded into the input register
and FIFO array on the LOW-to-HIGH transition of every Write Clock (WCLK).
Data is stored in the FIFO array sequentially and independently of any on-going
read operation.
To prevent data overflow, the Full Flag (
FF) will go LOW, inhibiting further
write operations. Upon the completion of a valid read cycle, the Full Flag (
FF)
will go HIGH after t
WFF
, allowing a valid write to begin. Write Enable (
WEN)
is ignored when the FIFO is full.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK). The Empty Flag (
EF)is synchronized with respect to the LOW-
to-HIGH transition of the Read Clock (RCLK).
The Write and Read clocks can be asynchronous or coincident.
READ ENABLES (
REN)
When both Read Enable (
REN) is LOW, data is read from the FIFO array
to the output register on the LOW-to-HIGH transition of the Read Clock (RCLK).
When Read Enable (
REN) is HIGH, the output register holds the previous
data and no new data is allowed to be loaded into the register.
When all the data has been read from the FIFO, the Empty Flag (
EF) will go
LOW, inhibiting further read operations. Once a valid write operation has been
accomplished, the Empty Flag (
EF) will go HIGH after t
REF
and a valid read
can begin. The Read Enable (
REN) is ignored when the FIFO is empty.
OUTPUT ENABLE (
OE)
When Output Enable (
OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When Output Enable (
OE) is disabled
(HIGH), the Q output data bus is in a high-impedance state.
OUTPUTS:
FULL FLAG (
FF)
The Full Flag (
FF) will go LOW, inhibiting further write operation, when the
device is full. If no reads are performed after Reset (
RS), the Full Flag (FF)
will go LOW after 256 writes for the IDT72V10081, 512 writes for the
IDT72V11081, 1,024 writes for the IDT72V12081, 2,048 writes for the
IDT72V13081 and 4,096 writes for the IDT72V14081.
The Full Flag (
FF) is synchronized with respect to the LOW-to-HIGH
transition of the Write Clock (WCLK).
EMPTY FLAG (
EF)
The Empty Flag (
EF) will go LOW, inhibiting further read operations, when
the read pointer is equal to the write pointer, indicating the device is empty.
The Empty Flag (
EF) is synchronized with respect to the LOW-to-HIGH
transition of the Read Clock (RCLK).
DATA OUTPUTS (Q
0
- Q7)
Data outputs for a 8-bit wide data.
6
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
NOTES:
1. After reset, the outputs will be LOW if
OE = 0 and high-impedance if OE = 1.
2. The clocks (RCLK, WCLK) can be free-running during reset.
Figure 2. Reset Timing
NOTE:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge for
FF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then
FF may not change state until the next WCLK edge.
Figure 3. Write Cycle Timing
t
RS
t
RSR
RS
REN
t
RSF
t
RSF
OE = 1
OE = 0
(1)
EF
FF
Q
0
- Q
7
6161 drw06
WEN
t
RSS
t
RSF
t
RSR
t
RSS
t
DH
t
ENH
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
DS
t
WFF
t
WFF
WCLK
D
0
- D
7
WEN
FF
RCLK
REN
NO OPERATION
6161 drw07
DATA IN VALID
t
ENS
7
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
t
DS
D
0
(First Valid
Write)
t
SKEW1
D
0
D
1
D
3
D
2
D
1
t
ENS
t
FRL
(1)
t
REF
t
A
t
OLZ
t
OE
t
A
WCLK
D
0
- D
7
RCLK
EF
REN
Q
0
- Q
7
OE
WEN
6161 drw09
t
ENS
NOTE:
1.
When t
SKEW1
minimum specification, t
FRL
= t
CLK
+ t
SKEW1
When
t
SKEW1
< minimum specification, t
FRL
= 2t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
The Latency Timings apply only at the Empty Boundary (
EF = LOW).
Figure 5. First Data Word Latency Timing
t
ENH
t
ENS
NO OPERATION
t
OLZ
VALID DATA
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
t
A
t
OE
t
OHZ
RCLK
REN
EF
Q
0
- Q
7
OE
WCLK
WEN
6161 drw08
NOTE:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge for
EF to change during the current clock cycle. If the time between
the rising edge of RCLK and the rising edge of WCLK is less than t
SKEW1
, then
EF may not change state until the next RCLK edge.
Figure 4. Read Cycle Timing
8
IDT72V10081/11081/12081/13081/14081 3.3V MULTIMEDIA FIFO
256 x 8, 512 x 8, 1,024 x 8, 2,048 x 8 and 4,096 x 8
INDUSTRIAL TEMPERATURE RANGE
Figure 7. Empty Flag Timing
Figure 6. Full Flag Timing
t
SKEW1
t
DS
t
SKEW1
t
ENH
t
ENH
NEXT DATA READ
DATA READ
WCLK
D
0
- D
7
FF
WEN
RCLK
REN
Q
0
- Q
7
t
WFF
t
WFF
t
WFF
t
ENS
t
ENS
DATA IN OUTPUT REGISTER
OE LOW
NO WRITE
NO WRITE
6161 drw10
t
A
t
A
t
ENS
t
ENS
(1)
t
ENH
NO WRITE
t
A
t
DS
t
DS
DATA WRITE 1
t
ENS
t
ENH
t
ENS
t
ENH
DATA WRITE 2
WCLK
D
0
- D
7
RCLK
EF
REN
OE
Q
0
- Q
7
DATA READ
t
SKEW1
(1)
t
FRL
t
FFL
DATA IN OUTPUT REGISTER
(1)
t
SKEW1
LOW
t
REF
t
REF
t
REF
WEN
6161 drw11
NOTE:
1.
When t
SKEW1
minimum specification, t
FRL
= t
CLK
+ t
SKEW1
When
t
SKEW1
< minimum specification, t
FRL
= 2t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
The Latency Timings apply only at the Empty Boundary (
EF = LOW).
9
CORPORATE HEADQUARTERS
for SALES:
for Tech Support:
2975 Stender Way
800-345-7015 or 408-727-6116
408-330-1753
Santa Clara, CA 95054
fax: 408-492-8674
email: FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
6161 drw18
XXXXX
IDT
Device Type
X XX
X
X
Power Speed
Package
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Process/
Temperature
Range
I
Industrial (-40
C to +85C)
PF
Plastic Thin Quad Flatpack (TQFP, PR32-1)
72V10081 256 x 8
3.3V Multimedia FIFO
72V11081 512 x 8
3.3V Multimedia FIFO
72V12081 1,024 x 8
3.3V Multimedia FIFO
72V13081 2,048 x 8
3.3V Multimedia FIFO
72V14081 4,096 x 8
3.3V Multimedia FIFO
15
Industrial
L
Low Power