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Электронный компонент: 72V14071

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1
2003 Integrated Device Technology, Inc. All rights reserved. Products specifications subject to change without notice.
DSC-6360/-
INDUSTRIAL TEMPERATURE RANGE
3.3 VOLT DUAL MULTIMEDIA FIFO
DUAL 256 x 8, DUAL 512 x 8
DUAL 1,024 x 8, DUAL 2,048 x 8
DUAL 4,096 x 8
PRELIMINARY
IDT72V10071, IDT72V11071
IDT72V12071, IDT72V13071
IDT72V14071
JUNE 2003
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
FEATURES:




Memory organization:
IDT72V10071
Dual 256 x 8
IDT72V11071
Dual 512 x 8
IDT72V12071
Dual 1,024 x 8
IDT72V13071
Dual 2,048 x 8
IDT72V14071
Dual 4,096 x 8




Offers optimal combination of large capacity, high speed,
design flexibility and small footprint




15 ns read/write cycle time




5V input tolerant




Separate control lines and data lines for each FIFO




Separate Empty and Full flags for each FIFO




Enable puts output data lines in high-impedance state




Space-saving 64-pin plastic Thin Quad Flat Pack (STQFP)




Industrial temperature range (40


C to +85C)
DESCRIPTION:
The IDT72V10071/72V11071/72V12071/72V13071/72V14071 are dual
Multimedia FIFOs. The device is functionally equivalent to two independent
FIFOs in a single package with all associated control, data, and flag lines
assigned to separate pins.
Each of the two FIFOs (designated FIFO A and FIFO B) has a 8-bit input
data port (DA0 - DA7, DB0 - DB7) and a 8-bit output data port (QA0 - QA7,
QB0 - QB7). Each input port is controlled by a free-running clock (WCLKA,
WCLKB), and a Write Enable pin (
WENA, WENB). Data is written into each of
the two arrays on every rising clock edge of the Write Clock (WCLKA, WCLKB)
when the appropriate Write Enable pin is asserted.
The output port of each FIFO bank is controlled by its associated clock pin
(RCLKA, RCLKB) and Read Enable pin (
RENA, RENB). The Read Clock can
be tied to the Write Clock for single clock operation or the two clocks can run
asynchronous of one another for dual clock operation. An Output Enable pin
(
OEA, OEB) is provided on the read port of each FIFO for three-state output
control.
Each of the two FIFOs has two fixed flags, Empty (
EFA, EFB) and Full (FFA,
FFB).
This FIFO is fabricated using IDT's high-performance submicron CMOS
technology.
FUNCTIONAL BLOCK DIAGRAM
FLAG OUTPUTS
Q
A0
- Q
A7
Data Out
x8
6360 drw01
OEA
WCLKA
EFA
FFA
RENA
RCLKA
WENA
D
A0
- D
A7
Data In
x8
RSA
RESET LOGIC
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
WRITE
CONTROL
READ
CONTROL
Q
B0
- Q
B7
Data Out
x8
OEB
WCLKB
RENB
RCLKB
WENB
D
B0
- D
B7
Data In
x8
FIFO ARRAY
256 x 8, 512 x 8
1,024 x 8, 2,048 x 8
4,096 x 8
WRITE
CONTROL
READ
CONTROL
FLAG OUTPUTS
EFB
FFB
RSB
RESET LOGIC
2
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
PIN CONFIGURATION
STQFP (PP64-1, order code: TF)
TOP VIEW
QA
6
QA
5
QA
4
DNC
(1)
QA
3
QA
2
QA
1
QA
0
V
CC
WCLKA
WENA
RSA
DA
1
DA
2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
QB
7
FFB
EFB
OEB
RCLKB
RENB
GND
Vcc
DB
7
DB
6
DB
5
DB
4
GND
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
QA
7
FFA EFA OEA
GND
RCLKA
RENA GND QB
0
QB
1
QB
2
QB
3
DNC
QB
4
QB
5
QB
6
DA
3
GND
DA
4
DA
5
DA
6
DA
7
WCLKB
WENB
RSB
DB
1
DB
2
DB
3
6360 drw02
V
CC
DA
0
DNC
(1)
DNC
(1)
V
CC
DB
0
DNC
(1)
DNC
(1)
GND
NOTE:
1. DNC = Do Not Connect.
3
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
PIN DESCRIPTIONS
The IDT72V10071/72V11071/72V12071/72V13071/72V14071's two
FIFOs, referred to as FIFO A and FIFO B, are identical in every respect.
FIFO A and FIFO B operate completely independent from each other.
Symbol
Name
I/O
Description
DA0-DA7
A Data Inputs
I
8-bit data inputs to FIFO array A.
DB0-DB7
B Data Inputs
I
8-bit data inputs to FIFO array B.
RSA, RSB
Reset
I
When
RSA (RSB) is set LOW, the associated internal read and write pointers of array A (B) are set to the first
location;
FFA (FFB) go as HIGH and EFA (EFB) go as LOW. After power-up, a reset of both FIFOs A and B
is required before an initial WRITE.
WCLKA
Write Clock
I
Data is written into the FIFO A (B) on a LOW-to-HIGH transition of WCLKA (WCLKB) when the write enable
WCLKB
is asserted.
WENA
Write Enable
I
When
WENA (WENB) is LOW, data A (B) is written into the FIFO on every LOW-to-HIGH transition WCLKA
WENB
(WCLKB). Data will not be written into the FIFO if
FFA (FFB) is LOW.
QA0-QA7
A Data Outputs
O 8-bit data outputs from FIFO array A.
QB0-QB7
B Data Outputs
O 8-bit data outputs from FIFO array B.
RCLKA
Read Clock
I
Data is read from FIFO A (B) on a LOW-to-HIGH transition of RCLKA (RCLKB) when
RENA (RENB) is
RCLKB
asserted.
RENA
Read Enable
I
When
RENA (RENB) is LOW, data is read from FIFO A (B) on every LOW-to-HIGH transition of RCLKA
RENB
(RCLKB). Data will not be read from Array A (B) if
EFA (EFB) is LOW.
OEA
Output Enable
I
When
OEA (OEB) is LOW, outputs DA0-DA7 (DB0-DB7) are active. If OEA (OEB) is HIGH, outputs
OEB
DA0-DA7 (DB0-DB7) will be in a high-impedance state.
EFA
Empty Flag
O When
EFA (EFB) is LOW, FIFO A (B) is empty and further data reads from the output are inhibited. When
EFB
EFA (EFB) is HIGH, FIFO A (B) is not empty. EFA (EFB) is synchronized to RCLKA (RCLKB).
FFA
Full Flag
O When
FFA (FFB) is LOW, FIFO A (B) is full and further data writes into the input are inhibited. When FFA
FFB
(
FFB) is HIGH, FIFO A (B) is not full. FFA (FFB) is synchronized to WCLKA (WCLKB).
V
CC
Power
+3.3V power supply pin.
GND
Ground
0V ground pin.
4
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
Symbol
Rating
Industrial
Unit
V
TERM
Terminal Voltage with
0.5 to +5
V
Respect to GND
T
STG
Storage Temperature
55 to +125
C
I
OUT
DC Output Current
50 to +50
mA
NOTE:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of the specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
RECOMMENDED OPERATING
CONDITIONS
V
CC
Supply Voltage(Industrial)
3.0
3.3
3.6
V
GND
Supply Voltage(Industrial)
0
0
--
V
V
IH
Input High Voltage (Industrial)
2.0
--
5.0
V
V
IL
Input Low Voltage (Industrial)
--
--
0.8
V
T
A
Operating Temperature
-40
85
C
Industrial
IDT72V10071
IDT72V11071
IDT72V12071
IDT72V13071
IDT72V14071
Industrial
t
CLK
= 15 ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
I
LI
(1)
Input Leakage Current (Any Input)
1
--
1
A
I
LO
(2)
Output Leakage Current
10
--
10
A
V
OH
Output Logic "1" Voltage, I
OH
= 2 mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage, I
OL
= 8 mA
--
--
0.4
V
I
CC1
(3,4,5)
Active Power Supply Current (both FIFOs)
--
--
40
mA
I
CC2
(2,6)
Standby Current
--
--
10
mA
NOTES:
1. Measurements with 0.4
V
IN
V
CC
.
2.
OEA, OEB
V
IH,
0.4
V
OUT
V
CC
.
3. Tested with outputs disabled (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHz and data inputs switch at 10 MHz.
5. Typical I
CC1
= 2[0.17 + 0.48*f
S
+ 0.02*C
L
*f
S
] (in mA).
These equations are valid under the following conditions:
V
CC
= 3.3V, T
A
= 25C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
DC ELECTRICAL CHARACTERISTICS
(Industrial :V
CC
= 3.3V 0.3V, TA = -40
C to +85C)
Symbol
Parameter
Conditions
Max.
Unit
C
IN
(2)
Input Capacitance
V
IN
= 0V
10
pF
C
OUT
(1,2)
Output Capacitance
V
OUT
= 0V
10
pF
NOTE:
1. With output deselected (
OEA, OEB
V
IH
).
2. Characterized values, not currently tested.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter
Min
Typ. Max Unit
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
NOTE:
1. Outputs are not 5V tolerant.
5
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
In Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
Industrial
IDT72V10071L15
IDT72V11071L15
IDT72V12071L15
IDT72V13071L15
IDT72V14071L15
Symbol
Parameter
Min.
Max.
Unit
f
S
Clock Cycle Frequency
--
66.7
MHz
t
A
Data Access Time
2
10
ns
t
CLK
Clock Cycle Time
15
--
ns
t
CLKH
Clock High Time
6
--
ns
t
CLKL
Clock Low Time
6
--
ns
t
DS
Data Set-up Time
4
--
ns
t
DH
Data Hold Time
1
--
ns
t
ENS
Enable Set-up Time
4
--
ns
t
ENH
Enable Hold Time
1
--
ns
t
RS
Reset Pulse Width
(1)
15
--
ns
t
RSS
Reset Set-up Time
10
--
ns
t
RSR
Reset Recovery Time
10
--
ns
t
RSF
Reset to Flag Time and Output Time
--
15
ns
t
OLZ
Output Enable to Output in Low-Z
(2)
0
--
ns
t
OE
Output Enable to Output Valid
3
8
ns
t
OHZ
Output Enable to Output in High-Z
(2)
3
8
ns
t
WFF
Write Clock to Full Flag
--
10
ns
t
REF
Read Clock to Empty Flag
--
10
ns
t
SKEW1
Skew Time Between Read Clock and Write Clock for Empty Flag and Full Flag
6
--
ns
*Includes jig and scope capacitances.
Figure 1. Output Load
or equivalent circuit
NOTES:
1. Pulse widths less than minimum values are not allowed.
2. Values guaranteed by design, not currently tested.
30pF*
330
3.3V
510
D.U.T.
6360 drw03
AC ELECTRICAL CHARACTERISTICS
(1)
(Industrial: V
CC =
3.3V 0.3V, TA = -40
C to +85C)
AC TEST CONDITIONS
6
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
Read Enable (
RENA, RENB) -- When Read Enable, RENA, (RENB) is
LOW, data is read from Array A (B) to the output register on the LOW-to-HIGH
transition of the Read Clock, RCLKA (RCLKB).
When Read Enable,
RENA, (RENB) for FIFO A (B) is HIGH, the output
register holds the previous data and no new data is allowed to be loaded into
the register.
When all the data has been read from FIFO A (B), the Empty Flag,
EFA
(
EFB) will go LOW, inhibiting further read operations. Once a valid write
operation has been accomplished,
EFA (EFB) will go HIGH after t
REF
and a
valid read can begin. The Read Enable,
RENA, (RENB) is ignored when FIFO
A (B) is empty.
Output Enable (
OEA, OEB) -- When Output Enable, OEA (OEB) is
enabled (LOW), the parallel output buffers of FIFO A (B) receive data from their
respective output register. When Output Enable,
OEA (OEB) is disabled
(HIGH), the QA (QB) output data bus is in a high-impedance state.
OUTPUTS:
Full Flag (
FFA, FFB) -- FFA (FFB) will go LOW, inhibiting further write
operations, when Array A (B) is full. If no reads are performed after reset,
FFA (FFB) will go LOW after 256 writes to the IDT72V10071's FIFO A (B), 512
writes to the IDT72V11071's FIFO A (B), 1,024 writes to the IDT72V12071's
FIFO A (B), 2,048 writes to the IDT72V13071's FIFO A (B), and 4,096 writes
to the IDT72V14071's FIFO A (B).
FFA (FFB) is synchronized with respect to the LOW-to-HIGH transition of
the Write Clock WCLKA (WCLKB).
Empty Flag (
EFA, EFB) -- EFA (EFB) will go LOW, inhibiting further read
operations, when the read pointer is equal to the write pointer, indicating that
Array A (B) is empty.
EFA (EFB) is synchronized with respect to the LOW-to-HIGH transition of
the Read Clock RCLKA (RCLKB).
Data Outputs (QA
0
QA
7,
QB
0
QB
7
) -- QA
0
- QA
7
are the eight data
outputs for memory array A, QB
0
- QB
7
are the eight data outputs for memory
array B
.
SIGNAL DESCRIPTIONS
FIFO A and FIFO B are identical in every respect. The following description
explains the interaction of input and output signals for FIFO A. The correspond-
ing signal names for FIFO B are provided in parentheses.
INPUTS:
Data In (D
A0
D
A7
, D
B0
D
B7
) -- D
A0
- D
A7
are the eight data inputs
for memory array A. D
B0
- D
B7
are the eight data inputs for memory array B.
CONTROLS:
Reset (
RSA, RSB) -- Reset of FIFO A (B) is accomplished whenever RSA
(
RSB) input is taken to a LOW state. During reset, the internal read and write
pointers associated with the FIFO are set to the first location. A reset is required
after power-up before a write operation can take place. The Full Flag,
FFA
(
FFB) will be reset to HIGH after t
RSF
. The Empty Flag,
EFA (EFB) will be reset
to LOW after t
RSF
. During reset, the output register is initialized to all zeros.
Write Clock (WCLKA, WCLKB) -- A write cycle to Array A (B) is initiated
on the LOW-to-HIGH transition of WCLKA (WCLKB). Data set-up and hold
times must be met with respect to the LOW-to-HIGH transition of WCLKA
(WCLKB). The Full Flag,
FFA (FFB) is synchronized with respect to the
LOW-to-HIGH transition of the Write Clock, WCLKA (WCLKB).
The Write and Read clock can be asynchronous or coincident.
Write Enable (
WENA, WENB) -- When WENA (WENB) is LOW, data can
be loaded into the input register of RAM Array A (B) on the LOW-to-HIGH
transition of every Write Clock, WCLKA (WCLKB). Data is stored in Array A
(B) sequentially and independently of any on-going read operation.
When
WENA (WENB) is HIGH, the input register holds the previous data
and no new data is allowed to be loaded into the register.
To prevent data overflow,
FFA (FFB) will go LOW, inhibiting further write
operations. Upon the completion of a valid read cycle, the
FFA (FFB) will go
HIGH after t
WFF
, allowing a valid write to begin.
WENA (WENB) is ignored when
FIFO A (B) is full.
Read Clock (RCLKA, RCLKB) --
Data can be read from Array A (B) on the LOW-to-HIGH transition of
RCLKA (RCLKB). The Empty Flag,
EFA (EFB) is synchronized with respect
to the LOW-to-HIGH transition of RCLKA (RCLKB).
The Write and Read Clock can be asynchronous or coincident.
7
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
Figure 2. Reset Timing
NOTES:
1. After reset, QA
0
- QA
7
(QB
0
- QB
7
) will be LOW if
OEA (OEB) = 0 and tri-state if OEA (OEB) = 1.
2. The clocks RCLKA, WCLKA (RCLKB, WCLKB) can be free-running during reset.
Figure 3. Write Cycle Timing
NOTE:
1. t
SKEW1
is the minimum time between a rising RCLKA (RCLKB) edge and a rising WCLKA (WCLKB) edge for
FFA (FFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
SKEW1
, then
FFA (FFB) may not change state until the next WCLKA (WCLKB)
edge.
t
DH
t
ENH
t
SKEW1(1)
t
CLK
t
CLKH
t
CLKL
t
DS
t
WFF
WCLKA (WCLKB)
(DA
0
- DA
7
DB
0
- DB
7
)
WENA (WENB)
F F A (F F B)
RCLKA (RCLKB)
RENA (RENB)
NO OPERATION
6360 drw05
DATA IN VALID
t
WFF
t
ENS
t
RS
t
RSR
RSA (RSB)
RENA(RENB)
t
RSF
t
RSF
OEA (OEB) = 1
OEA (OEB) = 0
(1)
EF A
(
EF B)
QA
0
- QA
7
(QB
0
- QB
7
)
6360 drw04
WENA (WENB)
t
RSS
t
RSF
t
RSR
t
RSS
F F A
(
F F B)
8
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
Figure 4. Read Cycle Timing
NOTE:
1. When t
SKEW1
minimum specification, t
FRL
= t
CLK
+ t
SKEW1
When
t
SKEW1
< minimum specification, t
FRL
= 2t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
The Latency Timings apply only at the Empty Boundary (
EFA, EFB = LOW).
Figure 5. First Data Word Latency Timing
NOTE:
1. t
SKEW1
is the minimum time between a rising WCLKA (WCLKB) edge and a rising RCLKA (RCLKB) edge for
EFA (EFB) to change during the current clock cycle. If the time
between the rising edge of RCLKA (RCLKB) and the rising edge of WCLKA (WCLKB) is less than t
SKEW1
, then
EFA (EFB) may not change state until the next RCLKA (RCLKB)
edge.
t
ENH
t
ENS
NO OPERATION
t
OLZ
VALID DATA
t
SKEW1
(1)
t
CLK
t
CLKH
t
CLKL
t
REF
t
REF
t
A
t
OE
t
OHZ
RCLKA (RCLKB)
RENA (RENB)
EF A (EF B)
QA
0
- QA
7
(QB
0
- QB
7
)
OEA (OEB)
WCLKA, WCLKB
WENA (WENB)
6360 drw06
t
DS
D
0
(First Valid Write)
t
SKEW1
D
0
D
1
D
3
D
2
D
1
t
ENS
t
FRL
(1)
t
REF
t
A
t
OLZ
t
OE
t
A
WCLKA (WCLKB)
DA
0
- DA
7
(DB
0
- DB
7
)
RCLKA (RCLKB)
EF A (EF B)
RENA (RENB)
QA
0
- QA
7
(QB
0
- QB
7
)
OEA (OEB)
WENA (WENB)
6360 drw07
t
ENS
9
IDT72V10071/72V11071/72V12071/72V13071/72V14071 3.3V, MULTIMEDIA FIFO
DUAL 256 x 8, 512 x 8, 1024 x 8, 2048 x 8 and 4096 x 8
INDUSTRIAL TEMPERATURE RANGE
Figure 6. Full Flag Timing
Figure 7. Empty Flag Timing
NOTE:
1. When t
SKEW1
minimum specification, t
FRL
maximum = t
CLK
+ t
SKEW1
When
t
SKEW1
< minimum specification, t
FRL
maximum = 2t
CLK
+ t
SKEW1
or t
CLK
+ t
SKEW1
The Latency Timings apply only at the Empty Boundary (
EFA, EFB = LOW).
WCLKA
(WCLKB)
DA
0
- DA
7
(DB
0
- DB
7
)
FFA (FFB)
WENA
(
WENB)
RCLKA
(RCLKB)
RENA
(
RENB)
QA
0
- QA
7
(QB
0
- QB
7
)
OEA
(
OEB)
6360 drw08
t
SKEW1
t
DS
t
SKEW1
t
ENH
t
ENH
NEXT DATA READ
DATA READ
t
WFF
t
WFF
t
WFF
t
ENS
t
ENS
DATA IN OUTPUT REGISTER
LOW
NO WRITE
NO WRITE
t
A
t
A
t
ENS
t
ENS
t
ENH
NO WRITE
t
DH
t
A
t
DS
t
DS
t
ENS
t
ENH
t
ENS
t
ENH
DATA WRITE 2
WCLKA (WCLKB)
DA
0
- DA
7
(DB
0
- DB
7
)
RCLKA (RLCKB)
EFA (EFB)
RENA
(
RENB)
OEA (OEB)
QA
0
- QA
7
(QB
0
- QB
7
)
DATA READ
t
SKEW1
(1)
t
FRL
t
FRL
DATA IN OUTPUT REGISTER
(1)
t
SKEW1
LOW
t
REF
t
REF
t
REF
WENA, (WENB)
6360 drw09
DATA WRITE 1
10
CORPORATE HEADQUARTERS
for SALES:
for TECH SUPPORT:
2975 Stender Way
800-345-7015 or 408-727-6116
(408) 330-1753
Santa Clara, CA 95054
fax: 408-492-8674
FIFOhelp@idt.com
www.idt.com
ORDERING INFORMATION
6360 drw10
XXXXX
IDT
Device Type
X XX
XX
Power Speed
Package
Process/
Temperature
Range
Clock Cycle Time (t
CLK
),
speed in Nanoseconds
I
Industrial (-40
C to +85C)
TF
Plastic Quad Flatpack (STQFP, PP64-1)
15
Industrial
L
Low Power
72V10071
72V11071
72V12071
72V13071
72V14071
256 x 8
3.3 Volt DUAL Multimedia FIFO
512 x 8
3.3 Volt DUAL Multimedia FIFO
1,024 x 8
3.3 Volt DUAL Multimedia FIFO
2,048 x 8
3.3 Volt DUAL Multimedia FIFO
4,096 x 8
3.3 Volt DUAL Multimedia FIFO
X