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Электронный компонент: 72V15165

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1
APRIL 2003
PRELIMINARY
IDT72V11165, IDT72V12165
IDT72V13165, IDT72V14165
IDT72V15165
IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.
INDUSTRIAL TEMPERATURE RANGE
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
DSC-6359/1
3.3 VOLT MULTIMEDIA FIFO
256 x 16, 512 x 16,
1,024 x 16, 2,048 x 16,
and 4,096 x 16
FEATURES:




256 x 16-bit organization array (IDT72V11165)




512 x 16-bit organization array (IDT72V12165)




1,024 x 16-bit organization array (IDT72V13165)




2,048 x 16-bit organization array (IDT72V14165)




4,096 x 16-bit organization array (IDT72V15165)




15 ns read/write cycle time




5V input tolerant




Independent Read and Write Clocks




Empty/Full and Half-Full flag capability




Output enable puts output data bus in high-impedance state




Available in a 64-lead thin quad flatpack (10x10mm and 14x14mm
TQFP)




Industrial temperature range (40


C to +85C)
FUNCTIONAL BLOCK DIAGRAM
RESET LOGIC
FLAG OUTPUTS
WRITE
CONTROL
READ
CONTROL
FIFO ARRAY
WCLK
WEN
D
0
- D
15
Data In
x16
RS
EF
HF
Q
0
- Q
15
Data Out
x16
RCLK
REN
6359 drw01
FF
OE
DESCRIPTION:
The IDT72V11165/72V12165/72V13165/72V14165/72V15165 devices
are First-In, First-Out (FIFO) memories with clocked read and write controls.
These FIFOs have 16-bit input and output ports. The input port is controlled
by a free-running clock (WCLK), and an input enable pin (
WEN). Data is written
into the Multimedia FIFO on every clock when
WEN is asserted. The output port
is controlled by another clock pin (RCLK) and another enable pin (
REN). The
Read Clock (RCLK) can be tied to the Write Clock for single clock operation or
the two clocks can run asynchronous of one another for dual-clock operation.
An Output Enable pin (
OE) is provided on the read port for three-state control
of the output.
These Multimedia FIFOs support three fixed flags: Empty Flag (
EF), Full
Flag (
FF), and Half Full Flag (HF).
2
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
PIN CONFIGURATIONS
STQFP (PP64-1, order code: TF)
TOP VIEW
PIN 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
GND
RCLK
REN
OE
RS
V
CC
GND
EF
GND
Q
1
V
CC
Q
2
Q
3
GND
Q
4
Q
5
V
CC
Q
6
Q
7
GND
Q
8
Q
9
Q
10
Q
11
GND
Q
12
V
CC
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
D
10
D
11
D
12
D
13
D
14
D
15
GND
DNC
(1)
WCLK
WEN
V
CC
FF
HF
Q
15
GND
Q
14
Q
13
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
6359 drw02
GND
GND
V
CC
DNC
(1)
GND
D
0
V
CC
Q
0
DNC
(1)
DNC
(1)
DNC
(1)
PIN DESCRIPTION
Symbol
Name
I/O
Description
D0D15
Data Inputs
I
Data inputs for an 16-bit bus.
EF
Empty Flag
O
EF indicates whether or not the FIFO memory is empty.
FF
Full Flag
O
FF indicates whether or not the FIFO memory is full.
HF
Half-Full Flag
O
The device is more than half full when
HF is LOW.
OE
Output Enable
I
When
OE is LOW, the data output bus is active. If OE is HIGH, the output data bus will be in a high-impedance
state.
Q0Q15
Data Outputs
O
Data outputs for an 16-bit bus.
RCLK
Read Clock
I
When
REN is LOW, data is read from the FIFO on a LOW-to-HIGH transition of RCLK, if the FIFO is not empty.
REN
Read Enable
I
When
REN is LOW, data is read from the FIFO on every LOW-to-HIGH transition of RCLK. When REN is HIGH,
the output register holds the previous data. Data will not be read from the FIFO if the
EF is LOW.
RS
Reset
I
When
RS is set LOW, internal read and write pointers are set to the first location of the RAM array, FF
goes HIGH, and
EF goes LOW. A reset is required before an initial WRITE after power-up.
WCLK
Write Clock
I
When
WEN is LOW, data is written into the FIFO on a LOW-to-HIGH transition of WCLK, if the FIFO is not full.
WEN
Write Enable
I
When
WEN is LOW, data is written into the FIFO on every LOW-to-HIGH transition of WCLK. When WEN is
HIGH, the FIFO holds the previous data. Data will not be written into the FIFO if the
FF is LOW.
V
CC
Power
I
+3.3V power supply pins.
GND
Ground
I
Ground pins.
NOTE:
1. DNC = Do Not Connect.
3
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
RECOMMENDED DC OPERATING
CONDITIONS
Symbol
Parameter
Min.
Typ.
Max.
Unit
V
CC
Supply Voltage Industrial
3.0
3.3
3.6
V
GND
Supply Voltage
0
0
0
V
V
IH
Input High Voltage Industrial
2.0
--
5.5
V
V
IL
(1)
Input Low Voltage Industrial
-0.5
--
0.8
V
T
A
Operating Temperature
-40
85
C
Industrial
NOTE:
1. 1.5V undershoots are allowed for 10ns once per cycle.
Symbol
Rating
Industrial
Unit
V
TERM
(2)
Terminal Voltage
0.5 to +5
V
with respect to GND
T
STG
Storage
55 to +125
C
Temperature
I
OUT
DC Output Current
50 to +50
mA
Symbol
Parameter
(1)
Conditions
Max.
Unit
C
IN
(2)
Input
V
IN
= 0V
10
pF
Capacitance
C
OUT
(1,2)
Output
V
OUT
= 0V
10
pF
Capacitance
CAPACITANCE
(T
A
= +25
C, f = 1.0MHz)
NOTES:
1. With output deselected, (
OE
V
IH
).
2. Characterized values, not currently tested.
IDT72V11165
IDT72V12165
IDT72V13165
IDT72V14165
IDT72V15165
Industrial
t
CLK
= 15 ns
Symbol
Parameter
Min.
Typ.
Max.
Unit
I
LI
(1)
Input Leakage Current (any input)
1
--
1
A
I
LO
(2)
Output Leakage Current
10
--
10
A
V
OH
Output Logic "1" Voltage, I
OH
= 2 mA
2.4
--
--
V
V
OL
Output Logic "0" Voltage, I
OL
= 8 mA
--
--
0.4
V
I
CC1
(3,4,5)
Active Power Supply Current
--
--
30
mA
I
CC2
(3,6)
Standby Current
--
--
5
mA
DC ELECTRICAL CHARACTERISTICS
(Industrial: V
CC
= 3.3V
0.3V, TA = -40C to +85C)
NOTES:
1. Measurements with 0.4
V
IN
V
CC
.
2.
OE
V
IH,
0.4
V
OUT
V
CC
.
3. Tested with outputs disabled (I
OUT
= 0).
4. RCLK and WCLK toggle at 20 MHZ and data inputs switch at 10 MHz.
5. Typical I
CC1
= 2.04 + 0.88*f
S
+ 0.02*C
L
*f
S
(in mA).
These equations are valid under the following conditions:
V
CC
= 3.3V, T
A
= 25
C, f
S
= WCLK frequency = RCLK frequency (in MHz, using TTL levels), data switching at f
S
/2, C
L
= capacitive load (in pF).
6. All Inputs = V
CC
- 0.2V or GND + 0.2V, except RCLK and WCLK, which toggle at 20 MHz.
ABSOLUTE MAXIMUM RATINGS
NOTES:
1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. V
CC
terminal only.
4
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
AC ELECTRICAL CHARACTERISTICS
(Industrial: VCC = 3.3V 0.3V, TA = -40C to +85C)
Industrial
IDT72V11165
IDT72V12165
IDT72V13165
IDT72V14165
IDT72V15165
Symbol
Parameter
Min.
Max.
Unit
f
S
Clock Cycle Frequency
--
66.7
MHz
t
A
Data Access Time
2
10
ns
t
CLK
Clock Cycle Time
15
--
ns
t
CLKH
Clock HIGH Time
6
--
ns
t
CLKL
Clock LOW Time
6
--
ns
t
DS
Data Set-up Time
4
--
ns
t
DH
Data Hold Time
1
--
ns
t
ENS
Enable Set-up Time
4
--
ns
t
ENH
Enable Hold Time
1
--
ns
t
RS
Reset Pulse Width
(2)
15
--
ns
t
RSS
Reset Set-up Time
10
--
ns
t
RSR
Reset Recovery Time
10
--
ns
t
RSF
Reset to Flag and Output Time
--
15
ns
t
OLZ
Output Enable to Output in Low-Z
(3)
0
--
ns
t
OE
Output Enable to Output Valid
3
8
ns
t
OHZ
Output Enable to Output in High-Z
(3)
3
8
ns
t
WFF
Write Clock to Full Flag
--
10
ns
t
REF
Read Clock to Empty Flag
--
10
ns
t
HF
Clock to Half-Full Flag
--
20
ns
t
SKEW1
Skew time between Read Clock & Write Clock for
FF and EF
6
--
ns
Input Pulse Levels
GND to 3.0V
Input Rise/Fall Times
3ns
Input Timing Reference Levels
1.5V
Output Reference Levels
1.5V
Output Load
See Figure 1
AC TEST CONDITIONS
Figure 1. Output Load
* Includes jig and scope capacitances.
30pF*
330
3.3V
510
D.U.T.
6359 drw03
NOTES:
1. Industrial temperature range product for the 15ns speed grade available.
2. Pulse widths less than minimum values are not allowed.
3. Values guaranteed by design, not currently tested.
5
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
FUNCTIONAL DESCRIPTION
WRITE/READ AND FLAG FUNCTION
To write data into to the FIFO, Write Enable (
WEN) must be LOW. Data
presented to the DATA IN lines will be clocked into the FIFO on subsequent
transitions of the Write Clock (WCLK). After the first write is performed, the Empty
Flag (
EF) will go HIGH. Subsequent writes will continue to fill up the FIFO.
If one continued to write data into the FIFO, and we assumed no read
operations were taking place, the Half-Full Flag (
HF) would toggle to LOW once
the 129th (72V11165), 257th (72V12165), 513th (72V13165), 1,025th
(72V14165), and 2,049th (72V15165) word respectively was written into the
FIFO.
When the FIFO is full, the Full Flag (
FF) will go LOW, inhibiting further write
operations. If no reads are performed after a reset,
FF will go LOW after D writes
to the FIFO. D = 256 writes for the IDT72V11165, 512 for the IDT72V12165,
1,024 for the IDT72V13165, 2,048 for the IDT72V14165 and 4,096 for the
IDT72V15165, respectively.
If the FIFO is full, the first read operation will cause
FF to go HIGH.
Subsequent read operations will cause the Half-Full Flag (
HF) to go HIGH.
Continuing read operations will cause the FIFO to be empty. When the last word
has been read from the FIFO, the
EF will go LOW inhibiting further read
operations.
REN is ignored when the FIFO is empty.
SIGNAL DESCRIPTIONS:
INPUTS:
DATA IN (D
0
- D
15
)
Data inputs for 16-bit wide data.
CONTROLS:
RESET (
RS)
Reset is accomplished whenever the Reset (
RS) input is taken to a LOW
state. During reset, both internal read and write pointers are set to the first
location. A reset is required after power-up before a write operation can take
place. The Half-Full Flag (
HF) to HIGH after t
RSF
. The Full Flag (
FF) will reset
to HIGH. The Empty Flag (
EF) will reset to LOW. During reset, the output register
is initialized to all zeros and the offset registers are initialized to their default values.
WRITE CLOCK (WCLK)
A write cycle is initiated on the LOW-to-HIGH transition of the Write Clock
(WCLK). Data setup and hold times must be met with respect to the LOW-to-HIGH
transition of WCLK.
The Write and Read Clocks can be asynchronous or coincident.
WRITE ENABLE (
WEN)
When the
WEN input is LOW, data may be loaded into the FIFO RAM array
on the rising edge of every WCLK cycle if the device is not full. Data is stored
in the RAM array sequentially and independently of any ongoing read
operation.
When
WEN is HIGH, no new data is written in the RAM array on each WCLK
cycle.
To prevent data overflow,
FF will go LOW, inhibiting further write operations.
Upon the completion of a valid read cycle,
FF will go HIGH allowing a write to
occur. The
FF flag is updated on the rising edge of WCLK.
READ CLOCK (RCLK)
Data can be read on the outputs on the LOW-to-HIGH transition of the Read
Clock (RCLK), when Output Enable (
OE) is set LOW.
The Write and Read Clocks can be asynchronous or coincident.
READ ENABLE (
REN)
When Read Enable is LOW, data is loaded from the RAM array into the output
register on the rising edge of every RCLK cycle if the device is not empty.
When the
REN input is HIGH, the output register holds the previous data and
no new data is loaded into the output register. The data outputs Q
0
-Q
n
maintain
the previous data value.
Every word accessed at Q
n
, including the first word written to an empty FIFO,
must be requested using
REN. When the last word has been read from the FIFO,
the Empty Flag (
EF) will go LOW, inhibiting further read operations. REN is
ignored when the FIFO is empty. Once a write is performed,
EF will go HIGH
allowing a read to occur. The
EF flag is updated on the rising edge of RCLK.
OUTPUT ENABLE (
OE)
When Output Enable (
OE) is enabled (LOW), the parallel output buffers
receive data from the output register. When
OE is disabled (HIGH), the Q output
data bus is in a high-impedance state.
OUTPUTS
FULL FLAG/INPUT READY (
FF)
When the FIFO is full,
FF will go LOW, inhibiting further write operations.
When
FF is HIGH, the FIFO is not full. If no reads are performed after a reset,
FF will go LOW after D writes to the FIFO. D = 256 writes for the IDT72V11165,
512 for the IDT72V12165, 1,024 for the IDT72V13165, 2,048 for the
IDT72V14165 and 4,096 for the IDT72V15165.
FF is synchronous and updated on the rising edge of WCLK.
EMPTY FLAG/OUTPUT READY (
EF)
When the FIFO is empty,
EF will go LOW, inhibiting further read operations.
When
EF is HIGH, the FIFO is not empty.
EF is synchronous and updated on the rising edge of RCLK.
HALF-FULL FLAG (
HF)
After half of the memory is filled, and at the LOW-to-HIGH transition of the next
write cycle, the Half-Full Flag goes LOW and will remain set until the difference
between the write pointer and read pointer is less than or equal to one half of
the total memory of the device. The Half-Full Flag (
HF) is then reset to HIGH
by the LOW-to-HIGH transition of the Read Clock (RCLK). The
HF is
asynchronous.
DATA OUTPUTS (Q0-Q15)
Data outputs for 16-bit wide data.
6
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
Figure 2. Reset Timing
(1)
RS
REN, WEN
HF
Q
0
- Q
15
OE = 0
OE = 1
6359 drw04
RCLK, WCLK
FF
EF
IDT Standard Mode
(2)
(1)
t
RSF
t
RSF
t
RSF
t
RSF
t
RSR
t
RS
IDT Standard Mode
NOTES:
1. The clocks (RCLK, WCLK) can be free-running asynchronously or coincidentally.
2. After reset, the outputs will be LOW if
OE = 0 and high-impedanced if OE = 1.
NOTE:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus t
WFF
. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than tSKEW1, then the
FF deassertion time may be delayed an extra WCLK cycle.
Figure 3. Full Flag Timing
D
0
- D
15
WEN
RCLK
FF
REN
t
ENH
t
ENH
Q
0
- Q
15
DATA READ
NEXT DATA READ
DATA IN OUTPUT REGISTER
LOW
OE
t
SKEW1
DATA WRITE
6359 drw24
WCLK
NO WRITE
1
2
1
2
t
DS
NO WRITE
t
WFF
t
WFF
t
WFF
t
A
t
ENS
t
ENS
t
SKEW1
t
DS
t
A
Wd
(1)
(1)
7
IDT72V11165/72V12165/72V13165/72V14165/72V15165 3.3V MULTIMEDIA FIFO
256 x 16, 512 x 16, 1,024 x 16, 2,048 x 16 and 4,096 x 16
INDUSTRIAL
TEMPERATURE RANGE
NOTE:
1. t
SKEW1
is the minimum time between a rising WCLK edge and a rising RCLK edge to guarantee that
EF will go HIGH after one RCLK cycle plus t
REF
. If the time between the rising
edge of WCLK and the rising edge of RCLK is less than t
SKEW1
. then the
EF deassertion may be delayed an extra RCLK cycle.
Figure 5. Read Cycle Timing
NO OPERATION
RCLK
REN
EF
t
CLKL
t
ENH
t
REF
LAST WORD
t
A
t
OLZ
t
OE
Q
0
-
Q
15
OE
WCLK
WEN
6359 drw26
D
0
-
D
15
t
ENS
t
ENS
t
ENH
t
DS
t
DH
FIRST WORD
t
OHZ
t
CLK
1
2
t
REF
t
SKEW1
t
CLKH
(1)
Figure 4. Write Cycle Timing
NOTE:
1. t
SKEW1
is the minimum time between a rising RCLK edge and a rising WCLK edge to guarantee that
FF will go HIGH after one WCLK cycle plus t
RFF
. If the time between the rising
edge of RCLK and the rising edge of WCLK is less than t
SKEW1
. then the
FF deassertion may be delayed an extra WCLK cycle.
WCLK
D
0
-
D
15
WEN
FF
RCLK
REN
t
DS
t
WFF
t
WFF
DATA IN VALID
NO OPERATION
(1)
t
SKEW1
6359 drw25
t
ENS
t
DH
t
ENH
1
2
t
CLKH
t
CLKL
t
CLK
8
CORPORATE HEADQUARTERS
for SALES:
for TECH SUPPORT:
2975 Stender Way
800-345-7015 or 408-727-6116
(408) 330-1753
Santa Clara, CA 95054
fax: 408-492-8674
FIFOhelp@idt.com
www.idt.com
IDT
XXXXX
Device Type
X
Power
XX
Speed
X
Package
X
Clock Cycle Time (t
CLK
)
Speed in Nanoseconds
Process /
Temperature
Range
6359 drw32
Industrial (-40
C to +85C)
I
TF
Slim Thin Plastic Quad Flatpack (STQFP, PP64-1)
15
L
Low Power
72V11165
72V12165
72V13165
72V14165
72V15165
256 x 16
3.3V Multimedia FIFO
512 x 16
3.3V Multimedia FIFO
1,024 x 16
3.3V Multimedia FIFO
2,048 x 16
3.3V Multimedia FIFO
4,096 x 16
3.3V Multimedia FIFO
Industrial
ORDERING INFORMATION